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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761136223; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cJarjOHnzMQr4ZfDR1YaDT6/LXUlXROKNryhb0ckRQs=; b=PKJLWoqwajol/X1Lifur74jU7G9ku1lCZkM3UclbrTdE8e07y19uExH4LJi8UTaVMnWVwQ 9FzADtYzB5urt6dsIxpxIPa7+xJZ5ZbgAL8d9z247u4cS84KsFFVuhFtO7B2E1FsSo9COg UoErXzM6mDRWq1QLCGPGRVfMjJTwpPQ= X-MC-Unique: 13CcXV6BPDuAXbnFzozk-w-1 X-Mimecast-MFC-AGG-ID: 13CcXV6BPDuAXbnFzozk-w_1761136216 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 06/16] hw/arm/ast27x0: Share single UART set across PSP, SSP, and TSP Date: Wed, 22 Oct 2025 14:29:43 +0200 Message-ID: <20251022122953.877335-7-clg@redhat.com> In-Reply-To: <20251022122953.877335-1-clg@redhat.com> References: <20251022122953.877335-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761136308107154100 From: Jamin Lin In the original model, each subsystem (PSP, SSP, and TSP) created its own set of 13 UART devices, resulting in a total of 39 UART instances. However, on real AST2700 hardware, there is only one set of 13 UARTs shared among all processors. This commit reworks the UART handling to correctly model the shared hardware design. The PSP now creates the full set of 13 UART instances, while the SSP and TSP link to the corresponding shared UART device through object properties. Changes include: - Add "DEFINE_PROP_LINK("uart", ...)" and "DEFINE_PROP_INT32("uart-dev", ..= .)" to allow each coprocessor to reference a specific shared UART instance. - Modify SSP to link to PSP=E2=80=99s UART4, and TSP to link to PSP=E2=80= =99s UART7. - Introduce "uart_alias" to remap the UART=E2=80=99s MMIO region into the c= oprocessor=E2=80=99s memory space. - Redirect the UART interrupt to the coprocessor=E2=80=99s NVIC, replacing = the default routing to the PSP=E2=80=99s GIC. With this change, only one set of 13 UART devices is instantiated by the PS= P, while the SSP and TSP reuse them via aliasing and shared interrupt routing, matching the real AST2700 hardware behavior. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-7-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_coprocessor.h | 6 +++--- hw/arm/aspeed_ast27x0-fc.c | 24 ++++++++++++------------ hw/arm/aspeed_ast27x0-ssp.c | 29 ++++++++++++----------------- hw/arm/aspeed_ast27x0-tsp.c | 29 ++++++++++++----------------- hw/arm/aspeed_coprocessor_common.c | 3 +++ 5 files changed, 42 insertions(+), 49 deletions(-) diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h index c1f2c549c323..4a50f688ecdc 100644 --- a/include/hw/arm/aspeed_coprocessor.h +++ b/include/hw/arm/aspeed_coprocessor.h @@ -19,13 +19,15 @@ struct AspeedCoprocessorState { MemoryRegion sdram; MemoryRegion *sram; MemoryRegion sram_alias; + MemoryRegion uart_alias; MemoryRegion scu_alias; Clock *sysclk; =20 AspeedSCUState *scu; AspeedSCUState scuio; AspeedTimerCtrlState timerctrl; - SerialMM uart[ASPEED_UARTS_NUM]; + SerialMM *uart; + int uart_dev; }; =20 #define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor" @@ -39,8 +41,6 @@ struct AspeedCoprocessorClass { const char * const *valid_cpu_types; const hwaddr *memmap; const int *irqmap; - int uarts_base; - int uarts_num; }; =20 struct Aspeed27x0CoprocessorState { diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index ba43a4620760..99af87dbd7bd 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -93,6 +93,10 @@ static bool ast2700fc_ca35_init(MachineState *machine, E= rror **errp) AST2700FC_HW_STRAP2, &error_abort); aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART12, sc->uarts_base, sc->uarts_num, serial_hd(0)); + aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART4, sc->uarts_base, + sc->uarts_num, serial_hd(1)); + aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base, + sc->uarts_num, serial_hd(2)); if (!qdev_realize(DEVICE(&s->ca35), NULL, errp)) { return false; } @@ -115,8 +119,6 @@ static bool ast2700fc_ca35_init(MachineState *machine, = Error **errp) =20 static bool ast2700fc_ssp_init(MachineState *machine, Error **errp) { - AspeedCoprocessorState *soc; - AspeedCoprocessorClass *sc; Ast2700FCState *s =3D AST2700A1FC(machine); AspeedSoCState *psp =3D ASPEED_SOC(&s->ca35); =20 @@ -132,10 +134,10 @@ static bool ast2700fc_ssp_init(MachineState *machine,= Error **errp) object_property_set_link(OBJECT(&s->ssp), "memory", OBJECT(&s->ssp_memory), &error_abort); =20 - soc =3D ASPEED_COPROCESSOR(&s->ssp); - sc =3D ASPEED_COPROCESSOR_GET_CLASS(soc); - aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART4, sc->uarts_base, - sc->uarts_num, serial_hd(1)); + object_property_set_link(OBJECT(&s->ssp), "uart", + OBJECT(&psp->uart[4]), &error_abort); + object_property_set_int(OBJECT(&s->ssp), "uart-dev", ASPEED_DEV_UART4, + &error_abort); object_property_set_link(OBJECT(&s->ssp), "sram", OBJECT(&psp->sram), &error_abort); object_property_set_link(OBJECT(&s->ssp), "scu", @@ -149,8 +151,6 @@ static bool ast2700fc_ssp_init(MachineState *machine, E= rror **errp) =20 static bool ast2700fc_tsp_init(MachineState *machine, Error **errp) { - AspeedCoprocessorState *soc; - AspeedCoprocessorClass *sc; Ast2700FCState *s =3D AST2700A1FC(machine); AspeedSoCState *psp =3D ASPEED_SOC(&s->ca35); =20 @@ -166,10 +166,10 @@ static bool ast2700fc_tsp_init(MachineState *machine,= Error **errp) object_property_set_link(OBJECT(&s->tsp), "memory", OBJECT(&s->tsp_memory), &error_abort); =20 - soc =3D ASPEED_COPROCESSOR(&s->tsp); - sc =3D ASPEED_COPROCESSOR_GET_CLASS(soc); - aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base, - sc->uarts_num, serial_hd(2)); + object_property_set_link(OBJECT(&s->tsp), "uart", + OBJECT(&psp->uart[7]), &error_abort); + object_property_set_int(OBJECT(&s->tsp), "uart-dev", ASPEED_DEV_UART7, + &error_abort); object_property_set_link(OBJECT(&s->tsp), "sram", OBJECT(&psp->sram), &error_abort); object_property_set_link(OBJECT(&s->tsp), "scu", diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 577a3379c6c0..d12a9b8459c2 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -133,16 +133,10 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj) { Aspeed27x0CoprocessorState *a =3D ASPEED27X0SSP_COPROCESSOR(obj); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(obj); - AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); - int i; =20 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); =20 - for (i =3D 0; i < sc->uarts_num; i++) { - object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M= M); - } - object_initialize_child(obj, "intc0", &a->intc[0], TYPE_ASPEED_2700SSP_INTC); object_initialize_child(obj, "intc1", &a->intc[1], @@ -165,7 +159,6 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *= dev_soc, Error **errp) AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); DeviceState *armv7m; g_autofree char *sdram_name =3D NULL; - int uart; int i; =20 if (!clock_has_source(s->sysclk)) { @@ -244,15 +237,19 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState= *dev_soc, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i, qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i= )); } + /* UART */ - for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { - if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], - sc->memmap[uart], errp)) { - return; - } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, - aspeed_soc_ast27x0ssp_get_irq(s, uart)); - } + memory_region_init_alias(&s->uart_alias, OBJECT(s), "uart.alias", + &s->uart->serial.io, 0, + memory_region_size(&s->uart->serial.io)); + memory_region_add_subregion(s->memory, sc->memmap[s->uart_dev], + &s->uart_alias); + /* + * Redirect the UART interrupt to the NVIC, replacing the default rout= ing + * to the PSP's GIC. + */ + sysbus_connect_irq(SYS_BUS_DEVICE(s->uart), 0, + aspeed_soc_ast27x0ssp_get_irq(s, s->uart_dev)); =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl), "aspeed.timerctrl", @@ -283,8 +280,6 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClas= s *klass, dc->realize =3D aspeed_soc_ast27x0ssp_realize; =20 sc->valid_cpu_types =3D valid_cpu_types; - sc->uarts_num =3D 13; - sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast27x0ssp_irqmap; sc->memmap =3D aspeed_soc_ast27x0ssp_memmap; } diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index a7c141678fc2..5b75e1420639 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -133,16 +133,10 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj) { Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_COPROCESSOR(obj); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(obj); - AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); - int i; =20 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); =20 - for (i =3D 0; i < sc->uarts_num; i++) { - object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M= M); - } - object_initialize_child(obj, "intc0", &a->intc[0], TYPE_ASPEED_2700TSP_INTC); object_initialize_child(obj, "intc1", &a->intc[1], @@ -165,7 +159,6 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *= dev_soc, Error **errp) AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); DeviceState *armv7m; g_autofree char *sdram_name =3D NULL; - int uart; int i; =20 if (!clock_has_source(s->sysclk)) { @@ -244,15 +237,19 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState= *dev_soc, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i, qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i= )); } + /* UART */ - for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { - if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], - sc->memmap[uart], errp)) { - return; - } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, - aspeed_soc_ast27x0tsp_get_irq(s, uart)); - } + memory_region_init_alias(&s->uart_alias, OBJECT(s), "uart.alias", + &s->uart->serial.io, 0, + memory_region_size(&s->uart->serial.io)); + memory_region_add_subregion(s->memory, sc->memmap[s->uart_dev], + &s->uart_alias); + /* + * Redirect the UART interrupt to the NVIC, replacing the default rout= ing + * to the PSP's GIC. + */ + sysbus_connect_irq(SYS_BUS_DEVICE(s->uart), 0, + aspeed_soc_ast27x0tsp_get_irq(s, s->uart_dev)); =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl), "aspeed.timerctrl", @@ -283,8 +280,6 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClas= s *klass, dc->realize =3D aspeed_soc_ast27x0tsp_realize; =20 sc->valid_cpu_types =3D valid_cpu_types; - sc->uarts_num =3D 13; - sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast27x0tsp_irqmap; sc->memmap =3D aspeed_soc_ast27x0tsp_memmap; } diff --git a/hw/arm/aspeed_coprocessor_common.c b/hw/arm/aspeed_coprocessor= _common.c index 14e26bbe234e..f037d5b573fd 100644 --- a/hw/arm/aspeed_coprocessor_common.c +++ b/hw/arm/aspeed_coprocessor_common.c @@ -29,6 +29,9 @@ static const Property aspeed_coprocessor_properties[] =3D= { MemoryRegion *), DEFINE_PROP_LINK("scu", AspeedCoprocessorState, scu, TYPE_ASPEED_SCU, AspeedSCUState *), + DEFINE_PROP_LINK("uart", AspeedCoprocessorState, uart, TYPE_SERIAL_MM, + SerialMM *), + DEFINE_PROP_INT32("uart-dev", AspeedCoprocessorState, uart_dev, 0), }; =20 static void aspeed_coprocessor_class_init(ObjectClass *oc, const void *dat= a) --=20 2.51.0