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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761136207; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=A8fvnFldiTzr+/y70KNLcplQCpYUtA7dZ4ZVBCMkK9A=; b=JZmVzTQanu08AF4S5XrKrnUHTZvyEA48vFHjOWsa05fwDQ36Vn1gWGcWYRubDISIv6HdR3 xMhaQzwc+sHjIsIKzHrpfHafPso0d6EqvkimCBXqaO6CIw94ZrPQkdbekOME6UNGSlQoYU 433BNZaqTNG4iwh47eXmQWTg2LHirJs= X-MC-Unique: qeDJxTTQOBCEx3B62oGolQ-1 X-Mimecast-MFC-AGG-ID: qeDJxTTQOBCEx3B62oGolQ_1761136204 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 01/16] hw/arm/aspeed_ast27x0-ssp: Add SDRAM region and fix naming and size to 512MB Date: Wed, 22 Oct 2025 14:29:38 +0200 Message-ID: <20251022122953.877335-2-clg@redhat.com> In-Reply-To: <20251022122953.877335-1-clg@redhat.com> References: <20251022122953.877335-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761136289139158500 From: Jamin Lin Previously, the SSP memory was incorrectly modeled as "SRAM" with a 32 MB size. This change introduces a new sdram field in AspeedCoprocessorState and updates the realization logic accordingly. Rename from SRAM to SDRAM and correct size from 32MB to 512MB to match hardware. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-2-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_coprocessor.h | 1 + hw/arm/aspeed_ast27x0-ssp.c | 20 ++++++++++---------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h index d77655d65911..0c7168a89c15 100644 --- a/include/hw/arm/aspeed_coprocessor.h +++ b/include/hw/arm/aspeed_coprocessor.h @@ -16,6 +16,7 @@ struct AspeedCoprocessorState { DeviceState parent; =20 MemoryRegion *memory; + MemoryRegion sdram; MemoryRegion sram; Clock *sysclk; =20 diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 936c7c72e8f7..9f3a1933a066 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -16,10 +16,10 @@ #include "hw/arm/aspeed_soc.h" #include "hw/arm/aspeed_coprocessor.h" =20 -#define AST2700_SSP_RAM_SIZE (32 * MiB) +#define AST2700_SSP_SDRAM_SIZE (512 * MiB) =20 static const hwaddr aspeed_soc_ast27x0ssp_memmap[] =3D { - [ASPEED_DEV_SRAM] =3D 0x00000000, + [ASPEED_DEV_SDRAM] =3D 0x00000000, [ASPEED_DEV_INTC] =3D 0x72100000, [ASPEED_DEV_SCU] =3D 0x72C02000, [ASPEED_DEV_SCUIO] =3D 0x74C02000, @@ -165,7 +165,7 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *= dev_soc, Error **errp) AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(dev_soc); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); DeviceState *armv7m; - g_autofree char *sram_name =3D NULL; + g_autofree char *sdram_name =3D NULL; int uart; int i; =20 @@ -184,16 +184,16 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState= *dev_soc, Error **errp) OBJECT(s->memory), &error_abort); sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort); =20 - sram_name =3D g_strdup_printf("aspeed.dram.%d", - CPU(a->armv7m.cpu)->cpu_index); - - if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, - AST2700_SSP_RAM_SIZE, errp)) { + /* SDRAM */ + sdram_name =3D g_strdup_printf("aspeed.sdram.%d", + CPU(a->armv7m.cpu)->cpu_index); + if (!memory_region_init_ram(&s->sdram, OBJECT(s), sdram_name, + AST2700_SSP_SDRAM_SIZE, errp)) { return; } memory_region_add_subregion(s->memory, - sc->memmap[ASPEED_DEV_SRAM], - &s->sram); + sc->memmap[ASPEED_DEV_SDRAM], + &s->sdram); =20 /* SCU */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { --=20 2.51.0 From nobody Fri Nov 14 18:19:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761136211; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aWLaHec6OH8er+yCVkAR80rxv7wHU2S6lmmqzgzou4o=; b=PoKfHXKJoWtBkAvAdcShjdOGGK+gD2CKxvZZKKe/S6ae/xac3KctR0M2Hl2biAOcMkSP4l gW3iIHRKB0jPbqtU2FFMKvAyGc8EYO35QeqYNjBsyq8oeErl+vnuczA+6/K1Nai7Sfa14H P3cCP4A9yDqyb+oUJffgkHP6rnKEqoc= X-MC-Unique: lpzDsHizNVC-HhGqJyLbPA-1 X-Mimecast-MFC-AGG-ID: lpzDsHizNVC-HhGqJyLbPA_1761136207 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 02/16] hw/arm/aspeed_ast27x0-tsp: Add SDRAM region and fix naming and size to 512MB Date: Wed, 22 Oct 2025 14:29:39 +0200 Message-ID: <20251022122953.877335-3-clg@redhat.com> In-Reply-To: <20251022122953.877335-1-clg@redhat.com> References: <20251022122953.877335-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761136558573154100 From: Jamin Lin Previously, the TSP memory was incorrectly modeled as "SRAM" with a 32 MB size. Rename from SRAM to SDRAM and correct size from 32MB to 512MB to match hardware. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-3-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0-tsp.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 9318f8c86c51..caeb3392a8e6 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -16,10 +16,10 @@ #include "hw/arm/aspeed_soc.h" #include "hw/arm/aspeed_coprocessor.h" =20 -#define AST2700_TSP_RAM_SIZE (32 * MiB) +#define AST2700_TSP_SDRAM_SIZE (512 * MiB) =20 static const hwaddr aspeed_soc_ast27x0tsp_memmap[] =3D { - [ASPEED_DEV_SRAM] =3D 0x00000000, + [ASPEED_DEV_SDRAM] =3D 0x00000000, [ASPEED_DEV_INTC] =3D 0x72100000, [ASPEED_DEV_SCU] =3D 0x72C02000, [ASPEED_DEV_SCUIO] =3D 0x74C02000, @@ -165,7 +165,7 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *= dev_soc, Error **errp) AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(dev_soc); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); DeviceState *armv7m; - g_autofree char *sram_name =3D NULL; + g_autofree char *sdram_name =3D NULL; int uart; int i; =20 @@ -184,16 +184,16 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState= *dev_soc, Error **errp) OBJECT(s->memory), &error_abort); sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort); =20 - sram_name =3D g_strdup_printf("aspeed.dram.%d", - CPU(a->armv7m.cpu)->cpu_index); - - if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, - AST2700_TSP_RAM_SIZE, errp)) { + /* SDRAM */ + sdram_name =3D g_strdup_printf("aspeed.sdram.%d", + CPU(a->armv7m.cpu)->cpu_index); + if (!memory_region_init_ram(&s->sdram, OBJECT(s), sdram_name, + AST2700_TSP_SDRAM_SIZE, errp)) { return; } memory_region_add_subregion(s->memory, - sc->memmap[ASPEED_DEV_SRAM], - &s->sram); + sc->memmap[ASPEED_DEV_SDRAM], + &s->sdram); =20 /* SCU */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { --=20 2.51.0 From nobody Fri Nov 14 18:19:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761136214; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KA8xEAyx6y77z8VjzGcdEiGx9scJIiR54DJNfg8a8AQ=; b=Yf4fgStK9Q8K520PcsJo/CHj08Yq7CcwPrpRIofJ65fDxdju97Vds82g79AbD691urdLBG 41E6q3BTiF4C1r/9Af2ODoLVsGtJqtQ1QObjMrQmg/8FEHAZQ2DEaSnfI9pDk66l5MhYxG qYcRUWlzGtg8xXmm1mj52EOz998iK9A= X-MC-Unique: KMRJ_7PGPAChnfK2pRcIQw-1 X-Mimecast-MFC-AGG-ID: KMRJ_7PGPAChnfK2pRcIQw_1761136209 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 03/16] hw/arm/ast27x0: Add SRAM link and alias mapping for SSP coprocessor Date: Wed, 22 Oct 2025 14:29:40 +0200 Message-ID: <20251022122953.877335-4-clg@redhat.com> In-Reply-To: <20251022122953.877335-1-clg@redhat.com> References: <20251022122953.877335-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761136659062158500 From: Jamin Lin AST2700 has a 128KB SRAM, physically mapped at 0x10000000=E2=80=930x1001FFF= F for the PSP (CA35) processor. The SSP coprocessor shares this same SRAM but accesses it through a different address window at 0x70000000=E2=80=930x7001= FFFF. To model this shared-memory behavior in QEMU, this commit introduces a linked SRAM property and alias mapping between the PSP and SSP subsystems. Changes include: - Add a "MemoryRegion *sram" link and "MemoryRegion sram_alias" to AspeedCoprocessorState. - Register the new "sram" property in aspeed_coprocessor_common.c. - In aspeed_ast27x0-fc.c, connect the SSP coprocessor=E2=80=99s "sram" link= to the PSP=E2=80=99s SRAM region. - In aspeed_ast27x0-ssp.c, create an alias mapping for SRAM at 0x70000000 =E2=80=93 0x7001FFFF in the SSP=E2=80=99s memory map. This ensures that the SSP can correctly access the shared SRAM contents through its own address space while maintaining a consistent physical backing region. It also guarantees that the SRAM is realized before the SSP device, ensuring successful alias setup. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-4-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_coprocessor.h | 3 ++- hw/arm/aspeed_ast27x0-fc.c | 4 ++++ hw/arm/aspeed_ast27x0-ssp.c | 7 +++++++ hw/arm/aspeed_coprocessor_common.c | 2 ++ 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h index 0c7168a89c15..d9a5f517d7c7 100644 --- a/include/hw/arm/aspeed_coprocessor.h +++ b/include/hw/arm/aspeed_coprocessor.h @@ -17,7 +17,8 @@ struct AspeedCoprocessorState { =20 MemoryRegion *memory; MemoryRegion sdram; - MemoryRegion sram; + MemoryRegion *sram; + MemoryRegion sram_alias; Clock *sysclk; =20 AspeedSCUState scu; diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index a61ecff3909b..25e668a648fa 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -118,6 +118,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, E= rror **errp) AspeedCoprocessorState *soc; AspeedCoprocessorClass *sc; Ast2700FCState *s =3D AST2700A1FC(machine); + AspeedSoCState *psp =3D ASPEED_SOC(&s->ca35); + s->ssp_sysclk =3D clock_new(OBJECT(s), "SSP_SYSCLK"); clock_set_hz(s->ssp_sysclk, 200000000ULL); =20 @@ -134,6 +136,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, E= rror **errp) sc =3D ASPEED_COPROCESSOR_GET_CLASS(soc); aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART4, sc->uarts_base, sc->uarts_num, serial_hd(1)); + object_property_set_link(OBJECT(&s->ssp), "sram", + OBJECT(&psp->sram), &error_abort); if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) { return false; } diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 9f3a1933a066..66c4ef6d1b74 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -20,6 +20,7 @@ =20 static const hwaddr aspeed_soc_ast27x0ssp_memmap[] =3D { [ASPEED_DEV_SDRAM] =3D 0x00000000, + [ASPEED_DEV_SRAM] =3D 0x70000000, [ASPEED_DEV_INTC] =3D 0x72100000, [ASPEED_DEV_SCU] =3D 0x72C02000, [ASPEED_DEV_SCUIO] =3D 0x74C02000, @@ -195,6 +196,12 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState = *dev_soc, Error **errp) sc->memmap[ASPEED_DEV_SDRAM], &s->sdram); =20 + /* SRAM */ + memory_region_init_alias(&s->sram_alias, OBJECT(s), "sram.alias", + s->sram, 0, memory_region_size(s->sram)); + memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM], + &s->sram_alias); + /* SCU */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; diff --git a/hw/arm/aspeed_coprocessor_common.c b/hw/arm/aspeed_coprocessor= _common.c index 8a94b44f07f2..8322ad5eb544 100644 --- a/hw/arm/aspeed_coprocessor_common.c +++ b/hw/arm/aspeed_coprocessor_common.c @@ -25,6 +25,8 @@ static void aspeed_coprocessor_realize(DeviceState *dev, = Error **errp) static const Property aspeed_coprocessor_properties[] =3D { DEFINE_PROP_LINK("memory", AspeedCoprocessorState, memory, TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_LINK("sram", AspeedCoprocessorState, sram, TYPE_MEMORY_REG= ION, + MemoryRegion *), }; =20 static void aspeed_coprocessor_class_init(ObjectClass *oc, const void *dat= a) --=20 2.51.0 From nobody Fri Nov 14 18:19:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761136218; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nAgQ1I7e4bYUpQNPSKgwIRQqQ39LlJBUSouGvNb4faE=; b=KFZgmDiFMBFArl+egti0y57TdYNfpBBVEShQ6luyiDudUuta3sWk01OJwgISd3uwoUG37U 3rZeE2V13pM2S6+IKFbZWqIhVlN5qGveUjfW3+K/V7LLztCAgLKIyvtmHTptGRM6xmJg4f qJ+NRuHpaUcd9GlkxSXIRanggm7GYt8= X-MC-Unique: HjHAZ_GiM-mfoy2aTouE5Q-1 X-Mimecast-MFC-AGG-ID: HjHAZ_GiM-mfoy2aTouE5Q_1761136211 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 04/16] hw/arm/ast27x0: Add SRAM link and alias mapping for TSP coprocessor Date: Wed, 22 Oct 2025 14:29:41 +0200 Message-ID: <20251022122953.877335-5-clg@redhat.com> In-Reply-To: <20251022122953.877335-1-clg@redhat.com> References: <20251022122953.877335-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761136247062154100 From: Jamin Lin AST2700 has a 128KB SRAM, physically mapped at 0x10000000=E2=80=930x1001FFF= F for the PSP (CA35) processor. The TSP coprocessor shares this same SRAM but accesses it through a different address window at 0x70000000=E2=80=930x7001= FFFF. To model this shared-memory behavior in QEMU, this commit introduces a linked SRAM property and alias mapping between the PSP and TSP subsystems. Changes include: - Add the SRAM alias mapping at 0x70000000 in aspeed_ast27x0-tsp.c. - In aspeed_ast27x0-fc.c, connect the TSP coprocessor=E2=80=99s "sram" link= to the PSP=E2=80=99s SRAM region. - Ensure the alias region is initialized during TSP SoC realization so the TSP can correctly access shared SRAM through its own address space. This ensures that the TSP and PSP share the same physical SRAM backing. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-5-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0-fc.c | 4 ++++ hw/arm/aspeed_ast27x0-tsp.c | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index 25e668a648fa..dfac7d1e17b8 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -150,6 +150,8 @@ static bool ast2700fc_tsp_init(MachineState *machine, E= rror **errp) AspeedCoprocessorState *soc; AspeedCoprocessorClass *sc; Ast2700FCState *s =3D AST2700A1FC(machine); + AspeedSoCState *psp =3D ASPEED_SOC(&s->ca35); + s->tsp_sysclk =3D clock_new(OBJECT(s), "TSP_SYSCLK"); clock_set_hz(s->tsp_sysclk, 200000000ULL); =20 @@ -166,6 +168,8 @@ static bool ast2700fc_tsp_init(MachineState *machine, E= rror **errp) sc =3D ASPEED_COPROCESSOR_GET_CLASS(soc); aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base, sc->uarts_num, serial_hd(2)); + object_property_set_link(OBJECT(&s->tsp), "sram", + OBJECT(&psp->sram), &error_abort); if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) { return false; } diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index caeb3392a8e6..56b68adf541b 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -20,6 +20,7 @@ =20 static const hwaddr aspeed_soc_ast27x0tsp_memmap[] =3D { [ASPEED_DEV_SDRAM] =3D 0x00000000, + [ASPEED_DEV_SRAM] =3D 0x70000000, [ASPEED_DEV_INTC] =3D 0x72100000, [ASPEED_DEV_SCU] =3D 0x72C02000, [ASPEED_DEV_SCUIO] =3D 0x74C02000, @@ -195,6 +196,12 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState = *dev_soc, Error **errp) sc->memmap[ASPEED_DEV_SDRAM], &s->sdram); =20 + /* SRAM */ + memory_region_init_alias(&s->sram_alias, OBJECT(s), "sram.alias", + s->sram, 0, memory_region_size(s->sram)); + memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM], + &s->sram_alias); + /* SCU */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761136218; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=h+iSTY7ypTD5IhBhaGjoBU8rgZcYEQnS7JehcOzg5B0=; b=Rmcv1h+yayySDj3Zj0rv3X/fdaX/amplI8ZOysgcWHH0/9qtH+6kXqba4S39uDYyzJTR+6 rT7gmryf+XkoFt0DrFvT/YnyE7/aXtS9UOzV8x3244VbeEb3zNQQ+JUvsKT6Dj+7S2DZL6 sdsy6QrEBdFiQvhzEnkmZtL6ciWhUXc= X-MC-Unique: GOkRwBQZNYCdp5xdUN5D0g-1 X-Mimecast-MFC-AGG-ID: GOkRwBQZNYCdp5xdUN5D0g_1761136213 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 05/16] hw/arm/ast27x0: Share single SCU instance across PSP, SSP, and TSP Date: Wed, 22 Oct 2025 14:29:42 +0200 Message-ID: <20251022122953.877335-6-clg@redhat.com> In-Reply-To: <20251022122953.877335-1-clg@redhat.com> References: <20251022122953.877335-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761136472916158500 From: Jamin Lin AST2700 has a single SCU hardware block, memory-mapped at 0x12C02000=E2=80=930x12C03FFF from the perspective of the main CA35 process= or (PSP). The SSP and TSP coprocessors access this same SCU block at different addresses: 0x72C02000=E2=80=930x72C03FFF. Previously, each subsystem (PSP, SSP, and TSP) instantiated its own SCU device, resulting in three independent SCU instances in the QEMU model. In real hardware, however, only a single SCU exists and is shared among all processors. This commit reworks the SCU model to correctly reflect the hardware behavior by allowing SSP and TSP to reference the PSP=E2=80=99s SCU instanc= e. The following changes are introduced: - Add a scu property to AspeedCoprocessorState for linking the coprocessor to the PSP=E2=80=99s SCU instance. - Replace per-coprocessor SCU instantiation with a shared SCU link. - Add "MemoryRegion scu_alias" to model address remapping for SSP and TSP. - Create SCU alias regions in both SSP and TSP coprocessors and map them at 0x72C02000 to mirror the PSP=E2=80=99s SCU registers. - Ensure the SCU device in PSP is realized before SSP/TSP alias setup. With this change, PSP, SSP, and TSP now share a consistent SCU state, matching the single-SCU hardware design of AST2700. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-6-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_coprocessor.h | 4 ++-- hw/arm/aspeed_ast27x0-fc.c | 4 ++++ hw/arm/aspeed_ast27x0-ssp.c | 13 +++++-------- hw/arm/aspeed_ast27x0-tsp.c | 13 +++++-------- hw/arm/aspeed_coprocessor_common.c | 2 ++ 5 files changed, 18 insertions(+), 18 deletions(-) diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h index d9a5f517d7c7..c1f2c549c323 100644 --- a/include/hw/arm/aspeed_coprocessor.h +++ b/include/hw/arm/aspeed_coprocessor.h @@ -19,9 +19,10 @@ struct AspeedCoprocessorState { MemoryRegion sdram; MemoryRegion *sram; MemoryRegion sram_alias; + MemoryRegion scu_alias; Clock *sysclk; =20 - AspeedSCUState scu; + AspeedSCUState *scu; AspeedSCUState scuio; AspeedTimerCtrlState timerctrl; SerialMM uart[ASPEED_UARTS_NUM]; @@ -36,7 +37,6 @@ struct AspeedCoprocessorClass { =20 /** valid_cpu_types: NULL terminated array of a single CPU type. */ const char * const *valid_cpu_types; - uint32_t silicon_rev; const hwaddr *memmap; const int *irqmap; int uarts_base; diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index dfac7d1e17b8..ba43a4620760 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -138,6 +138,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, E= rror **errp) sc->uarts_num, serial_hd(1)); object_property_set_link(OBJECT(&s->ssp), "sram", OBJECT(&psp->sram), &error_abort); + object_property_set_link(OBJECT(&s->ssp), "scu", + OBJECT(&psp->scu), &error_abort); if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) { return false; } @@ -170,6 +172,8 @@ static bool ast2700fc_tsp_init(MachineState *machine, E= rror **errp) sc->uarts_num, serial_hd(2)); object_property_set_link(OBJECT(&s->tsp), "sram", OBJECT(&psp->sram), &error_abort); + object_property_set_link(OBJECT(&s->tsp), "scu", + OBJECT(&psp->scu), &error_abort); if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) { return false; } diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 66c4ef6d1b74..577a3379c6c0 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -137,9 +137,7 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj) int i; =20 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); - object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); - qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev); =20 for (i =3D 0; i < sc->uarts_num; i++) { object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M= M); @@ -203,11 +201,11 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState= *dev_soc, Error **errp) &s->sram_alias); =20 /* SCU */ - if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { - return; - } - aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0, - sc->memmap[ASPEED_DEV_SCU]); + memory_region_init_alias(&s->scu_alias, OBJECT(s), "scu.alias", + &s->scu->iomem, 0, + memory_region_size(&s->scu->iomem)); + memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU], + &s->scu_alias); =20 /* INTC */ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { @@ -285,7 +283,6 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClas= s *klass, dc->realize =3D aspeed_soc_ast27x0ssp_realize; =20 sc->valid_cpu_types =3D valid_cpu_types; - sc->silicon_rev =3D AST2700_A1_SILICON_REV; sc->uarts_num =3D 13; sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast27x0ssp_irqmap; diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 56b68adf541b..a7c141678fc2 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -137,9 +137,7 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj) int i; =20 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); - object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); - qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev); =20 for (i =3D 0; i < sc->uarts_num; i++) { object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M= M); @@ -203,11 +201,11 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState= *dev_soc, Error **errp) &s->sram_alias); =20 /* SCU */ - if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { - return; - } - aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0, - sc->memmap[ASPEED_DEV_SCU]); + memory_region_init_alias(&s->scu_alias, OBJECT(s), "scu.alias", + &s->scu->iomem, 0, + memory_region_size(&s->scu->iomem)); + memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU], + &s->scu_alias); =20 /* INTC */ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { @@ -285,7 +283,6 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClas= s *klass, dc->realize =3D aspeed_soc_ast27x0tsp_realize; =20 sc->valid_cpu_types =3D valid_cpu_types; - sc->silicon_rev =3D AST2700_A1_SILICON_REV; sc->uarts_num =3D 13; sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast27x0tsp_irqmap; diff --git a/hw/arm/aspeed_coprocessor_common.c b/hw/arm/aspeed_coprocessor= _common.c index 8322ad5eb544..14e26bbe234e 100644 --- a/hw/arm/aspeed_coprocessor_common.c +++ b/hw/arm/aspeed_coprocessor_common.c @@ -27,6 +27,8 @@ static const Property aspeed_coprocessor_properties[] =3D= { TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_LINK("sram", AspeedCoprocessorState, sram, TYPE_MEMORY_REG= ION, MemoryRegion *), + DEFINE_PROP_LINK("scu", AspeedCoprocessorState, scu, TYPE_ASPEED_SCU, + AspeedSCUState *), }; =20 static void aspeed_coprocessor_class_init(ObjectClass *oc, const void *dat= a) --=20 2.51.0 From nobody Fri Nov 14 18:19:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1761136306; cv=none; d=zohomail.com; s=zohoarc; b=NPPuOI1UbjgM4oacHDbUvSNIsLFyriTqjac08omn4u+gArEypGhKQ1octLuC+Y+jKL1zwBs2a1ihm2vXsskWQg9+s4wy5JHofbnhsJlyc9+IaWXY+dPLBd5jssNTtmiIfLzZ+0a4CsslSUN+uAhGeEn9AcWzJ5UwUBhxCONTupQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761136306; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 22 Oct 2025 12:30:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761136223; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cJarjOHnzMQr4ZfDR1YaDT6/LXUlXROKNryhb0ckRQs=; b=PKJLWoqwajol/X1Lifur74jU7G9ku1lCZkM3UclbrTdE8e07y19uExH4LJi8UTaVMnWVwQ 9FzADtYzB5urt6dsIxpxIPa7+xJZ5ZbgAL8d9z247u4cS84KsFFVuhFtO7B2E1FsSo9COg UoErXzM6mDRWq1QLCGPGRVfMjJTwpPQ= X-MC-Unique: 13CcXV6BPDuAXbnFzozk-w-1 X-Mimecast-MFC-AGG-ID: 13CcXV6BPDuAXbnFzozk-w_1761136216 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 06/16] hw/arm/ast27x0: Share single UART set across PSP, SSP, and TSP Date: Wed, 22 Oct 2025 14:29:43 +0200 Message-ID: <20251022122953.877335-7-clg@redhat.com> In-Reply-To: <20251022122953.877335-1-clg@redhat.com> References: <20251022122953.877335-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761136308107154100 From: Jamin Lin In the original model, each subsystem (PSP, SSP, and TSP) created its own set of 13 UART devices, resulting in a total of 39 UART instances. However, on real AST2700 hardware, there is only one set of 13 UARTs shared among all processors. This commit reworks the UART handling to correctly model the shared hardware design. The PSP now creates the full set of 13 UART instances, while the SSP and TSP link to the corresponding shared UART device through object properties. Changes include: - Add "DEFINE_PROP_LINK("uart", ...)" and "DEFINE_PROP_INT32("uart-dev", ..= .)" to allow each coprocessor to reference a specific shared UART instance. - Modify SSP to link to PSP=E2=80=99s UART4, and TSP to link to PSP=E2=80= =99s UART7. - Introduce "uart_alias" to remap the UART=E2=80=99s MMIO region into the c= oprocessor=E2=80=99s memory space. - Redirect the UART interrupt to the coprocessor=E2=80=99s NVIC, replacing = the default routing to the PSP=E2=80=99s GIC. With this change, only one set of 13 UART devices is instantiated by the PS= P, while the SSP and TSP reuse them via aliasing and shared interrupt routing, matching the real AST2700 hardware behavior. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-7-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_coprocessor.h | 6 +++--- hw/arm/aspeed_ast27x0-fc.c | 24 ++++++++++++------------ hw/arm/aspeed_ast27x0-ssp.c | 29 ++++++++++++----------------- hw/arm/aspeed_ast27x0-tsp.c | 29 ++++++++++++----------------- hw/arm/aspeed_coprocessor_common.c | 3 +++ 5 files changed, 42 insertions(+), 49 deletions(-) diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h index c1f2c549c323..4a50f688ecdc 100644 --- a/include/hw/arm/aspeed_coprocessor.h +++ b/include/hw/arm/aspeed_coprocessor.h @@ -19,13 +19,15 @@ struct AspeedCoprocessorState { MemoryRegion sdram; MemoryRegion *sram; MemoryRegion sram_alias; + MemoryRegion uart_alias; MemoryRegion scu_alias; Clock *sysclk; =20 AspeedSCUState *scu; AspeedSCUState scuio; AspeedTimerCtrlState timerctrl; - SerialMM uart[ASPEED_UARTS_NUM]; + SerialMM *uart; + int uart_dev; }; =20 #define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor" @@ -39,8 +41,6 @@ struct AspeedCoprocessorClass { const char * const *valid_cpu_types; const hwaddr *memmap; const int *irqmap; - int uarts_base; - int uarts_num; }; =20 struct Aspeed27x0CoprocessorState { diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index ba43a4620760..99af87dbd7bd 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -93,6 +93,10 @@ static bool ast2700fc_ca35_init(MachineState *machine, E= rror **errp) AST2700FC_HW_STRAP2, &error_abort); aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART12, sc->uarts_base, sc->uarts_num, serial_hd(0)); + aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART4, sc->uarts_base, + sc->uarts_num, serial_hd(1)); + aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base, + sc->uarts_num, serial_hd(2)); if (!qdev_realize(DEVICE(&s->ca35), NULL, errp)) { return false; } @@ -115,8 +119,6 @@ static bool ast2700fc_ca35_init(MachineState *machine, = Error **errp) =20 static bool ast2700fc_ssp_init(MachineState *machine, Error **errp) { - AspeedCoprocessorState *soc; - AspeedCoprocessorClass *sc; Ast2700FCState *s =3D AST2700A1FC(machine); AspeedSoCState *psp =3D ASPEED_SOC(&s->ca35); =20 @@ -132,10 +134,10 @@ static bool ast2700fc_ssp_init(MachineState *machine,= Error **errp) object_property_set_link(OBJECT(&s->ssp), "memory", OBJECT(&s->ssp_memory), &error_abort); =20 - soc =3D ASPEED_COPROCESSOR(&s->ssp); - sc =3D ASPEED_COPROCESSOR_GET_CLASS(soc); - aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART4, sc->uarts_base, - sc->uarts_num, serial_hd(1)); + object_property_set_link(OBJECT(&s->ssp), "uart", + OBJECT(&psp->uart[4]), &error_abort); + object_property_set_int(OBJECT(&s->ssp), "uart-dev", ASPEED_DEV_UART4, + &error_abort); object_property_set_link(OBJECT(&s->ssp), "sram", OBJECT(&psp->sram), &error_abort); object_property_set_link(OBJECT(&s->ssp), "scu", @@ -149,8 +151,6 @@ static bool ast2700fc_ssp_init(MachineState *machine, E= rror **errp) =20 static bool ast2700fc_tsp_init(MachineState *machine, Error **errp) { - AspeedCoprocessorState *soc; - AspeedCoprocessorClass *sc; Ast2700FCState *s =3D AST2700A1FC(machine); AspeedSoCState *psp =3D ASPEED_SOC(&s->ca35); =20 @@ -166,10 +166,10 @@ static bool ast2700fc_tsp_init(MachineState *machine,= Error **errp) object_property_set_link(OBJECT(&s->tsp), "memory", OBJECT(&s->tsp_memory), &error_abort); =20 - soc =3D ASPEED_COPROCESSOR(&s->tsp); - sc =3D ASPEED_COPROCESSOR_GET_CLASS(soc); - aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base, - sc->uarts_num, serial_hd(2)); + object_property_set_link(OBJECT(&s->tsp), "uart", + OBJECT(&psp->uart[7]), &error_abort); + object_property_set_int(OBJECT(&s->tsp), "uart-dev", ASPEED_DEV_UART7, + &error_abort); object_property_set_link(OBJECT(&s->tsp), "sram", OBJECT(&psp->sram), &error_abort); object_property_set_link(OBJECT(&s->tsp), "scu", diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 577a3379c6c0..d12a9b8459c2 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -133,16 +133,10 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj) { Aspeed27x0CoprocessorState *a =3D ASPEED27X0SSP_COPROCESSOR(obj); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(obj); - AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); - int i; =20 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); =20 - for (i =3D 0; i < sc->uarts_num; i++) { - object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M= M); - } - object_initialize_child(obj, "intc0", &a->intc[0], TYPE_ASPEED_2700SSP_INTC); object_initialize_child(obj, "intc1", &a->intc[1], @@ -165,7 +159,6 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *= dev_soc, Error **errp) AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); DeviceState *armv7m; g_autofree char *sdram_name =3D NULL; - int uart; int i; =20 if (!clock_has_source(s->sysclk)) { @@ -244,15 +237,19 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState= *dev_soc, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i, qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i= )); } + /* UART */ - for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { - if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], - sc->memmap[uart], errp)) { - return; - } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, - aspeed_soc_ast27x0ssp_get_irq(s, uart)); - } + memory_region_init_alias(&s->uart_alias, OBJECT(s), "uart.alias", + &s->uart->serial.io, 0, + memory_region_size(&s->uart->serial.io)); + memory_region_add_subregion(s->memory, sc->memmap[s->uart_dev], + &s->uart_alias); + /* + * Redirect the UART interrupt to the NVIC, replacing the default rout= ing + * to the PSP's GIC. + */ + sysbus_connect_irq(SYS_BUS_DEVICE(s->uart), 0, + aspeed_soc_ast27x0ssp_get_irq(s, s->uart_dev)); =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl), "aspeed.timerctrl", @@ -283,8 +280,6 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClas= s *klass, dc->realize =3D aspeed_soc_ast27x0ssp_realize; =20 sc->valid_cpu_types =3D valid_cpu_types; - sc->uarts_num =3D 13; - sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast27x0ssp_irqmap; sc->memmap =3D aspeed_soc_ast27x0ssp_memmap; } diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index a7c141678fc2..5b75e1420639 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -133,16 +133,10 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj) { Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_COPROCESSOR(obj); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(obj); - AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); - int i; =20 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); =20 - for (i =3D 0; i < sc->uarts_num; i++) { - object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M= M); - } - object_initialize_child(obj, "intc0", &a->intc[0], TYPE_ASPEED_2700TSP_INTC); object_initialize_child(obj, "intc1", &a->intc[1], @@ -165,7 +159,6 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *= dev_soc, Error **errp) AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); DeviceState *armv7m; g_autofree char *sdram_name =3D NULL; - int uart; int i; =20 if (!clock_has_source(s->sysclk)) { @@ -244,15 +237,19 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState= *dev_soc, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i, qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i= )); } + /* UART */ - for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { - if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], - sc->memmap[uart], errp)) { - return; - } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, - aspeed_soc_ast27x0tsp_get_irq(s, uart)); - } + memory_region_init_alias(&s->uart_alias, OBJECT(s), "uart.alias", + &s->uart->serial.io, 0, + memory_region_size(&s->uart->serial.io)); + memory_region_add_subregion(s->memory, sc->memmap[s->uart_dev], + &s->uart_alias); + /* + * Redirect the UART interrupt to the NVIC, replacing the default rout= ing + * to the PSP's GIC. + */ + sysbus_connect_irq(SYS_BUS_DEVICE(s->uart), 0, + aspeed_soc_ast27x0tsp_get_irq(s, s->uart_dev)); =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl), "aspeed.timerctrl", @@ -283,8 +280,6 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClas= s *klass, dc->realize =3D aspeed_soc_ast27x0tsp_realize; =20 sc->valid_cpu_types =3D valid_cpu_types; - sc->uarts_num =3D 13; - sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast27x0tsp_irqmap; sc->memmap =3D aspeed_soc_ast27x0tsp_memmap; } diff --git a/hw/arm/aspeed_coprocessor_common.c b/hw/arm/aspeed_coprocessor= _common.c index 14e26bbe234e..f037d5b573fd 100644 --- a/hw/arm/aspeed_coprocessor_common.c +++ b/hw/arm/aspeed_coprocessor_common.c @@ -29,6 +29,9 @@ static const Property aspeed_coprocessor_properties[] =3D= { MemoryRegion *), DEFINE_PROP_LINK("scu", AspeedCoprocessorState, scu, TYPE_ASPEED_SCU, AspeedSCUState *), + DEFINE_PROP_LINK("uart", AspeedCoprocessorState, uart, TYPE_SERIAL_MM, + SerialMM *), + DEFINE_PROP_INT32("uart-dev", AspeedCoprocessorState, uart_dev, 0), }; =20 static void aspeed_coprocessor_class_init(ObjectClass *oc, const void *dat= a) --=20 2.51.0 From nobody Fri Nov 14 18:19:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761136222; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kB28TO+73+LeDdZTZD3TGVweCe+TgzwQ/tG9XCfyIjw=; b=dqDPO4ztdMHGHuJzJmNxis8H+dttdUCHrIUgzQh2PHMeD96zxaxXgq6HP9aL+RM7R/gRHN yuYnTsD6BZetaxnFEpH935V+brIPI6nTQo4iYb18q6lF3QKA1o9Y+2OI2PjLHAppCe2byp vm2x0OCQff9fOJWWBdn2pkfnhs6q9y4= X-MC-Unique: 1neqlS2fOtyROEuuzDVpwQ-1 X-Mimecast-MFC-AGG-ID: 1neqlS2fOtyROEuuzDVpwQ_1761136218 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 07/16] hw/arm/aspeed_ast27x0-fc: Map FMC0 flash contents into CA35 boot ROM Date: Wed, 22 Oct 2025 14:29:44 +0200 Message-ID: <20251022122953.877335-8-clg@redhat.com> In-Reply-To: <20251022122953.877335-1-clg@redhat.com> References: <20251022122953.877335-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761136503995154100 From: Jamin Lin This patch introduces a dedicated ca35_boot_rom memory region and copies the FMC0 flash data into it. The motivation is to support the upcoming vbootrom. The vbootrom replaces the existing BOOTMCU (RISC-V 32 SPL) flow, which currently reads the "image-bmc" from FMC_CS0 and loads the following components into DRAM: - Trusted Firmware-A - OP-TEE OS - u-boot-nodtb.bin - u-boot.dtb After loading, BOOTMCU releases the CA35 reset so that CA35 can start executing Trusted Firmware-A. The vbootrom follows the same sequence: CA35 fetches "image-bmc" from FMC0 flash at the SPI boot ROM base address (0x100000000), parses the FIT image, loads each component into its designated DRAM location, and then jumps to Trusted Firmware-A. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-8-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0-fc.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index 99af87dbd7bd..99c0b3415990 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -35,6 +35,7 @@ struct Ast2700FCState { =20 MemoryRegion ca35_memory; MemoryRegion ca35_dram; + MemoryRegion ca35_boot_rom; MemoryRegion ssp_memory; MemoryRegion tsp_memory; =20 @@ -44,8 +45,6 @@ struct Ast2700FCState { Aspeed27x0SoCState ca35; Aspeed27x0CoprocessorState ssp; Aspeed27x0CoprocessorState tsp; - - bool mmio_exec; }; =20 #define AST2700FC_BMC_RAM_SIZE (1 * GiB) @@ -61,6 +60,9 @@ static bool ast2700fc_ca35_init(MachineState *machine, Er= ror **errp) Ast2700FCState *s =3D AST2700A1FC(machine); AspeedSoCState *soc; AspeedSoCClass *sc; + BlockBackend *fmc0 =3D NULL; + DeviceState *dev =3D NULL; + uint64_t rom_size; =20 object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a1"); soc =3D ASPEED_SOC(&s->ca35); @@ -112,6 +114,14 @@ static bool ast2700fc_ca35_init(MachineState *machine,= Error **errp) ast2700fc_board_info.ram_size =3D machine->ram_size; ast2700fc_board_info.loader_start =3D sc->memmap[ASPEED_DEV_SDRAM]; =20 + dev =3D ssi_get_cs(soc->fmc.spi, 0); + fmc0 =3D dev ? m25p80_get_blk(dev) : NULL; + + if (fmc0) { + rom_size =3D memory_region_size(&soc->spi_boot); + aspeed_install_boot_rom(soc, fmc0, &s->ca35_boot_rom, rom_size); + } + arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info); =20 return true; --=20 2.51.0 From nobody Fri Nov 14 18:19:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=0mrGC44ytrTwti36xw5A+Z8AQF9qMTxkNxQmboOOC9I=; b=P6URHbzEdxRXzeaTLtmMtsNdaQYsrKjk2/DDOrQs6K00uuww+BdHzSCbDvk1zWTVrDOkQM qfsph9xbvXkGTErEjaeeHpTrGqT+3aga1EiwU3gFwWUtHSjkQ+CHXQlkRLuvjJafvRUj3J jtQF+ZVdg1pKeOvk5QOH6oLea5/CNO8= X-MC-Unique: J-Qjev2vPZe2_pmtYz2DTA-1 X-Mimecast-MFC-AGG-ID: J-Qjev2vPZe2_pmtYz2DTA_1761136220 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 08/16] hw/arm/aspeed_ast27x0-fc: Add VBOOTROM support Date: Wed, 22 Oct 2025 14:29:45 +0200 Message-ID: <20251022122953.877335-9-clg@redhat.com> In-Reply-To: <20251022122953.877335-1-clg@redhat.com> References: <20251022122953.877335-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761136279243154100 From: Jamin Lin Introduces support for loading a vbootrom image into the dedicated vbootrom memory region in the AST2700 Full Core machine. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-9-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0-fc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index 99c0b3415990..7be2e849274d 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -60,6 +60,7 @@ static bool ast2700fc_ca35_init(MachineState *machine, Er= ror **errp) Ast2700FCState *s =3D AST2700A1FC(machine); AspeedSoCState *soc; AspeedSoCClass *sc; + const char *bios_name =3D NULL; BlockBackend *fmc0 =3D NULL; DeviceState *dev =3D NULL; uint64_t rom_size; @@ -122,6 +123,10 @@ static bool ast2700fc_ca35_init(MachineState *machine,= Error **errp) aspeed_install_boot_rom(soc, fmc0, &s->ca35_boot_rom, rom_size); } =20 + /* VBOOTROM */ + bios_name =3D machine->firmware ?: VBOOTROM_FILE_NAME; + aspeed_load_vbootrom(soc, bios_name, errp); + arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info); =20 return true; --=20 2.51.0 From nobody Fri Nov 14 18:19:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1761136502; cv=none; d=zohomail.com; s=zohoarc; b=I1APSPqPSe8Ata+P0xOLmU8idvZmuAn9X+Z6I80uag4VGGcVR9mcT0dVhc/mkD1VNVEeU28hhenJab+Csc8lPLCEe/ktw4ZXgttCwjohkjVrVizbuugSX4Ic0Wq9Uj7t9iARcdPPn22t53QZj304+KbuPWt243q85W18o+kAlP0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761136502; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 22 Oct 2025 12:30:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761136225; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sBKVPsCk6JfCpKccEDyOPP4XCsV/Wew3iFRnXLLT2RA=; b=SU986IHHkHy2jMKcyZo4l9LNX1HEKXohHx+Frtf+O+NPP7ryiS+whqn16jwxCgRFEM+ipw Wd+l7D1dS0fYM+VXLB5OwEtcUcPqA8RsdLvrfjaE87/7DbsLM45EkejysqmpSLHQaoHs3i kr4F5/JHc9zjFhZGzPG/MUCsa1hYCIM= X-MC-Unique: Diz9goS1MHKOBMJ5pAsCkA-1 X-Mimecast-MFC-AGG-ID: Diz9goS1MHKOBMJ5pAsCkA_1761136222 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 09/16] tests/functional/aarch64/ast2700fc: Update test ASPEED SDK v09.08 Date: Wed, 22 Oct 2025 14:29:46 +0200 Message-ID: <20251022122953.877335-10-clg@redhat.com> In-Reply-To: <20251022122953.877335-1-clg@redhat.com> References: <20251022122953.877335-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761136229; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NiL6bE9oL27bwsJLB5al9tSpk773hiCMrh7JUdV6Yiw=; b=AtQHe3iYF6y4MQRIDfA2m7FsJc8j0vUliNO3VJxFdtwzQ8GeLPpXuV8ekEctLGwuP3Ru4v ZcSOT75fsLh6lcVKyYz0bJE5GMRc8o+EwqjGBYSeyy0TCny783/iXqLkm5v/jTfr/4XjTw xxXBdsyqQNKJgFyAUK2/HlbCB0AB6iA= X-MC-Unique: FbPS9IrSMU-44txqekFngg-1 X-Mimecast-MFC-AGG-ID: FbPS9IrSMU-44txqekFngg_1761136224 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 10/16] tests/functional/aarch64/ast2700fc: Add eth2 network interface check in PCIe test Date: Wed, 22 Oct 2025 14:29:47 +0200 Message-ID: <20251022122953.877335-11-clg@redhat.com> In-Reply-To: <20251022122953.877335-1-clg@redhat.com> References: <20251022122953.877335-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761136517399158500 From: Jamin Lin Enhance the AST2700 functional PCIe test to verify the network interface configuration for eth2. This adds an additional command to check the IP address assignment on eth2 to ensure network functionality is correctly initialized in the test environment. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-11-jamin_li= n@aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- tests/functional/aarch64/test_aspeed_ast2700fc.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/func= tional/aarch64/test_aspeed_ast2700fc.py index bcce0c8d4e53..843647e6c539 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700fc.py +++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py @@ -60,6 +60,9 @@ def do_ast2700_pcie_test(self): 'lspci -s 0002:01:00.0', '0002:01:00.0 Ethernet controller: ' 'Intel Corporation 82574L Gigabit Network Connection') + exec_command_and_wait_for_pattern(self, + 'ip addr show dev eth2', + 'inet 10.0.2.15/24') =20 def do_ast2700fc_ssp_test(self): self.vm.shutdown() @@ -135,6 +138,7 @@ def start_ast2700fc_test(self, name): =20 def test_aarch64_ast2700fc_sdk_v09_08(self): self.set_machine('ast2700fc') + self.require_netdev('user') =20 self.archive_extract(self.ASSET_SDK_V908_AST2700) self.start_ast2700fc_test('ast2700-default') --=20 2.51.0 From nobody Fri Nov 14 18:19:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761136234; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TdTrbPXtynNAXwAhpN5/gd4TGsAWE13woMEeI3VLlnU=; b=ZIbPNXyj+DpbLZm/z82mb16l5bnd/jkOYPp9v5HnJoxCDizvCBm70dvdMmq6+/J5VNxYn2 v6aRX6CgIHutF82bMOiOeRuVihoHtG7hzLXRHAdiWuvveX6vbcMncC0kLblMhgs9QqOZnz Ri1rEufwxryua0KEWR0rKK1WL/gumCQ= X-MC-Unique: qgk6dzNRN2yK9iS0MJowxQ-1 X-Mimecast-MFC-AGG-ID: qgk6dzNRN2yK9iS0MJowxQ_1761136227 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 11/16] tests/functional/aarch64/ast2700fc: Move coprocessor image loading to common function Date: Wed, 22 Oct 2025 14:29:48 +0200 Message-ID: <20251022122953.877335-12-clg@redhat.com> In-Reply-To: <20251022122953.877335-1-clg@redhat.com> References: <20251022122953.877335-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761136462966158500 From: Jamin Lin This removes duplicate code in start_ast2700fc_test() and prepares for reus= e in upcoming VBOOTROM tests. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-12-jamin_li= n@aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- .../aarch64/test_aspeed_ast2700fc.py | 22 ++++++++++--------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/func= tional/aarch64/test_aspeed_ast2700fc.py index 843647e6c539..9ab3d3269b2a 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700fc.py +++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py @@ -36,6 +36,17 @@ def verify_openbmc_boot_and_login(self, name): exec_command_and_wait_for_pattern(self, 'root', 'Password:') exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~= #') =20 + def load_ast2700fc_coprocessor(self, name): + load_elf_list =3D { + 'ssp': self.scratch_file(name, 'zephyr-aspeed-ssp.elf'), + 'tsp': self.scratch_file(name, 'zephyr-aspeed-tsp.elf') + } + + for cpu_num, key in enumerate(load_elf_list, start=3D4): + file =3D load_elf_list[key] + self.vm.add_args('-device', + f'loader,file=3D{file},cpu-num=3D{cpu_num}') + ASSET_SDK_V908_AST2700 =3D Asset( 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v= 09.08/ast2700-default-obmc.tar.gz', 'eac3dc409b7ea3cd4b03d4792d3cebd469792ad893cb51e1d15f0fc20bd1e= 2cd') @@ -123,16 +134,7 @@ def start_ast2700fc_test(self, name): self.vm.add_args('-device', f'loader,addr=3D0x430000000,cpu-num=3D{i}') =20 - load_elf_list =3D { - 'ssp': self.scratch_file(name, 'zephyr-aspeed-ssp.elf'), - 'tsp': self.scratch_file(name, 'zephyr-aspeed-tsp.elf') - } - - for cpu_num, key in enumerate(load_elf_list, start=3D4): - file =3D load_elf_list[key] - self.vm.add_args('-device', - f'loader,file=3D{file},cpu-num=3D{cpu_num}') - + self.load_ast2700fc_coprocessor(name) self.do_test_aarch64_aspeed_sdk_start( self.scratch_file(name, 'image-bmc')) =20 --=20 2.51.0 From nobody Fri Nov 14 18:19:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761136232; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/eDRd8TMDVFLc1jfdHKLOkdmmzQsBdOy51ZEFZ2mk/4=; b=APHCIEhrmEKX8jOZ7cxoAe9PbCnhB3WUA4rxxgTgw+kq5tv/rhbqYmheD7eDKy6lJNPB/3 7AHfrepQlBAO0sQXJADfmmsgmOAFmdjqJt8Sy2aXyjz3eno2meF2AOCYulikCtBRixIOQ8 lKF1Hb3YqVz4aAQxRMAQjfj4uRGEL4g= X-MC-Unique: Hg20khiLNc-GfCqQjOjh2Q-1 X-Mimecast-MFC-AGG-ID: Hg20khiLNc-GfCqQjOjh2Q_1761136229 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 12/16] tests/functional/aarch64/ast2700fc: Add vbootrom test Date: Wed, 22 Oct 2025 14:29:49 +0200 Message-ID: <20251022122953.877335-13-clg@redhat.com> In-Reply-To: <20251022122953.877335-1-clg@redhat.com> References: <20251022122953.877335-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761136542367154100 From: Jamin Lin Add start_ast2700fc_test_vbootrom() which boots the ast2700fc machine with -bios ast27x0_bootrom.bin and reuses the coprocessor loader. Add test_aarch64_ast2700fc_sdk_vbootrom_v09_08() to test the vbootrom with ast2700fc machine. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-13-jamin_li= n@aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- tests/functional/aarch64/test_aspeed_ast2700fc.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/func= tional/aarch64/test_aspeed_ast2700fc.py index 9ab3d3269b2a..8dbc8f234f9c 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700fc.py +++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py @@ -138,6 +138,12 @@ def start_ast2700fc_test(self, name): self.do_test_aarch64_aspeed_sdk_start( self.scratch_file(name, 'image-bmc')) =20 + def start_ast2700fc_test_vbootrom(self, name): + self.vm.add_args('-bios', 'ast27x0_bootrom.bin') + self.load_ast2700fc_coprocessor(name) + self.do_test_aarch64_aspeed_sdk_start( + self.scratch_file(name, 'image-bmc')) + def test_aarch64_ast2700fc_sdk_v09_08(self): self.set_machine('ast2700fc') self.require_netdev('user') @@ -150,5 +156,14 @@ def test_aarch64_ast2700fc_sdk_v09_08(self): self.do_ast2700fc_ssp_test() self.do_ast2700fc_tsp_test() =20 + def test_aarch64_ast2700fc_sdk_vbootrom_v09_08(self): + self.set_machine('ast2700fc') + + self.archive_extract(self.ASSET_SDK_V908_AST2700) + self.start_ast2700fc_test_vbootrom('ast2700-default') + self.verify_openbmc_boot_and_login('ast2700-default') + self.do_ast2700fc_ssp_test() + self.do_ast2700fc_tsp_test() + if __name__ =3D=3D '__main__': QemuSystemTest.main() --=20 2.51.0 From nobody Fri Nov 14 18:19:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761136234; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9tdVRDMa+CP59QN6n9l8X5fBQaMisZCvXCWykcYIN4A=; b=G8w1/BolR2+06Oy++CB+GECZ3+QmjS4iAkkL0Pmw3UqPm5ebjpPd5njYYcZky6nFc7r88j HXO/IyWvK7BsK9B+MK5VwPkmefecUmMsUy+vK+MbhXoF/9lQmxjrGVq9LhazpSJLq4324W gJrJDpwF2X8Kr20gPj9AZi53eOOpqNg= X-MC-Unique: wuAYAdUUNkG1f2kyvcjgVw-1 X-Mimecast-MFC-AGG-ID: wuAYAdUUNkG1f2kyvcjgVw_1761136231 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Felix Wu , Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 13/16] hw/gpio: Add property for ASPEED GPIO in 32 bits basis Date: Wed, 22 Oct 2025 14:29:50 +0200 Message-ID: <20251022122953.877335-14-clg@redhat.com> In-Reply-To: <20251022122953.877335-1-clg@redhat.com> References: <20251022122953.877335-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761136459349154100 From: Felix Wu Added 32 bits property for ASPEED GPIO. Previously it can only be access in bitwise manner. The changes to qobject is to index gpios with array indices on top of accessing with registers. This allows for easier gpio access, especially in tests with complex behaviors that requires large number of gpios at a time, like fault injection and networking behaviors. Indexing multiple gpios at once allows qmp/side band client to no longer hardcode and populate register names and manipulate them faster. Signed-off-by: Felix Wu Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/qemu-devel/20251015011830.1688468-2-lixiaoyan= @google.com [ clg: wrapped commit log lines ] Signed-off-by: C=C3=A9dric Le Goater --- hw/gpio/aspeed_gpio.c | 57 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index 609a556908f9..2d78bf9515c4 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -1308,6 +1308,57 @@ static void aspeed_gpio_2700_write(void *opaque, hwa= ddr offset, } =20 /* Setup functions */ +static void aspeed_gpio_set_set(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + uint32_t set_val =3D 0; + AspeedGPIOState *s =3D ASPEED_GPIO(obj); + AspeedGPIOClass *agc =3D ASPEED_GPIO_GET_CLASS(s); + int set_idx =3D 0; + + if (!visit_type_uint32(v, name, &set_val, errp)) { + return; + } + + if (sscanf(name, "gpio-set[%d]", &set_idx) !=3D 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + + if (set_idx >=3D agc->nr_gpio_sets || set_idx < 0) { + error_setg(errp, "%s: invalid set_idx %s", __func__, name); + return; + } + + aspeed_gpio_update(s, &s->sets[set_idx], set_val, + ~s->sets[set_idx].direction); +} + +static void aspeed_gpio_get_set(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + uint32_t set_val =3D 0; + AspeedGPIOState *s =3D ASPEED_GPIO(obj); + AspeedGPIOClass *agc =3D ASPEED_GPIO_GET_CLASS(s); + int set_idx =3D 0; + + if (sscanf(name, "gpio-set[%d]", &set_idx) !=3D 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + + if (set_idx >=3D agc->nr_gpio_sets || set_idx < 0) { + error_setg(errp, "%s: invalid set_idx %s", __func__, name); + return; + } + + set_val =3D s->sets[set_idx].data_value; + visit_type_uint32(v, name, &set_val, errp); +} + +/****************** Setup functions ******************/ static const GPIOSetProperties ast2400_set_props[ASPEED_GPIO_MAX_NR_SETS] = =3D { [0] =3D {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, [1] =3D {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, @@ -1435,6 +1486,12 @@ static void aspeed_gpio_init(Object *obj) g_free(name); } } + + for (int i =3D 0; i < agc->nr_gpio_sets; i++) { + char *name =3D g_strdup_printf("gpio-set[%d]", i); + object_property_add(obj, name, "uint32", aspeed_gpio_get_set, + aspeed_gpio_set_set, NULL, NULL); + } } =20 static const VMStateDescription vmstate_gpio_regs =3D { --=20 2.51.0 From nobody Fri Nov 14 18:19:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1761136382; cv=none; d=zohomail.com; s=zohoarc; b=FlMDQXlmy9vCqYUw9PC9eYzps9lw9y/okLu0EkS8RmHbtyXX88xcU6f0LFsyZIznh11zHZ2MbsTBzMpLIEHlEI11QuGoIA4RqxAgEK0TBjUNCAgwH4vmtWmJr2prNbuOnxgqVznLu9Yag7bmaqb4tZqRdbR/UlP6PzwACoeic5k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761136382; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 22 Oct 2025 12:30:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761136239; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Xm0lAR7m+7Yigr6CnsX4IQzn/DIW8aFNZGH/VklZDhY=; b=ayOUl1mtvKSjFGqRW9sIrEbjVmw4KVOAnn2e43BE6a+TK18D4ZwVtVLY7wU8+jyYmiMIV8 HBNGhFjrCQFxYXI1S4eHn6NWtoxpkz+7e0VK4j8x8kMkYhVH3hfPIKIAonjy1ekw6COnZA 9Hrta34+K2qwtmbHbOeE57RV+xALY04= X-MC-Unique: hk3-HJF4OruOW3NPOLI5Ag-1 X-Mimecast-MFC-AGG-ID: hk3-HJF4OruOW3NPOLI5Ag_1761136233 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Felix Wu , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 14/16] tests/qtest: Add qtest for for ASPEED GPIO gpio-set property Date: Wed, 22 Oct 2025 14:29:51 +0200 Message-ID: <20251022122953.877335-15-clg@redhat.com> In-Reply-To: <20251022122953.877335-1-clg@redhat.com> References: <20251022122953.877335-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761136384617154100 From: Felix Wu - Added qtests to test gpio-set property for ASPEED. - Added function to get uint in qdict. Signed-off-by: Felix Wu Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251015011830.1688468-3-lixiaoyan= @google.com Signed-off-by: C=C3=A9dric Le Goater --- include/qobject/qdict.h | 1 + qobject/qdict.c | 13 ++++ tests/qtest/aspeed_gpio-test.c | 105 ++++++++++++++++++++++++++++++--- 3 files changed, 110 insertions(+), 9 deletions(-) diff --git a/include/qobject/qdict.h b/include/qobject/qdict.h index 903e6e5462fb..861996f08dd6 100644 --- a/include/qobject/qdict.h +++ b/include/qobject/qdict.h @@ -57,6 +57,7 @@ void qdict_put_str(QDict *qdict, const char *key, const c= har *value); =20 double qdict_get_double(const QDict *qdict, const char *key); int64_t qdict_get_int(const QDict *qdict, const char *key); +uint64_t qdict_get_uint(const QDict *qdict, const char *key); bool qdict_get_bool(const QDict *qdict, const char *key); QList *qdict_get_qlist(const QDict *qdict, const char *key); QDict *qdict_get_qdict(const QDict *qdict, const char *key); diff --git a/qobject/qdict.c b/qobject/qdict.c index a90ac9ae2f89..0dafe6d42179 100644 --- a/qobject/qdict.c +++ b/qobject/qdict.c @@ -209,6 +209,19 @@ int64_t qdict_get_int(const QDict *qdict, const char *= key) return qnum_get_int(qobject_to(QNum, qdict_get(qdict, key))); } =20 +/** + * qdict_get_uint(): Get an unsigned integer mapped by 'key' + * + * This function assumes that 'key' exists and it stores a + * QNum representable as uint. + * + * Return unsigned integer mapped by 'key'. + */ +uint64_t qdict_get_uint(const QDict *qdict, const char *key) +{ + return qnum_get_uint(qobject_to(QNum, qdict_get(qdict, key))); +} + /** * qdict_get_bool(): Get a bool mapped by 'key' * diff --git a/tests/qtest/aspeed_gpio-test.c b/tests/qtest/aspeed_gpio-test.c index 12675d4cbba9..c2f9ca2298a7 100644 --- a/tests/qtest/aspeed_gpio-test.c +++ b/tests/qtest/aspeed_gpio-test.c @@ -27,28 +27,115 @@ #include "qemu/timer.h" #include "qobject/qdict.h" #include "libqtest-single.h" +#include "qemu/typedefs.h" =20 #define AST2600_GPIO_BASE 0x1E780000 =20 #define GPIO_ABCD_DATA_VALUE 0x000 #define GPIO_ABCD_DIRECTION 0x004 =20 +static uint32_t qtest_qom_get_uint32(QTestState *s, const char *path, + const char *property) +{ + QDict *r; + + uint32_t res; + r =3D qtest_qmp(s, "{ 'execute': 'qom-get', 'arguments': " + "{ 'path': %s, 'property': %s } }", path, property); + res =3D qdict_get_uint(r, "return"); + qobject_unref(r); + + return res; +} + +static void qtest_qom_set_uint32(QTestState *s, const char *path, + const char *property, uint32_t value) +{ + QDict *r; + + r =3D qtest_qmp(s, "{ 'execute': 'qom-set', 'arguments': " + "{ 'path': %s, 'property': %s, 'value': %" PRIu32 " }= }", + path, property, value); + qobject_unref(r); +} + +static const char *resp_get_error(QDict *r, const char* error_key) +{ + QDict *qdict; + + g_assert(r); + + qdict =3D qdict_get_qdict(r, "error"); + if (qdict) { + return qdict_get_str(qdict, error_key); + } + + return NULL; +} + +static bool qtest_qom_check_error(QTestState *s, const char *path, + const char *property, const char *error_= msg, + const char *error_msg_key) +{ + QDict *r; + bool b; + + r =3D qtest_qmp(s, "{ 'execute': 'qom-get', 'arguments': " + "{ 'path': %s, 'property': %s } }", path, property); + b =3D g_str_equal(resp_get_error(r, error_msg_key), error_msg); + qobject_unref(r); + + return b; +} + static void test_set_colocated_pins(const void *data) { QTestState *s =3D (QTestState *)data; - + const char path[] =3D "/machine/soc/gpio"; /* * gpioV4-7 occupy bits within a single 32-bit value, so we want to ma= ke * sure that modifying one doesn't affect the other. */ - qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV4", true); - qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV5", false); - qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV6", true); - qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV7", false); - g_assert(qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV4")); - g_assert(!qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV5")); - g_assert(qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV6")); - g_assert(!qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV7")); + qtest_qom_set_bool(s, path, "gpioV4", true); + qtest_qom_set_bool(s, path, "gpioV5", false); + qtest_qom_set_bool(s, path, "gpioV6", true); + qtest_qom_set_bool(s, path, "gpioV7", false); + g_assert(qtest_qom_get_bool(s, path, "gpioV4")); + g_assert(!qtest_qom_get_bool(s, path, "gpioV5")); + g_assert(qtest_qom_get_bool(s, path, "gpioV6")); + g_assert(!qtest_qom_get_bool(s, path, "gpioV7")); + + /* + * Testing the gpio-set[%d] properties, using individual gpio boolean + * properties to do cross check. + * We use gpioR4-7 for test, Setting them to be 0b1010. + */ + qtest_qom_set_uint32(s, path, "gpio-set[4]", 0x0); + g_assert(qtest_qom_get_uint32(s, path, "gpio-set[4]") =3D=3D 0x0); + qtest_qom_set_uint32(s, path, "gpio-set[4]", 0xa000); + g_assert(qtest_qom_get_uint32(s, path, "gpio-set[4]") =3D=3D 0xa000); + + g_assert(!qtest_qom_get_bool(s, path, "gpioR4")); + g_assert(qtest_qom_get_bool(s, path, "gpioR5")); + g_assert(!qtest_qom_get_bool(s, path, "gpioR6")); + g_assert(qtest_qom_get_bool(s, path, "gpioR7")); + + /* + * Testing the invalid indexing, the response info should contain foll= owing + * info: + * {key: "class", value: "GenericError"} + * + * For pins, it should follow "gpio%2[A-Z]%1d" or "gpio%3[18A-E]%1d" f= ormat. + */ + const char error_msg[] =3D "GenericError"; + const char error_msg_key[] =3D "class"; + + g_assert(qtest_qom_check_error(s, path, "gpioR+1", error_msg, + error_msg_key)); + g_assert(qtest_qom_check_error(s, path, "gpio-set[99]", error_msg, + error_msg_key)); + g_assert(qtest_qom_check_error(s, path, "gpio-set[-3]", error_msg, + error_msg_key)); } =20 static void test_set_input_pins(const void *data) --=20 2.51.0 From nobody Fri Nov 14 18:19:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1761136344; cv=none; d=zohomail.com; s=zohoarc; b=aB0YKgx2BStjHVHN3DV09EOr5sGTpy3bwlER/MjtMg3Skls1MGdgIFlFCY7bKy/YtggRsNTf5V0mp9VY4AlX8JhEaf7GdyF17fvYs1z74erie8+aRLRKiVFNH1eyukxi6E0HtOpUSNqAbSxLuNXwth25vygCHFB5xn5GW11q0bY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761136344; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 22 Oct 2025 12:30:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761136240; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FW6JqfxgLAwqsIH9ljEDUOQ58wJhevs/bEIifDWovxY=; b=al7RbK55wz4Yrd0CSC++4TnMsFQOXy6GN/QgeA5DOivuxztQaJrKDLPelbSJKQ/I3n5IXi WboVQOhTLCTyz0lNu0jIRW0YUhEkEGJvvWgC39t0zp56ziFTBFPLEAq12LEq6MBhp9TICG mxcSjAxnRllTttgVjt8LTOdDTUrfFe0= X-MC-Unique: 9wrK0TKDO6OLGEKF03D3rw-1 X-Mimecast-MFC-AGG-ID: 9wrK0TKDO6OLGEKF03D3rw_1761136236 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Jamin Lin Subject: [PULL 15/16] hw/arm/aspeed: ast2600-evb: Use w25q512jv flash model Date: Wed, 22 Oct 2025 14:29:52 +0200 Message-ID: <20251022122953.877335-16-clg@redhat.com> In-Reply-To: <20251022122953.877335-1-clg@redhat.com> References: <20251022122953.877335-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761136353542158500 The ast2600-evb machine model is using the "mx66u51235f" flash model, which has issues with recent Linux kernels (6.15+) when reading SFDP data. Change the flash model to "w25q512jv", which is the model present on some ast2600a3 EVB board and is known to work correctly with recent kernels. Adjust the corresponding qtest to reflect the new JEDEC ID of the w25q512jv flash. Reviewed-by: Jamin Lin Link: https://lore.kernel.org/qemu-devel/20251016212437.1046135-1-clg@redha= t.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 4 ++-- tests/qtest/aspeed_smc-test.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 21ee62f75044..1bc9e534ba49 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1592,8 +1592,8 @@ static void aspeed_machine_ast2600_evb_class_init(Obj= ectClass *oc, amc->soc_name =3D "ast2600-a3"; amc->hw_strap1 =3D AST2600_EVB_HW_STRAP1; amc->hw_strap2 =3D AST2600_EVB_HW_STRAP2; - amc->fmc_model =3D "mx66u51235f"; - amc->spi_model =3D "mx66u51235f"; + amc->fmc_model =3D "w25q512jv"; + amc->spi_model =3D "w25q512jv"; amc->num_cs =3D 1; amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON; diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c index 52a00e6f0a7e..50a87e625001 100644 --- a/tests/qtest/aspeed_smc-test.c +++ b/tests/qtest/aspeed_smc-test.c @@ -134,10 +134,10 @@ static void test_ast2600_evb(AspeedSMCTestData *data) "-drive file=3D%s,format=3Draw,if=3Dmtd", data->tmp_path); =20 - /* fmc cs0 with mx66u51235f flash */ + /* fmc cs0 with w25q512jv flash */ data->flash_base =3D 0x20000000; data->spi_base =3D 0x1E620000; - data->jedec_id =3D 0xc2253a; + data->jedec_id =3D 0xef4020; data->cs =3D 0; data->node =3D "/machine/soc/fmc/ssi.0/child[0]"; /* beyond 16MB */ --=20 2.51.0 From nobody Fri Nov 14 18:19:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1761136538; cv=none; d=zohomail.com; s=zohoarc; b=D/b179U0uxF07ts/4RpdTgEpLGdlZ4Uw0TwTsp8RMonJlcM3cePePJmzQqW18UXFlzNq8GplAeIYzuG312Bd8m2IxnI6eiYJ60dEsiFxKVnCqznhBqyewOegKXta0FgmpNljDOkvzOi7Vn8quTvivlC7O4Xxk6QqbLP4ltUA7y0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1761136538; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 22 Oct 2025 12:30:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1761136240; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=M40PfpnOpJtcy9N5Nocxi9lKZu+Hq5YHP/I1TensomQ=; b=f60kflN89gBlXYGZLSi8WOik0TI7t9dcX0cJtCsSjfA3LJ6efGx2gpN2Yfg+1GEju3a7fx 8du9HTYe7VU5k4ZKs6DWCqZOZ5XzlMfQ8YiFThLIQk3+GGJdZvqxiDCJJG34nVrrBhbcbG jhKggI3I1BXcIvzFOZOIQ4qOau6g+LY= X-MC-Unique: m1M24P3-McGcFrucXlUoOQ-1 X-Mimecast-MFC-AGG-ID: m1M24P3-McGcFrucXlUoOQ_1761136238 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 16/16] hw/arm/aspeed: Remove ast2700fc self-aliasing Date: Wed, 22 Oct 2025 14:29:53 +0200 Message-ID: <20251022122953.877335-17-clg@redhat.com> In-Reply-To: <20251022122953.877335-1-clg@redhat.com> References: <20251022122953.877335-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1761136540302154100 From: Philippe Mathieu-Daud=C3=A9 Remove pointless alias to the very same machine: $ qemu-system-aarch64 -M help | fgrep ast2700fc ast2700fc ast2700 full core support (alias of ast2700fc) ast2700fc ast2700 full core support Fixes: a74faf35efc ("hw/arm: Introduce ASPEED AST2700 A1 full core machine") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251021110427.93991-1-philmd@lina= ro.org Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0-fc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index 7be2e849274d..580ac5f7a124 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -207,7 +207,6 @@ static void ast2700fc_class_init(ObjectClass *oc, const= void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); =20 - mc->alias =3D "ast2700fc"; mc->desc =3D "ast2700 full core support"; mc->init =3D ast2700fc_init; mc->no_floppy =3D 1; --=20 2.51.0