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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [172.17.58.29] X-ClientProxiedBy: S-SC-EXCH-01.corp.syntacore.com (10.76.202.20) To S-SC-EXCH-01.corp.syntacore.com (10.76.202.20) X-KSMG-AntiPhishing: not scanned, disabled by settings X-KSMG-AntiSpam-Interceptor-Info: not scanned X-KSMG-AntiSpam-Status: not scanned, disabled by settings X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.1.1.8310, bases: 2025/10/22 06:57:00 #27791190 X-KSMG-AntiVirus-Status: NotDetected, skipped X-KSMG-LinksScanning: NotDetected X-KSMG-Message-Action: skipped X-KSMG-Rule-ID: 5 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=178.249.69.228; envelope-from=n.novikov@syntacore.com; helo=m.syntacore.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @syntacore.com) X-ZM-MESSAGEID: 1761134025830154100 Recent debugging of misaligned access handling on RISC-V revealed that we always call `tlb_fill` with `memop_size =3D=3D 0`. This behavior effectively disables natural alignment checks in `riscv_tlb_fill_align()`, because we have to fall back from `memop_size` to `size` when computing the alignment = bits. With `memop_size =3D=3D 0`, misaligned cross-page stores end up reported as `store access fault` (AF, cause=3D7) instead of the expected `store page fault` (PF, cause=3D15), since the =E2=80=9Cmisalign=E2=80=9D p= ath triggers before the second page translation can fault. This breaks misaligned accesses at page boundaries. After switching to pass the real `l->memop` into `tlb_fill`, the cross-page faults are no longer mis-classified as AF. Fixes: ec03dd972378 ("accel/tcg: Hoist first page lookup above pointer_wrap= ") Signed-off-by: Nikita Novikov Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/cputlb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 631f1fe135..271c061be1 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1782,7 +1782,7 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, Mem= OpIdx oi, * If the lookup potentially resized the table, refresh the * first CPUTLBEntryFull pointer. */ - if (mmu_lookup1(cpu, &l->page[1], 0, l->mmu_idx, type, ra)) { + if (mmu_lookup1(cpu, &l->page[1], l->memop, l->mmu_idx, type, ra))= { uintptr_t index =3D tlb_index(cpu, l->mmu_idx, addr); l->page[0].full =3D &cpu->neg.tlb.d[l->mmu_idx].fulltlb[index]; } --=20 2.51.0