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Tue, 21 Oct 2025 19:26:52 -0700 (PDT) From: Jay Chang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Jay Chang , Frank Chang , Jim Shu Subject: [PATCH v2 2/2] target/riscv: Make PMP CSRs conform to WARL constraints Date: Wed, 22 Oct 2025 10:26:28 +0800 Message-ID: <20251022022628.41307-6-jay.chang@sifive.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251022022628.41307-1-jay.chang@sifive.com> References: <20251022022628.41307-1-jay.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=jay.chang@sifive.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1761100127486154100 Content-Type: text/plain; charset="utf-8" This patch ensure pmpcfg and pmpaddr comply with WARL constraints. When the PMP granularity is greater than 4 bytes, NA4 mode is not valid per the spec and will be silently ignored. According to the spec, changing pmpcfg.A only affects the "read" value of pmpaddr. When G > 2 and pmpcfg.A is NAPOT, bits pmpaddr[G-2:0] read as all ones. When G > 1 and pmpcfg.A is OFF or TOR, bits pmpaddr[G-1:0] read as all zeros. This allows software to read back the correct granularity value. In addition, when updating the PMP address rule in TOR mode, the start and end addresses of the PMP region should be aligned to the PMP granularity. (The current SPEC only state in TOR mode that bits pmpaddr[G-1:0] do not affect the TOR address-matching logic.) Signed-off-by: Jay Chang Reviewed-by: Frank Chang Reviewed-by: Jim Shu --- target/riscv/pmp.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 72f1372a49..3ef62d26ad 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -108,6 +108,17 @@ static int pmp_is_invalid_smepmp_cfg(CPURISCVState *en= v, uint8_t val) g_assert_not_reached(); } } +/* + * Calculate PMP granularity value 'g' + * + * The granularity value 'g' is defined as log2(granularity) - 2, where + * granularity is the minimum alignment requirement for PMP regions in byt= es. + */ +static inline int pmp_get_granularity_g(CPURISCVState *env) +{ + return __builtin_ctz(riscv_cpu_cfg(env)->pmp_granularity >> 2); +} + =20 /* * Count the number of active rules. @@ -153,6 +164,15 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t= pmp_index, uint8_t val) qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - invalid\n"); } else { + uint8_t a_field =3D pmp_get_a_field(val); + /* + * When granularity g >=3D 1 (i.e., granularity > 4 bytes), + * the NA4 (Naturally Aligned 4-byte) mode is not selectable + */ + if ((riscv_cpu_cfg(env)->pmp_granularity > + MIN_RISCV_PMP_GRANULARITY) && (a_field =3D=3D PMP_AMATCH_N= A4)) { + return false; + } env->pmp_state.pmp[pmp_index].cfg_reg =3D val; pmp_update_rule_addr(env, pmp_index); return true; @@ -199,6 +219,7 @@ void pmp_update_rule_addr(CPURISCVState *env, uint32_t = pmp_index) target_ulong prev_addr =3D 0u; hwaddr sa =3D 0u; hwaddr ea =3D 0u; + int g =3D pmp_get_granularity_g(env); =20 if (pmp_index >=3D 1u) { prev_addr =3D env->pmp_state.pmp[pmp_index - 1].addr_reg; @@ -211,6 +232,11 @@ void pmp_update_rule_addr(CPURISCVState *env, uint32_t= pmp_index) break; =20 case PMP_AMATCH_TOR: + /* Bits pmpaddr[G-1:0] do not affect the TOR address-matching logi= c. */ + if (g >=3D 1) { + prev_addr &=3D ~((1ULL << g) - 1ULL); + this_addr &=3D ~((1ULL << g) - 1ULL); + } if (prev_addr >=3D this_addr) { sa =3D ea =3D 0u; break; @@ -577,6 +603,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t add= r_index, =20 /* * Handle a read from a pmpaddr CSR + * Change A field of pmpcfg affects the read value of pmpaddr */ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) { @@ -585,6 +612,25 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint= 32_t addr_index) =20 if (addr_index < pmp_regions) { val =3D env->pmp_state.pmp[addr_index].addr_reg; + int g =3D pmp_get_granularity_g(env); + switch (pmp_get_a_field(env->pmp_state.pmp[addr_index].cfg_reg)) { + case PMP_AMATCH_OFF: + /* fallthrough */ + case PMP_AMATCH_TOR: + /* Bit [g-1:0] read all zero */ + if (g >=3D 1 && g < TARGET_LONG_BITS) { + val &=3D ~((1ULL << g) - 1ULL); + } + break; + case PMP_AMATCH_NAPOT: + /* Bit [g-2:0] read all one */ + if (g >=3D 2 && g < TARGET_LONG_BITS) { + val |=3D ((1ULL << (g - 1)) - 1ULL); + } + break; + default: + break; + } trace_pmpaddr_csr_read(env->mhartid, addr_index, val); } else { qemu_log_mask(LOG_GUEST_ERROR, --=20 2.48.1