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Like PICCommonState, the APICCommonState is now a public typedef while stay= ing an abstract datatype. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20251019210303.104718-8-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/i386/apic.h | 33 +++++------ include/hw/i386/apic_internal.h | 7 +-- target/i386/cpu.h | 5 +- target/i386/kvm/kvm_i386.h | 2 +- target/i386/whpx/whpx-internal.h | 4 +- hw/i386/kvm/apic.c | 3 +- hw/i386/vapic.c | 2 +- hw/i386/x86-cpu.c | 2 +- hw/intc/apic.c | 97 +++++++++++++------------------- hw/intc/apic_common.c | 56 +++++++----------- target/i386/cpu-apic.c | 18 +++--- target/i386/cpu-dump.c | 2 +- target/i386/cpu.c | 2 +- target/i386/kvm/kvm.c | 2 +- target/i386/whpx/whpx-apic.c | 3 +- 15 files changed, 98 insertions(+), 140 deletions(-) diff --git a/include/hw/i386/apic.h b/include/hw/i386/apic.h index eb606d60760..871f1428885 100644 --- a/include/hw/i386/apic.h +++ b/include/hw/i386/apic.h @@ -1,28 +1,29 @@ #ifndef APIC_H #define APIC_H =20 +typedef struct APICCommonState APICCommonState; =20 /* apic.c */ void apic_set_max_apic_id(uint32_t max_apic_id); -int apic_accept_pic_intr(DeviceState *s); -void apic_deliver_pic_intr(DeviceState *s, int level); -void apic_deliver_nmi(DeviceState *d); -int apic_get_interrupt(DeviceState *s); -int cpu_set_apic_base(DeviceState *s, uint64_t val); -uint64_t cpu_get_apic_base(DeviceState *s); -bool cpu_is_apic_enabled(DeviceState *s); -void cpu_set_apic_tpr(DeviceState *s, uint8_t val); -uint8_t cpu_get_apic_tpr(DeviceState *s); -void apic_init_reset(DeviceState *s); -void apic_sipi(DeviceState *s); -void apic_poll_irq(DeviceState *d); -void apic_designate_bsp(DeviceState *d, bool bsp); -int apic_get_highest_priority_irr(DeviceState *dev); +int apic_accept_pic_intr(APICCommonState *s); +void apic_deliver_pic_intr(APICCommonState *s, int level); +void apic_deliver_nmi(APICCommonState *s); +int apic_get_interrupt(APICCommonState *s); +int cpu_set_apic_base(APICCommonState *s, uint64_t val); +uint64_t cpu_get_apic_base(APICCommonState *s); +bool cpu_is_apic_enabled(APICCommonState *s); +void cpu_set_apic_tpr(APICCommonState *s, uint8_t val); +uint8_t cpu_get_apic_tpr(APICCommonState *s); +void apic_init_reset(APICCommonState *s); +void apic_sipi(APICCommonState *s); +void apic_poll_irq(APICCommonState *s); +void apic_designate_bsp(APICCommonState *s, bool bsp); +int apic_get_highest_priority_irr(APICCommonState *s); int apic_msr_read(int index, uint64_t *val); int apic_msr_write(int index, uint64_t val); -bool is_x2apic_mode(DeviceState *d); +bool is_x2apic_mode(APICCommonState *s); =20 /* pc.c */ -DeviceState *cpu_get_current_apic(void); +APICCommonState *cpu_get_current_apic(void); =20 #endif diff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_interna= l.h index 429278da618..4a62fdceb4e 100644 --- a/include/hw/i386/apic_internal.h +++ b/include/hw/i386/apic_internal.h @@ -22,6 +22,7 @@ #define QEMU_APIC_INTERNAL_H =20 #include "cpu.h" +#include "hw/i386/apic.h" #include "system/memory.h" #include "qemu/timer.h" #include "target/i386/cpu-qom.h" @@ -125,8 +126,6 @@ #define VAPIC_ENABLE_BIT 0 #define VAPIC_ENABLE_MASK (1 << VAPIC_ENABLE_BIT) =20 -typedef struct APICCommonState APICCommonState; - #define TYPE_APIC_COMMON "apic-common" typedef struct APICCommonClass APICCommonClass; DECLARE_OBJ_CHECKERS(APICCommonState, APICCommonClass, @@ -203,8 +202,8 @@ typedef struct VAPICState { extern bool apic_report_tpr_access; =20 bool apic_next_timer(APICCommonState *s, int64_t current_time); -void apic_enable_tpr_access_reporting(DeviceState *d, bool enable); -void apic_enable_vapic(DeviceState *d, hwaddr paddr); +void apic_enable_tpr_access_reporting(APICCommonState *s, bool enable); +void apic_enable_vapic(APICCommonState *s, hwaddr paddr); =20 void vapic_report_tpr_access(DeviceState *dev, CPUState *cpu, target_ulong= ip, TPRAccess access); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ce948861a76..d0da9bfe58c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -27,6 +27,7 @@ #include "exec/cpu-defs.h" #include "exec/cpu-interrupt.h" #include "exec/memop.h" +#include "hw/i386/apic.h" #include "hw/i386/topology.h" #include "qapi/qapi-types-common.h" #include "qemu/cpu-float.h" @@ -2349,7 +2350,7 @@ struct ArchCPU { =20 /* in order to simplify APIC support, we leave this pointer to the user */ - struct DeviceState *apic_state; + APICCommonState *apic_state; struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; Notifier machine_done; =20 @@ -2830,7 +2831,7 @@ bool cpu_svm_has_intercept(CPUX86State *env, uint32_t= type); =20 /* apic.c */ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); -void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, +void apic_handle_tpr_access_report(APICCommonState *s, target_ulong ip, TPRAccess access); =20 /* Special values for X86CPUVersion: */ diff --git a/target/i386/kvm/kvm_i386.h b/target/i386/kvm/kvm_i386.h index 5f83e8850a2..5c908fdd6a5 100644 --- a/target/i386/kvm/kvm_i386.h +++ b/target/i386/kvm/kvm_i386.h @@ -56,7 +56,7 @@ bool kvm_has_adjust_clock_stable(void); bool kvm_has_exception_payload(void); void kvm_synchronize_all_tsc(void); =20 -void kvm_get_apic_state(DeviceState *d, struct kvm_lapic_state *kapic); +void kvm_get_apic_state(APICCommonState *s, struct kvm_lapic_state *kapic); void kvm_put_apicbase(X86CPU *cpu, uint64_t value); =20 bool kvm_has_x2apic_api(void); diff --git a/target/i386/whpx/whpx-internal.h b/target/i386/whpx/whpx-inter= nal.h index 6633e9c4ca3..2dcad1f5650 100644 --- a/target/i386/whpx/whpx-internal.h +++ b/target/i386/whpx/whpx-internal.h @@ -5,6 +5,8 @@ #include #include =20 +#include "hw/i386/apic.h" + typedef enum WhpxBreakpointState { WHPX_BP_CLEARED =3D 0, WHPX_BP_SET_PENDING, @@ -44,7 +46,7 @@ struct whpx_state { }; =20 extern struct whpx_state whpx_global; -void whpx_apic_get(DeviceState *s); +void whpx_apic_get(APICCommonState *s); =20 #define WHV_E_UNKNOWN_CAPABILITY 0x80370300L =20 diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c index 1be9bfe36e9..82355f04631 100644 --- a/hw/i386/kvm/apic.c +++ b/hw/i386/kvm/apic.c @@ -60,9 +60,8 @@ static void kvm_put_apic_state(APICCommonState *s, struct= kvm_lapic_state *kapic kvm_apic_set_reg(kapic, 0x3e, s->divide_conf); } =20 -void kvm_get_apic_state(DeviceState *dev, struct kvm_lapic_state *kapic) +void kvm_get_apic_state(APICCommonState *s, struct kvm_lapic_state *kapic) { - APICCommonState *s =3D APIC_COMMON(dev); int i, v; =20 if (kvm_has_x2apic_api() && s->apicbase & MSR_IA32_APICBASE_EXTD) { diff --git a/hw/i386/vapic.c b/hw/i386/vapic.c index 0c1c92c4793..f1089f0a7c8 100644 --- a/hw/i386/vapic.c +++ b/hw/i386/vapic.c @@ -490,7 +490,7 @@ void vapic_report_tpr_access(DeviceState *dev, CPUState= *cs, target_ulong ip, } =20 typedef struct VAPICEnableTPRReporting { - DeviceState *apic; + APICCommonState *apic; bool enable; } VAPICEnableTPRReporting; =20 diff --git a/hw/i386/x86-cpu.c b/hw/i386/x86-cpu.c index c876e6709e0..1a86a853d5f 100644 --- a/hw/i386/x86-cpu.c +++ b/hw/i386/x86-cpu.c @@ -86,7 +86,7 @@ int cpu_get_pic_interrupt(CPUX86State *env) return intno; } =20 -DeviceState *cpu_get_current_apic(void) +APICCommonState *cpu_get_current_apic(void) { if (current_cpu) { X86CPU *cpu =3D X86_CPU(current_cpu); diff --git a/hw/intc/apic.c b/hw/intc/apic.c index c7680338563..cb35c80c75b 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -181,10 +181,8 @@ static void apic_local_deliver(APICCommonState *s, int= vector) } } =20 -void apic_deliver_pic_intr(DeviceState *dev, int level) +void apic_deliver_pic_intr(APICCommonState *s, int level) { - APICCommonState *s =3D APIC(dev); - if (level) { apic_local_deliver(s, APIC_LVT_LINT0); } else { @@ -301,10 +299,8 @@ static void apic_deliver_irq(uint32_t dest, uint8_t de= st_mode, apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_m= ode); } =20 -bool is_x2apic_mode(DeviceState *dev) +bool is_x2apic_mode(APICCommonState *s) { - APICCommonState *s =3D APIC(dev); - return s->apicbase & MSR_IA32_APICBASE_EXTD; } =20 @@ -388,15 +384,12 @@ static void apic_set_tpr(APICCommonState *s, uint8_t = val) } } =20 -int apic_get_highest_priority_irr(DeviceState *dev) +int apic_get_highest_priority_irr(APICCommonState *s) { - APICCommonState *s; - - if (!dev) { + if (!s) { /* no interrupts */ return -1; } - s =3D APIC_COMMON(dev); return get_highest_priority_int(s->irr); } =20 @@ -458,22 +451,19 @@ static int apic_irq_pending(APICCommonState *s) static void apic_update_irq(APICCommonState *s) { CPUState *cpu; - DeviceState *dev =3D (DeviceState *)s; =20 cpu =3D CPU(s->cpu); if (!qemu_cpu_is_self(cpu)) { cpu_interrupt(cpu, CPU_INTERRUPT_POLL); } else if (apic_irq_pending(s) > 0) { cpu_interrupt(cpu, CPU_INTERRUPT_HARD); - } else if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) { + } else if (!apic_accept_pic_intr(s) || !pic_get_output(isa_pic)) { cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); } } =20 -void apic_poll_irq(DeviceState *dev) +void apic_poll_irq(APICCommonState *s) { - APICCommonState *s =3D APIC(dev); - apic_sync_vapic(s, SYNC_FROM_VAPIC); apic_update_irq(s); } @@ -516,7 +506,7 @@ static void apic_eoi(APICCommonState *s) =20 static bool apic_match_dest(APICCommonState *apic, uint32_t dest) { - if (is_x2apic_mode(&apic->parent_obj)) { + if (is_x2apic_mode(apic)) { return apic->initial_apic_id =3D=3D dest; } else { return apic->id =3D=3D (uint8_t)dest; @@ -550,7 +540,7 @@ static void apic_get_broadcast_bitmask(uint32_t *delive= r_bitmask, for (i =3D 0; i < max_apics; i++) { apic_iter =3D local_apics[i]; if (apic_iter) { - bool apic_in_x2apic =3D is_x2apic_mode(&apic_iter->parent_obj); + bool apic_in_x2apic =3D is_x2apic_mode(apic_iter); =20 if (is_x2apic_broadcast && apic_in_x2apic) { apic_set_bit(deliver_bitmask, i); @@ -642,27 +632,24 @@ static void apic_startup(APICCommonState *s, int vect= or_num) cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI); } =20 -void apic_sipi(DeviceState *dev) +void apic_sipi(APICCommonState *s) { - APICCommonState *s =3D APIC(dev); - if (!s->wait_for_sipi) return; cpu_x86_load_seg_cache_sipi(s->cpu, s->sipi_vector); s->wait_for_sipi =3D 0; } =20 -static void apic_deliver(DeviceState *dev, uint32_t dest, uint8_t dest_mod= e, +static void apic_deliver(APICCommonState *s, uint32_t dest, uint8_t dest_m= ode, uint8_t delivery_mode, uint8_t vector_num, uint8_t trigger_mode, uint8_t dest_shorthand) { - APICCommonState *s =3D APIC(dev); APICCommonState *apic_iter; uint32_t deliver_bitmask_size =3D max_apic_words * sizeof(uint32_t); g_autofree uint32_t *deliver_bitmask =3D g_new(uint32_t, max_apic_word= s); uint32_t current_apic_id; =20 - if (is_x2apic_mode(dev)) { + if (is_x2apic_mode(s)) { current_apic_id =3D s->initial_apic_id; } else { current_apic_id =3D s->id; @@ -709,18 +696,15 @@ static void apic_deliver(DeviceState *dev, uint32_t d= est, uint8_t dest_mode, =20 static bool apic_check_pic(APICCommonState *s) { - DeviceState *dev =3D (DeviceState *)s; - - if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) { + if (!apic_accept_pic_intr(s) || !pic_get_output(isa_pic)) { return false; } - apic_deliver_pic_intr(dev, 1); + apic_deliver_pic_intr(s, 1); return true; } =20 -int apic_get_interrupt(DeviceState *dev) +int apic_get_interrupt(APICCommonState *s) { - APICCommonState *s =3D APIC(dev); int intno; =20 /* if the APIC is installed or enabled, we let the 8259 handle the @@ -752,9 +736,8 @@ int apic_get_interrupt(DeviceState *dev) return intno; } =20 -int apic_accept_pic_intr(DeviceState *dev) +int apic_accept_pic_intr(APICCommonState *s) { - APICCommonState *s =3D APIC(dev); uint32_t lvt0; =20 if (!s) @@ -788,20 +771,18 @@ static void apic_timer(void *opaque) =20 static int apic_register_read(int index, uint64_t *value) { - DeviceState *dev; APICCommonState *s; uint32_t val; int ret =3D 0; =20 - dev =3D cpu_get_current_apic(); - if (!dev) { + s =3D cpu_get_current_apic(); + if (!s) { return -1; } - s =3D APIC(dev); =20 switch(index) { case 0x02: /* id */ - if (is_x2apic_mode(dev)) { + if (is_x2apic_mode(s)) { val =3D s->initial_apic_id; } else { val =3D s->id << 24; @@ -828,14 +809,14 @@ static int apic_register_read(int index, uint64_t *va= lue) val =3D 0; break; case 0x0d: - if (is_x2apic_mode(dev)) { + if (is_x2apic_mode(s)) { val =3D s->extended_log_dest; } else { val =3D s->log_dest << 24; } break; case 0x0e: - if (is_x2apic_mode(dev)) { + if (is_x2apic_mode(s)) { val =3D 0; ret =3D -1; } else { @@ -902,14 +883,14 @@ static uint64_t apic_mem_read(void *opaque, hwaddr ad= dr, unsigned size) =20 int apic_msr_read(int index, uint64_t *val) { - DeviceState *dev; + APICCommonState *s; =20 - dev =3D cpu_get_current_apic(); - if (!dev) { + s =3D cpu_get_current_apic(); + if (!s) { return -1; } =20 - if (!is_x2apic_mode(dev)) { + if (!is_x2apic_mode(s)) { return -1; } =20 @@ -943,20 +924,18 @@ static void apic_send_msi(MSIMessage *msi) =20 static int apic_register_write(int index, uint64_t val) { - DeviceState *dev; APICCommonState *s; =20 - dev =3D cpu_get_current_apic(); - if (!dev) { + s =3D cpu_get_current_apic(); + if (!s) { return -1; } - s =3D APIC(dev); =20 trace_apic_register_write(index, val); =20 switch(index) { case 0x02: - if (is_x2apic_mode(dev)) { + if (is_x2apic_mode(s)) { return -1; } =20 @@ -979,14 +958,14 @@ static int apic_register_write(int index, uint64_t va= l) apic_eoi(s); break; case 0x0d: - if (is_x2apic_mode(dev)) { + if (is_x2apic_mode(s)) { return -1; } =20 s->log_dest =3D val >> 24; break; case 0x0e: - if (is_x2apic_mode(dev)) { + if (is_x2apic_mode(s)) { return -1; } =20 @@ -1005,20 +984,20 @@ static int apic_register_write(int index, uint64_t v= al) uint32_t dest; =20 s->icr[0] =3D val; - if (is_x2apic_mode(dev)) { + if (is_x2apic_mode(s)) { s->icr[1] =3D val >> 32; dest =3D s->icr[1]; } else { dest =3D (s->icr[1] >> 24) & 0xff; } =20 - apic_deliver(dev, dest, (s->icr[0] >> 11) & 1, + apic_deliver(s, dest, (s->icr[0] >> 11) & 1, (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), (s->icr[0] >> 15) & 1, (s->icr[0] >> 18) & 3); break; } case 0x31: - if (is_x2apic_mode(dev)) { + if (is_x2apic_mode(s)) { return -1; } =20 @@ -1053,7 +1032,7 @@ static int apic_register_write(int index, uint64_t va= l) case 0x3f: { int vector =3D val & 0xff; =20 - if (!is_x2apic_mode(dev)) { + if (!is_x2apic_mode(s)) { return -1; } =20 @@ -1063,7 +1042,7 @@ static int apic_register_write(int index, uint64_t va= l) * - Trigger mode: 0 (Edge) * - Delivery mode: 0 (Fixed) */ - apic_deliver(dev, 0, 0, APIC_DM_FIXED, vector, 0, 1); + apic_deliver(s, 0, 0, APIC_DM_FIXED, vector, 0, 1); =20 break; } @@ -1102,14 +1081,14 @@ static void apic_mem_write(void *opaque, hwaddr add= r, uint64_t val, =20 int apic_msr_write(int index, uint64_t val) { - DeviceState *dev; + APICCommonState *s; =20 - dev =3D cpu_get_current_apic(); - if (!dev) { + s =3D cpu_get_current_apic(); + if (!s) { return -1; } =20 - if (!is_x2apic_mode(dev)) { + if (!is_x2apic_mode(s)) { return -1; } =20 diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 394fe020134..ec9e978b0b4 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -35,12 +35,11 @@ =20 bool apic_report_tpr_access; =20 -int cpu_set_apic_base(DeviceState *dev, uint64_t val) +int cpu_set_apic_base(APICCommonState *s, uint64_t val) { trace_cpu_set_apic_base(val); =20 - if (dev) { - APICCommonState *s =3D APIC_COMMON(dev); + if (s) { APICCommonClass *info =3D APIC_COMMON_GET_CLASS(s); /* Reset possibly modified xAPIC ID */ s->id =3D s->initial_apic_id; @@ -50,10 +49,9 @@ int cpu_set_apic_base(DeviceState *dev, uint64_t val) return 0; } =20 -uint64_t cpu_get_apic_base(DeviceState *dev) +uint64_t cpu_get_apic_base(APICCommonState *s) { - if (dev) { - APICCommonState *s =3D APIC_COMMON(dev); + if (s) { trace_cpu_get_apic_base((uint64_t)s->apicbase); return s->apicbase; } else { @@ -62,52 +60,43 @@ uint64_t cpu_get_apic_base(DeviceState *dev) } } =20 -bool cpu_is_apic_enabled(DeviceState *dev) +bool cpu_is_apic_enabled(APICCommonState *s) { - APICCommonState *s; - - if (!dev) { + if (!s) { return false; } =20 - s =3D APIC_COMMON(dev); - return s->apicbase & MSR_IA32_APICBASE_ENABLE; } =20 -void cpu_set_apic_tpr(DeviceState *dev, uint8_t val) +void cpu_set_apic_tpr(APICCommonState *s, uint8_t val) { - APICCommonState *s; APICCommonClass *info; =20 - if (!dev) { + if (!s) { return; } =20 - s =3D APIC_COMMON(dev); info =3D APIC_COMMON_GET_CLASS(s); =20 info->set_tpr(s, val); } =20 -uint8_t cpu_get_apic_tpr(DeviceState *dev) +uint8_t cpu_get_apic_tpr(APICCommonState *s) { - APICCommonState *s; APICCommonClass *info; =20 - if (!dev) { + if (!s) { return 0; } =20 - s =3D APIC_COMMON(dev); info =3D APIC_COMMON_GET_CLASS(s); =20 return info->get_tpr(s); } =20 -void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable) +void apic_enable_tpr_access_reporting(APICCommonState *s, bool enable) { - APICCommonState *s =3D APIC_COMMON(dev); APICCommonClass *info =3D APIC_COMMON_GET_CLASS(s); =20 apic_report_tpr_access =3D enable; @@ -116,26 +105,22 @@ void apic_enable_tpr_access_reporting(DeviceState *de= v, bool enable) } } =20 -void apic_enable_vapic(DeviceState *dev, hwaddr paddr) +void apic_enable_vapic(APICCommonState *s, hwaddr paddr) { - APICCommonState *s =3D APIC_COMMON(dev); APICCommonClass *info =3D APIC_COMMON_GET_CLASS(s); =20 s->vapic_paddr =3D paddr; info->vapic_base_update(s); } =20 -void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip, +void apic_handle_tpr_access_report(APICCommonState *s, target_ulong ip, TPRAccess access) { - APICCommonState *s =3D APIC_COMMON(dev); - vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access); } =20 -void apic_deliver_nmi(DeviceState *dev) +void apic_deliver_nmi(APICCommonState *s) { - APICCommonState *s =3D APIC_COMMON(dev); APICCommonClass *info =3D APIC_COMMON_GET_CLASS(s); =20 info->external_nmi(s); @@ -193,16 +178,14 @@ uint32_t apic_get_current_count(APICCommonState *s) return val; } =20 -void apic_init_reset(DeviceState *dev) +void apic_init_reset(APICCommonState *s) { - APICCommonState *s; APICCommonClass *info; int i; =20 - if (!dev) { + if (!s) { return; } - s =3D APIC_COMMON(dev); s->tpr =3D 0; s->spurious_vec =3D 0xff; s->log_dest =3D 0; @@ -233,13 +216,12 @@ void apic_init_reset(DeviceState *dev) } } =20 -void apic_designate_bsp(DeviceState *dev, bool bsp) +void apic_designate_bsp(APICCommonState *s, bool bsp) { - if (dev =3D=3D NULL) { + if (s =3D=3D NULL) { return; } =20 - APICCommonState *s =3D APIC_COMMON(dev); if (bsp) { s->apicbase |=3D MSR_IA32_APICBASE_BSP; } else { @@ -262,7 +244,7 @@ static void apic_reset_common(DeviceState *dev) s->vapic_paddr =3D 0; info->vapic_base_update(s); =20 - apic_init_reset(dev); + apic_init_reset(s); } =20 static const VMStateDescription vmstate_apic_common; diff --git a/target/i386/cpu-apic.c b/target/i386/cpu-apic.c index 242a05fdbe9..564c1288e47 100644 --- a/target/i386/cpu-apic.c +++ b/target/i386/cpu-apic.c @@ -41,34 +41,31 @@ APICCommonClass *apic_get_class(Error **errp) =20 void x86_cpu_apic_create(X86CPU *cpu, Error **errp) { - APICCommonState *apic; APICCommonClass *apic_class =3D apic_get_class(errp); =20 if (!apic_class) { return; } =20 - cpu->apic_state =3D DEVICE(object_new_with_class(OBJECT_CLASS(apic_cla= ss))); + cpu->apic_state =3D APIC_COMMON(object_new_with_class(OBJECT_CLASS(api= c_class))); object_property_add_child(OBJECT(cpu), "lapic", OBJECT(cpu->apic_state)); object_unref(OBJECT(cpu->apic_state)); =20 /* TODO: convert to link<> */ - apic =3D APIC_COMMON(cpu->apic_state); - apic->cpu =3D cpu; - apic->apicbase =3D APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE; + cpu->apic_state->cpu =3D cpu; + cpu->apic_state->apicbase =3D APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE= _ENABLE; =20 /* * apic_common_set_id needs to check if the CPU has x2APIC - * feature in case APIC ID >=3D 255, so we need to set apic->cpu + * feature in case APIC ID >=3D 255, so we need to set cpu->apic_state= ->cpu * before setting APIC ID */ - qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id); + qdev_prop_set_uint32(DEVICE(cpu->apic_state), "id", cpu->apic_id); } =20 void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) { - APICCommonState *apic; static bool apic_mmio_map_once; =20 if (cpu->apic_state =3D=3D NULL) { @@ -77,12 +74,11 @@ void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) qdev_realize(DEVICE(cpu->apic_state), NULL, errp); =20 /* Map APIC MMIO area */ - apic =3D APIC_COMMON(cpu->apic_state); if (!apic_mmio_map_once) { memory_region_add_subregion_overlap(get_system_memory(), - apic->apicbase & + cpu->apic_state->apicbase & MSR_IA32_APICBASE_BASE, - &apic->io_memory, + &cpu->apic_state->io_memory, 0x1000); apic_mmio_map_once =3D true; } diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c index a72ed93bd2f..67bf31e0caa 100644 --- a/target/i386/cpu-dump.c +++ b/target/i386/cpu-dump.c @@ -291,7 +291,7 @@ static void dump_apic_interrupt(const char *name, uint3= 2_t *ireg_tab, void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) { X86CPU *cpu =3D X86_CPU(cs); - APICCommonState *s =3D APIC_COMMON(cpu->apic_state); + APICCommonState *s =3D cpu->apic_state; if (!s) { qemu_printf("local apic state not available\n"); return; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 455caff6b23..0a66e1fec93 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8789,7 +8789,7 @@ void x86_cpu_after_reset(X86CPU *cpu) } =20 if (cpu->apic_state) { - device_cold_reset(cpu->apic_state); + device_cold_reset(DEVICE(cpu->apic_state)); } #endif } diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 309f043373c..f7a6ef650af 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -5029,7 +5029,7 @@ static int kvm_get_mp_state(X86CPU *cpu) =20 static int kvm_get_apic(X86CPU *cpu) { - DeviceState *apic =3D cpu->apic_state; + APICCommonState *apic =3D cpu->apic_state; struct kvm_lapic_state kapic; int ret; =20 diff --git a/target/i386/whpx/whpx-apic.c b/target/i386/whpx/whpx-apic.c index e1ef6d4e6d4..afcb25843b5 100644 --- a/target/i386/whpx/whpx-apic.c +++ b/target/i386/whpx/whpx-apic.c @@ -151,9 +151,8 @@ static void whpx_apic_put(CPUState *cs, run_on_cpu_data= data) } } =20 -void whpx_apic_get(DeviceState *dev) +void whpx_apic_get(APICCommonState *s) { - APICCommonState *s =3D APIC_COMMON(dev); CPUState *cpu =3D CPU(s->cpu); struct whpx_lapic_state kapic; =20 --=20 2.51.0