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This restricts the register API usage to only the base registers (from 0x0 to 0xec). This also removes all the custom code that was creating register descriptors for the register API and was leading to memory leaks when the device was finalized. Reviewed-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Luc Michel Message-ID: <20251017161809.235740-7-luc.michel@amd.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/net/xlnx-versal-canfd.h | 8 - hw/net/can/xlnx-versal-canfd.c | 303 ++--------------------------- 2 files changed, 15 insertions(+), 296 deletions(-) diff --git a/include/hw/net/xlnx-versal-canfd.h b/include/hw/net/xlnx-versa= l-canfd.h index ad3104dd13f..396f90d6dc1 100644 --- a/include/hw/net/xlnx-versal-canfd.h +++ b/include/hw/net/xlnx-versal-canfd.h @@ -54,14 +54,6 @@ typedef struct XlnxVersalCANFDState { qemu_irq irq_addr_err; =20 RegisterInfo reg_info[XLNX_VERSAL_CANFD_R_MAX]; - RegisterAccessInfo *tx_regs; - RegisterAccessInfo *rx0_regs; - RegisterAccessInfo *rx1_regs; - RegisterAccessInfo *af_regs; - RegisterAccessInfo *txe_regs; - RegisterAccessInfo *rx_mailbox_regs; - RegisterAccessInfo *af_mask_regs_mailbox; - uint32_t regs[XLNX_VERSAL_CANFD_R_MAX]; =20 ptimer_state *canfd_timer; diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c index 04f9a6d57d7..5735639b85a 100644 --- a/hw/net/can/xlnx-versal-canfd.c +++ b/hw/net/can/xlnx-versal-canfd.c @@ -1426,46 +1426,6 @@ static void filter_reg_write(XlnxVersalCANFDState *s= , hwaddr addr, } } =20 -static uint64_t filter_mask(RegisterInfo *reg, uint64_t val64) -{ - XlnxVersalCANFDState *s =3D XILINX_CANFD(reg->opaque); - uint32_t reg_idx =3D (reg->access->addr) / 4; - uint32_t val =3D val64; - uint32_t filter_offset =3D (reg_idx - R_AFMR_REGISTER) / 2; - - if (!(s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER] & - (1 << filter_offset))) { - s->regs[reg_idx] =3D val; - } else { - g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); - - qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d not enabl= ed\n", - path, filter_offset + 1); - } - - return s->regs[reg_idx]; -} - -static uint64_t filter_id(RegisterInfo *reg, uint64_t val64) -{ - XlnxVersalCANFDState *s =3D XILINX_CANFD(reg->opaque); - hwaddr reg_idx =3D (reg->access->addr) / 4; - uint32_t val =3D val64; - uint32_t filter_offset =3D (reg_idx - R_AFIR_REGISTER) / 2; - - if (!(s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER] & - (1 << filter_offset))) { - s->regs[reg_idx] =3D val; - } else { - g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); - - qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d not enabl= ed\n", - path, filter_offset + 1); - } - - return s->regs[reg_idx]; -} - static uint64_t canfd_tx_fifo_status_prew(RegisterInfo *reg, uint64_t val6= 4) { XlnxVersalCANFDState *s =3D XILINX_CANFD(reg->opaque); @@ -1591,125 +1551,6 @@ static uint64_t canfd_write_check_prew(RegisterInfo= *reg, uint64_t val64) return 0; } =20 -static const RegisterAccessInfo canfd_tx_regs[] =3D { - { .name =3D "TB_ID_REGISTER", .addr =3D A_TB_ID_REGISTER, - },{ .name =3D "TB0_DLC_REGISTER", .addr =3D A_TB0_DLC_REGISTER, - },{ .name =3D "TB_DW0_REGISTER", .addr =3D A_TB_DW0_REGISTER, - },{ .name =3D "TB_DW1_REGISTER", .addr =3D A_TB_DW1_REGISTER, - },{ .name =3D "TB_DW2_REGISTER", .addr =3D A_TB_DW2_REGISTER, - },{ .name =3D "TB_DW3_REGISTER", .addr =3D A_TB_DW3_REGISTER, - },{ .name =3D "TB_DW4_REGISTER", .addr =3D A_TB_DW4_REGISTER, - },{ .name =3D "TB_DW5_REGISTER", .addr =3D A_TB_DW5_REGISTER, - },{ .name =3D "TB_DW6_REGISTER", .addr =3D A_TB_DW6_REGISTER, - },{ .name =3D "TB_DW7_REGISTER", .addr =3D A_TB_DW7_REGISTER, - },{ .name =3D "TB_DW8_REGISTER", .addr =3D A_TB_DW8_REGISTER, - },{ .name =3D "TB_DW9_REGISTER", .addr =3D A_TB_DW9_REGISTER, - },{ .name =3D "TB_DW10_REGISTER", .addr =3D A_TB_DW10_REGISTER, - },{ .name =3D "TB_DW11_REGISTER", .addr =3D A_TB_DW11_REGISTER, - },{ .name =3D "TB_DW12_REGISTER", .addr =3D A_TB_DW12_REGISTER, - },{ .name =3D "TB_DW13_REGISTER", .addr =3D A_TB_DW13_REGISTER, - },{ .name =3D "TB_DW14_REGISTER", .addr =3D A_TB_DW14_REGISTER, - },{ .name =3D "TB_DW15_REGISTER", .addr =3D A_TB_DW15_REGISTER, - } -}; - -static const RegisterAccessInfo canfd_rx0_regs[] =3D { - { .name =3D "RB_ID_REGISTER", .addr =3D A_RB_ID_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DLC_REGISTER", .addr =3D A_RB_DLC_REGISTER, - .ro =3D 0xfe1fffff, - },{ .name =3D "RB_DW0_REGISTER", .addr =3D A_RB_DW0_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW1_REGISTER", .addr =3D A_RB_DW1_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW2_REGISTER", .addr =3D A_RB_DW2_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW3_REGISTER", .addr =3D A_RB_DW3_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW4_REGISTER", .addr =3D A_RB_DW4_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW5_REGISTER", .addr =3D A_RB_DW5_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW6_REGISTER", .addr =3D A_RB_DW6_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW7_REGISTER", .addr =3D A_RB_DW7_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW8_REGISTER", .addr =3D A_RB_DW8_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW9_REGISTER", .addr =3D A_RB_DW9_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW10_REGISTER", .addr =3D A_RB_DW10_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW11_REGISTER", .addr =3D A_RB_DW11_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW12_REGISTER", .addr =3D A_RB_DW12_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW13_REGISTER", .addr =3D A_RB_DW13_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW14_REGISTER", .addr =3D A_RB_DW14_REGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW15_REGISTER", .addr =3D A_RB_DW15_REGISTER, - .ro =3D 0xffffffff, - } -}; - -static const RegisterAccessInfo canfd_rx1_regs[] =3D { - { .name =3D "RB_ID_REGISTER_1", .addr =3D A_RB_ID_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DLC_REGISTER_1", .addr =3D A_RB_DLC_REGISTER_1, - .ro =3D 0xfe1fffff, - },{ .name =3D "RB0_DW0_REGISTER_1", .addr =3D A_RB0_DW0_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW1_REGISTER_1", .addr =3D A_RB_DW1_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW2_REGISTER_1", .addr =3D A_RB_DW2_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW3_REGISTER_1", .addr =3D A_RB_DW3_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW4_REGISTER_1", .addr =3D A_RB_DW4_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW5_REGISTER_1", .addr =3D A_RB_DW5_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW6_REGISTER_1", .addr =3D A_RB_DW6_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW7_REGISTER_1", .addr =3D A_RB_DW7_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW8_REGISTER_1", .addr =3D A_RB_DW8_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW9_REGISTER_1", .addr =3D A_RB_DW9_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW10_REGISTER_1", .addr =3D A_RB_DW10_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW11_REGISTER_1", .addr =3D A_RB_DW11_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW12_REGISTER_1", .addr =3D A_RB_DW12_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW13_REGISTER_1", .addr =3D A_RB_DW13_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW14_REGISTER_1", .addr =3D A_RB_DW14_REGISTER_1, - .ro =3D 0xffffffff, - },{ .name =3D "RB_DW15_REGISTER_1", .addr =3D A_RB_DW15_REGISTER_1, - .ro =3D 0xffffffff, - } -}; - -/* Acceptance filter registers. */ -static const RegisterAccessInfo canfd_af_regs[] =3D { - { .name =3D "AFMR_REGISTER", .addr =3D A_AFMR_REGISTER, - .pre_write =3D filter_mask, - },{ .name =3D "AFIR_REGISTER", .addr =3D A_AFIR_REGISTER, - .pre_write =3D filter_id, - } -}; - -static const RegisterAccessInfo canfd_txe_regs[] =3D { - { .name =3D "TXE_FIFO_TB_ID_REGISTER", .addr =3D A_TXE_FIFO_TB_ID_R= EGISTER, - .ro =3D 0xffffffff, - },{ .name =3D "TXE_FIFO_TB_DLC_REGISTER", .addr =3D A_TXE_FIFO_TB_DLC= _REGISTER, - .ro =3D 0xffffffff, - } -}; - static const RegisterAccessInfo canfd_regs_info[] =3D { { .name =3D "SOFTWARE_RESET_REGISTER", .addr =3D A_SOFTWARE_RESET_R= EGISTER, .pre_write =3D canfd_srr_pre_write, @@ -1915,6 +1756,16 @@ static const MemoryRegionOps canfd_ops =3D { }, }; =20 +static const MemoryRegionOps canfd_regs_ops =3D { + .read =3D register_read_memory, + .write =3D register_write_memory, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + static void canfd_reset(DeviceState *dev) { XlnxVersalCANFDState *s =3D XILINX_CANFD(dev); @@ -1994,140 +1845,16 @@ static int xlnx_canfd_connect_to_bus(XlnxVersalCAN= FDState *s, return can_bus_insert_client(bus, &s->bus_client); } =20 -#define NUM_REG_PER_AF ARRAY_SIZE(canfd_af_regs) -#define NUM_AF 32 -#define NUM_REG_PER_TXE ARRAY_SIZE(canfd_txe_regs) -#define NUM_TXE 32 - -static int canfd_populate_regarray(XlnxVersalCANFDState *s, - RegisterInfoArray *r_array, int pos, - const RegisterAccessInfo *rae, - int num_rae) -{ - int i; - - for (i =3D 0; i < num_rae; i++) { - int index =3D rae[i].addr / 4; - RegisterInfo *r =3D &s->reg_info[index]; - - *r =3D (RegisterInfo) { - .data =3D &s->regs[index], - .data_size =3D sizeof(uint32_t), - .access =3D &rae[i], - .opaque =3D OBJECT(s), - }; - - r_array->r[i + pos] =3D r; - } - return i + pos; -} - -static void canfd_create_rai(RegisterAccessInfo *rai_array, - const RegisterAccessInfo *canfd_regs, - int template_rai_array_sz, - int num_template_to_copy) -{ - int i; - int reg_num; - - for (reg_num =3D 0; reg_num < num_template_to_copy; reg_num++) { - int pos =3D reg_num * template_rai_array_sz; - - memcpy(rai_array + pos, canfd_regs, - template_rai_array_sz * sizeof(RegisterAccessInfo)); - - for (i =3D 0; i < template_rai_array_sz; i++) { - const char *name =3D canfd_regs[i].name; - uint64_t addr =3D canfd_regs[i].addr; - rai_array[i + pos].name =3D g_strdup_printf("%s%d", name, reg_= num); - rai_array[i + pos].addr =3D addr + pos * 4; - } - } -} - -static RegisterInfoArray *canfd_create_regarray(XlnxVersalCANFDState *s) -{ - const char *device_prefix =3D object_get_typename(OBJECT(s)); - uint64_t memory_size =3D XLNX_VERSAL_CANFD_R_MAX * 4; - int num_regs; - int pos =3D 0; - RegisterInfoArray *r_array; - - num_regs =3D ARRAY_SIZE(canfd_regs_info) + - s->cfg.tx_fifo * NUM_REGS_PER_MSG_SPACE + - s->cfg.rx0_fifo * NUM_REGS_PER_MSG_SPACE + - NUM_AF * NUM_REG_PER_AF + - NUM_TXE * NUM_REG_PER_TXE; - - s->tx_regs =3D g_new0(RegisterAccessInfo, - s->cfg.tx_fifo * ARRAY_SIZE(canfd_tx_regs)); - - canfd_create_rai(s->tx_regs, canfd_tx_regs, - ARRAY_SIZE(canfd_tx_regs), s->cfg.tx_fifo); - - s->rx0_regs =3D g_new0(RegisterAccessInfo, - s->cfg.rx0_fifo * ARRAY_SIZE(canfd_rx0_regs)); - - canfd_create_rai(s->rx0_regs, canfd_rx0_regs, - ARRAY_SIZE(canfd_rx0_regs), s->cfg.rx0_fifo); - - s->af_regs =3D g_new0(RegisterAccessInfo, - NUM_AF * ARRAY_SIZE(canfd_af_regs)); - - canfd_create_rai(s->af_regs, canfd_af_regs, - ARRAY_SIZE(canfd_af_regs), NUM_AF); - - s->txe_regs =3D g_new0(RegisterAccessInfo, - NUM_TXE * ARRAY_SIZE(canfd_txe_regs)); - - canfd_create_rai(s->txe_regs, canfd_txe_regs, - ARRAY_SIZE(canfd_txe_regs), NUM_TXE); - - if (s->cfg.enable_rx_fifo1) { - num_regs +=3D s->cfg.rx1_fifo * NUM_REGS_PER_MSG_SPACE; - - s->rx1_regs =3D g_new0(RegisterAccessInfo, - s->cfg.rx1_fifo * ARRAY_SIZE(canfd_rx1_regs)); - - canfd_create_rai(s->rx1_regs, canfd_rx1_regs, - ARRAY_SIZE(canfd_rx1_regs), s->cfg.rx1_fifo); - } - - r_array =3D g_new0(RegisterInfoArray, 1); - r_array->r =3D g_new0(RegisterInfo * , num_regs); - r_array->num_elements =3D num_regs; - r_array->prefix =3D device_prefix; - - pos =3D canfd_populate_regarray(s, r_array, pos, - canfd_regs_info, - ARRAY_SIZE(canfd_regs_info)); - pos =3D canfd_populate_regarray(s, r_array, pos, - s->tx_regs, s->cfg.tx_fifo * - NUM_REGS_PER_MSG_SPACE); - pos =3D canfd_populate_regarray(s, r_array, pos, - s->rx0_regs, s->cfg.rx0_fifo * - NUM_REGS_PER_MSG_SPACE); - if (s->cfg.enable_rx_fifo1) { - pos =3D canfd_populate_regarray(s, r_array, pos, - s->rx1_regs, s->cfg.rx1_fifo * - NUM_REGS_PER_MSG_SPACE); - } - pos =3D canfd_populate_regarray(s, r_array, pos, - s->af_regs, NUM_AF * NUM_REG_PER_AF); - pos =3D canfd_populate_regarray(s, r_array, pos, - s->txe_regs, NUM_TXE * NUM_REG_PER_TXE); - - memory_region_init_io(&r_array->mem, OBJECT(s), &canfd_ops, r_array, - device_prefix, memory_size); - return r_array; -} - static void canfd_realize(DeviceState *dev, Error **errp) { XlnxVersalCANFDState *s =3D XILINX_CANFD(dev); RegisterInfoArray *reg_array; =20 - reg_array =3D canfd_create_regarray(s); + reg_array =3D register_init_block32(dev, canfd_regs_info, + ARRAY_SIZE(canfd_regs_info), s->reg_= info, + s->regs, &canfd_regs_ops, false, + A_RX_FIFO_WATERMARK_REGISTER + + sizeof(uint32_t)); memory_region_add_subregion(&s->iomem, 0x00, ®_array->mem); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_canfd_int); --=20 2.51.0