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Tue, 21 Oct 2025 09:21:22 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Daniel Henrique Barboza , Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , Jim Shu Subject: [PATCH v3 17/18] hw/misc: riscv_wgchecker: Check the slot settings in translate Date: Wed, 22 Oct 2025 00:21:07 +0800 Message-ID: <20251021162108.585468-3-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251021155548.584543-1-jim.shu@sifive.com> References: <20251021155548.584543-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=jim.shu@sifive.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1761063793595154100 Content-Type: text/plain; charset="utf-8" The final part of wgChecker we need to implement is actually using the wgChecker slots programmed by guest to determine whether to block the transaction or not. Since this means we now change transaction mappings when the guest writes to wgChecker slots, we must also call the IOMMU notifiers at that point. One tricky part here is that the perm of 'blocked_io_as' is the condition of deny access. For example, if wgChecker only permits RO access, the perm of 'downstream_as' will be IOMMU_RO and the perm of 'blocked_io_as' will be IOMMU_WO. Signed-off-by: Jim Shu Reviewed-by: Daniel Henrique Barboza --- hw/misc/riscv_wgchecker.c | 70 ++++++++++++++++++++++++++++++++++++--- hw/misc/trace-events | 1 + 2 files changed, 67 insertions(+), 4 deletions(-) diff --git a/hw/misc/riscv_wgchecker.c b/hw/misc/riscv_wgchecker.c index b4acdaa294..c23b076b1c 100644 --- a/hw/misc/riscv_wgchecker.c +++ b/hw/misc/riscv_wgchecker.c @@ -99,6 +99,52 @@ REG32(SLOT_CFG, 0x010) #define P_READ (1 << 0) #define P_WRITE (1 << 1) =20 +static IOMMUAccessFlags wgc_perm_to_iommu_flags(int wgc_perm) +{ + if (wgc_perm =3D=3D (P_READ | P_WRITE)) { + return IOMMU_RW; + } else if (wgc_perm & P_WRITE) { + return IOMMU_WO; + } else if (wgc_perm & P_READ) { + return IOMMU_RO; + } else { + return IOMMU_NONE; + } +} + +static void wgchecker_iommu_notify_all(RISCVWgCheckerState *s) +{ + /* + * Do tlb_flush() to whole address space via memory_region_notify_iomm= u() + * when wgChecker changes it's config. + */ + + IOMMUTLBEvent event =3D { + .entry =3D { + .addr_mask =3D -1ULL, + } + }; + + trace_riscv_wgchecker_iommu_notify_all(); + + for (int i =3D 0; i < WGC_NUM_REGIONS; i++) { + WgCheckerRegion *region =3D &s->mem_regions[i]; + uint32_t nworlds =3D worldguard_config->nworlds; + + if (!region->downstream) { + continue; + } + event.entry.iova =3D 0; + event.entry.translated_addr =3D 0; + event.type =3D IOMMU_NOTIFIER_UNMAP; + event.entry.perm =3D IOMMU_NONE; + + for (int wid =3D 0; wid < nworlds; wid++) { + memory_region_notify_iommu(®ion->upstream, wid, event); + } + } +} + static void decode_napot(hwaddr a, hwaddr *sa, hwaddr *ea) { /* @@ -317,6 +363,9 @@ static IOMMUTLBEntry riscv_wgc_translate(IOMMUMemoryReg= ion *iommu, { WgCheckerRegion *region =3D container_of(iommu, WgCheckerRegion, upstr= eam); RISCVWgCheckerState *s =3D RISCV_WGCHECKER(region->wgchecker); + bool is_write; + WgAccessResult result; + int wgc_perm; hwaddr phys_addr; uint64_t region_size; =20 @@ -335,18 +384,25 @@ static IOMMUTLBEntry riscv_wgc_translate(IOMMUMemoryR= egion *iommu, * Look at the wgChecker configuration for this address, and * return a TLB entry directing the transaction at either * downstream_as or blocked_io_as, as appropriate. - * For the moment, always permit accesses. */ =20 /* Use physical address instead of offset */ phys_addr =3D addr + region->region_offset; + is_write =3D (flags =3D=3D IOMMU_WO); =20 - is_success =3D true; + result =3D wgc_check_access(s, phys_addr, iommu_idx, is_write); =20 trace_riscv_wgchecker_translate(phys_addr, flags, - iommu_idx, is_success ? "pass" : "block"); + iommu_idx, result.is_success ? "pass" : "block"); =20 - ret.target_as =3D is_success ? ®ion->downstream_as : ®ion->block= ed_io_as; + wgc_perm =3D result.perm; + if (!result.is_success) { + /* if target_as is blocked_io_as, the perm is the condition of den= y access. */ + wgc_perm ^=3D (P_READ | P_WRITE); + } + ret.perm =3D wgc_perm_to_iommu_flags(wgc_perm); + + ret.target_as =3D result.is_success ? ®ion->downstream_as : ®ion= ->blocked_io_as; return ret; } =20 @@ -612,6 +668,9 @@ static void riscv_wgchecker_writeq(void *opaque, hwaddr= addr, break; } =20 + /* Flush softmmu TLB when wgChecker changes config. */ + wgchecker_iommu_notify_all(s); + return; } =20 @@ -708,6 +767,9 @@ static void riscv_wgchecker_writel(void *opaque, hwaddr= addr, break; } =20 + /* Flush softmmu TLB when wgChecker changes config. */ + wgchecker_iommu_notify_all(s); + return; } =20 diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 7617b8843f..8505a9f964 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -417,3 +417,4 @@ riscv_wgchecker_mmio_write(uint64_t base, uint64_t offs= et, unsigned int size, ui riscv_wgchecker_mem_blocked_read(uint64_t phys_addr, unsigned size, uint32= _t wid) "phys_addr =3D 0x%" PRIx64 ", size =3D %u, wid =3D %" PRIu32 riscv_wgchecker_mem_blocked_write(uint64_t phys_addr, uint64_t data, unsig= ned size, uint32_t wid) "phys_addr =3D 0x%" PRIx64 ", data =3D 0x%" PRIx64 = ", size =3D %u, wid =3D %" PRIu32 riscv_wgchecker_translate(uint64_t addr, int flags, int wid, const char *r= es) "addr =3D 0x%016" PRIx64 ", flags =3D 0x%x, wid =3D %d: %s" +riscv_wgchecker_iommu_notify_all(void) "notifying UNMAP for all" --=20 2.43.0