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Tue, 21 Oct 2025 09:14:03 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Daniel Henrique Barboza , Richard Henderson , Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Zhao Liu , Peter Xu , David Hildenbrand , Michael Rolnik , Helge Deller , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Yoshinori Sato , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu Subject: [PATCH v3 13/18] hw/misc: riscv_worldguard: Add API to enable WG extension of CPU Date: Wed, 22 Oct 2025 00:13:19 +0800 Message-ID: <20251021161325.585278-6-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251021155548.584543-1-jim.shu@sifive.com> References: <20251021155548.584543-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=jim.shu@sifive.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1761063366306158500 Content-Type: text/plain; charset="utf-8" riscv_worldguard_apply_cpu() could enable WG CPU extension and set WG callback to CPUs. It is used by machine code after realizing global WG device. Signed-off-by: Jim Shu --- hw/misc/riscv_worldguard.c | 92 ++++++++++++++++++++++++++++++ include/hw/misc/riscv_worldguard.h | 1 + 2 files changed, 93 insertions(+) diff --git a/hw/misc/riscv_worldguard.c b/hw/misc/riscv_worldguard.c index 588c16ae9a..73fa8190cd 100644 --- a/hw/misc/riscv_worldguard.c +++ b/hw/misc/riscv_worldguard.c @@ -92,6 +92,98 @@ uint32_t mem_attrs_to_wid(MemTxAttrs attrs) } } =20 +static void riscv_cpu_wg_reset(CPURISCVState *env) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + uint32_t mlwid, slwid, mwiddeleg; + uint32_t trustedwid; + + if (!riscv_cpu_cfg(env)->ext_smwg) { + return; + } + + if (worldguard_config =3D=3D NULL) { + /* + * Note: This reset is dummy now and WG CSRs will be reset again + * after worldguard_config is realized. + */ + return; + } + + trustedwid =3D worldguard_config->trustedwid; + if (trustedwid =3D=3D NO_TRUSTEDWID) { + trustedwid =3D worldguard_config->nworlds - 1; + } + + /* Reset mlwid, slwid, mwiddeleg CSRs */ + if (worldguard_config->hw_bypass) { + /* HW bypass mode */ + mlwid =3D trustedwid; + } else { + mlwid =3D 0; + } + slwid =3D 0; + mwiddeleg =3D 0; + + env->mlwid =3D mlwid; + if (riscv_cpu_cfg(env)->ext_sswg) { + env->slwid =3D slwid; + env->mwiddeleg =3D mwiddeleg; + } + + /* Check mwid, mwidlist config */ + if (worldguard_config !=3D NULL) { + uint32_t valid_widlist =3D MAKE_64BIT_MASK(0, worldguard_config->n= worlds); + + /* CPU use default mwid / mwidlist config if not set */ + if (cpu->cfg.mwidlist =3D=3D UINT32_MAX) { + /* mwidlist contains all WIDs */ + cpu->cfg.mwidlist =3D valid_widlist; + } + if (cpu->cfg.mwid =3D=3D UINT32_MAX) { + cpu->cfg.mwid =3D trustedwid; + } + + /* Check if mwid/mwidlist HW config is valid in NWorld. */ + g_assert((cpu->cfg.mwidlist & ~valid_widlist) =3D=3D 0); + g_assert(cpu->cfg.mwid < worldguard_config->nworlds); + } +} + +/* + * riscv_worldguard_apply_cpu - Enable WG extension of CPU + * + * Note: This API should be used after global WG device is created + * (riscv_worldguard_realize()). + */ +void riscv_worldguard_apply_cpu(uint32_t hartid) +{ + CPUState *cpu =3D cpu_by_arch_id(hartid); + RISCVCPU *rcpu =3D RISCV_CPU(cpu); + CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; + + /* WG global config should exist */ + g_assert(worldguard_config); + + /* If the CPU with this hartid doesn't exist */ + if (env =3D=3D NULL) { + return; + } + + rcpu->cfg.ext_smwg =3D true; + if (riscv_has_ext(env, RVS) && riscv_has_ext(env, RVU)) { + rcpu->cfg.ext_sswg =3D true; + } + + /* Set machine specific WorldGuard callback */ + env->wg_reset =3D riscv_cpu_wg_reset; + env->wid_to_mem_attrs =3D wid_to_mem_attrs; + + /* Reset WG CSRs in CPU */ + env->wg_reset(env); +} + bool could_access_wgblocks(MemTxAttrs attrs, const char *wgblock) { uint32_t wid =3D mem_attrs_to_wid(attrs); diff --git a/include/hw/misc/riscv_worldguard.h b/include/hw/misc/riscv_wor= ldguard.h index bb276e59b8..fb08c92f46 100644 --- a/include/hw/misc/riscv_worldguard.h +++ b/include/hw/misc/riscv_worldguard.h @@ -48,6 +48,7 @@ extern struct RISCVWorldGuardState *worldguard_config; =20 DeviceState *riscv_worldguard_create(uint32_t nworlds, uint32_t trustedwid, bool hw_bypass, bool tz_compat); +void riscv_worldguard_apply_cpu(uint32_t hartid); =20 void wid_to_mem_attrs(MemTxAttrs *attrs, uint32_t wid); uint32_t mem_attrs_to_wid(MemTxAttrs attrs); --=20 2.43.0