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Tue, 21 Oct 2025 09:13:51 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Daniel Henrique Barboza , Richard Henderson , Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Zhao Liu , Peter Xu , David Hildenbrand , Michael Rolnik , Helge Deller , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Yoshinori Sato , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu Subject: [PATCH v3 11/18] target/riscv: Add WID to MemTxAttrs of CPU memory transactions Date: Wed, 22 Oct 2025 00:13:17 +0800 Message-ID: <20251021161325.585278-4-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251021155548.584543-1-jim.shu@sifive.com> References: <20251021155548.584543-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=jim.shu@sifive.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1761063280096154100 Content-Type: text/plain; charset="utf-8" When a RISC-V HART has WG extension, their memory transactions will contain WID. Support MemTxAttrs in RISC-V target and add WID inside if a HART has WG extension. Signed-off-by: Jim Shu --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 51 ++++++++++++++++++++++++++++++++++++--- 3 files changed, 50 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 22b4070476..32a9f8a6a4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2678,7 +2678,7 @@ static int64_t riscv_get_arch_id(CPUState *cs) =20 static const struct SysemuCPUOps riscv_sysemu_ops =3D { .has_work =3D riscv_cpu_has_work, - .get_phys_page_debug =3D riscv_cpu_get_phys_page_debug, + .get_phys_page_attrs_debug =3D riscv_cpu_get_phys_page_attrs_debug, .write_elf64_note =3D riscv_cpu_write_elf64_note, .write_elf32_note =3D riscv_cpu_write_elf32_note, .legacy_vmsd =3D &vmstate_riscv_cpu, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e99aa11140..e2436fdcd8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -625,6 +625,7 @@ int riscv_env_mmu_index(CPURISCVState *env, bool ifetch= ); bool cpu_get_fcfien(CPURISCVState *env); bool cpu_get_bcfien(CPURISCVState *env); bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt); +hwaddr riscv_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemT= xAttrs *attrs); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t reta= ddr); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d2be660d58..64e5557f0a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -136,6 +136,34 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env= , bool virt) } =20 #ifndef CONFIG_USER_ONLY +static uint32_t riscv_cpu_wg_get_wid(CPURISCVState *env, int mode) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + bool virt =3D env->virt_enabled; + + if (mode =3D=3D PRV_M) { + return cpu->cfg.mwid; + } else if (mode =3D=3D PRV_S) { + if (!virt || !env->mwiddeleg) { + /* HS-mode, S-mode w/o RVH, or VS-mode but mwiddeleg =3D 0 */ + return env->mlwid; + } else { + /* VS-mode */ + return env->slwid; + } + } else if (mode =3D=3D PRV_U) { + if (!riscv_has_ext(env, RVS) || !env->mwiddeleg) { + /* M/U mode CPU or mwiddeleg =3D 0 */ + return env->mlwid; + } else { + return env->slwid; + } + } + + return cpu->cfg.mwid; +} + void riscv_cpu_set_wg_mwid(CPURISCVState *env, uint32_t mwid) { CPUState *cs =3D env_cpu(env); @@ -1675,13 +1703,22 @@ static void raise_mmu_exception(CPURISCVState *env,= target_ulong address, env->two_stage_indirect_lookup =3D two_stage_indirect; } =20 -hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr riscv_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTx= Attrs *attrs) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; hwaddr phys_addr; int prot; int mmu_idx =3D riscv_env_mmu_index(&cpu->env, false); + int mode =3D mmuidx_priv(mmu_idx); + uint32_t wid; + + if (riscv_cpu_cfg(env)->ext_smwg && env->wid_to_mem_attrs) { + wid =3D riscv_cpu_wg_get_wid(env, mode); + env->wid_to_mem_attrs(attrs, wid); + } else { + *attrs =3D MEMTXATTRS_UNSPECIFIED; + } =20 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_id= x, true, env->virt_enabled, true, false)) { @@ -1793,12 +1830,20 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address= , int size, int mode =3D mmuidx_priv(mmu_idx); /* default TLB page size */ hwaddr tlb_size =3D TARGET_PAGE_SIZE; + uint32_t wid; + MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; =20 env->guest_phys_fault_addr =3D 0; =20 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); =20 + if (riscv_cpu_cfg(env)->ext_smwg && env->wid_to_mem_attrs) { + mode =3D mmuidx_priv(mmu_idx); + wid =3D riscv_cpu_wg_get_wid(env, mode); + env->wid_to_mem_attrs(&attrs, wid); + } + pmu_tlb_fill_incr_ctr(cpu, access_type); if (two_stage_lookup) { /* Two stage lookup */ @@ -1891,8 +1936,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, } =20 if (ret =3D=3D TRANSLATE_SUCCESS) { - tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), - prot, access_type, mmu_idx, tlb_size); + tlb_set_page_with_attrs(cs, address & ~(tlb_size - 1), pa & ~(tlb_= size - 1), + attrs, prot, access_type, mmu_idx, tlb_siz= e); return true; } else if (probe) { return false; --=20 2.43.0