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Tue, 21 Oct 2025 09:13:45 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Daniel Henrique Barboza , Richard Henderson , Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Zhao Liu , Peter Xu , David Hildenbrand , Michael Rolnik , Helge Deller , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Yoshinori Sato , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu Subject: [PATCH v3 10/18] target/riscv: Implement WorldGuard CSRs Date: Wed, 22 Oct 2025 00:13:16 +0800 Message-ID: <20251021161325.585278-3-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251021155548.584543-1-jim.shu@sifive.com> References: <20251021155548.584543-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=jim.shu@sifive.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1761063463007158500 Content-Type: text/plain; charset="utf-8" The WG v0.4 specification adds 3 CSRs to configure S/U/HS/VS-mode WIDs of CPUs in the higher privileged modes. The Smwg extension at least requires a RISC-V HART to have M/U-mode, and the Sswg/Smwgd extension at least requires a RISC-V HART to have M/S/U-mode. Signed-off-by: Jim Shu Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 4 ++ target/riscv/cpu.h | 5 +++ target/riscv/csr.c | 107 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 116 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 03946439f2..22b4070476 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -795,6 +795,10 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTyp= e type) env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, false); } =20 + if (riscv_cpu_cfg(env)->ext_smwg && env->wg_reset) { + env->wg_reset(env); + } + if (kvm_enabled()) { kvm_riscv_reset_vcpu(cpu); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8e18b5f13e..e99aa11140 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -514,6 +514,11 @@ struct CPUArchState { uint64_t rnmi_irqvec; uint64_t rnmi_excpvec; =20 + /* RISC-V WorldGuard */ + target_ulong mlwid; + target_ulong slwid; + target_ulong mwiddeleg; + /* machine specific WorldGuard callback */ void (*wg_reset)(CPURISCVState *env); void (*wid_to_mem_attrs)(MemTxAttrs *attrs, uint32_t wid); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5c91658c3d..be62a30953 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5470,6 +5470,109 @@ static RISCVException write_mnstatus(CPURISCVState = *env, int csrno, return RISCV_EXCP_NONE; } =20 +/* RISC-V Worldguard */ +static RISCVException worldguard_umode(CPURISCVState *env, int csrno) +{ + if (!riscv_cpu_cfg(env)->ext_smwg) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return umode(env, csrno); +} + +static RISCVException worldguard_sumode(CPURISCVState *env, int csrno) +{ + RISCVException ret; + + if (!riscv_cpu_cfg(env)->ext_sswg) { + return RISCV_EXCP_ILLEGAL_INST; + } + + ret =3D smode(env, csrno); + + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + return umode(env, csrno); +} + +static RISCVException rmw_mlwid(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + target_ulong new_mlwid =3D (env->mlwid & ~wr_mask) | (new_val & wr_mas= k); + + if (ret_val) { + *ret_val =3D env->mlwid; + } + + g_assert(cpu->cfg.mwidlist); + if (!(BIT(new_mlwid) & cpu->cfg.mwidlist)) { + /* Set WID to lowest legal value if writing illegal value (WARL) */ + new_mlwid =3D find_first_bit((unsigned long *)&cpu->cfg.mwidlist, = 32); + } + + if (env->mlwid !=3D new_mlwid) { + env->mlwid =3D new_mlwid; + tlb_flush(cs); + } + + return RISCV_EXCP_NONE; +} + +static RISCVException rmw_slwid(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + target_ulong new_slwid =3D (env->slwid & ~wr_mask) | (new_val & wr_mas= k); + + if (!env->mwiddeleg) { + /* + * When mwiddeleg CSR is zero, access to slwid raises an illegal + * instruction exception. + */ + return RISCV_EXCP_ILLEGAL_INST; + } + + if (ret_val) { + *ret_val =3D env->slwid; + } + + if (!(BIT(new_slwid) & env->mwiddeleg)) { + /* Set WID to lowest legal value if writing illegal value (WARL) */ + new_slwid =3D find_first_bit( + (unsigned long *)&env->mwiddeleg, TARGET_LONG_BITS); + } + + if (env->slwid !=3D new_slwid) { + env->slwid =3D new_slwid; + tlb_flush(env_cpu(env)); + } + + return RISCV_EXCP_NONE; +} + +static RISCVException rmw_mwiddeleg(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_= mask) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (ret_val) { + *ret_val =3D env->mwiddeleg; + } + + env->mwiddeleg =3D (env->mwiddeleg & ~wr_mask) | (new_val & wr_mask); + + /* Core wgMarker can only have WID value in mwidlist. */ + env->mwiddeleg &=3D cpu->cfg.mwidlist; + + return RISCV_EXCP_NONE; +} #endif =20 /* Crypto Extension */ @@ -6667,5 +6770,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_SCOUNTOVF] =3D { "scountovf", sscofpmf, read_scountovf, .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 + /* RISC-V WorldGuard */ + [CSR_MLWID] =3D { "mlwid", worldguard_umode, NULL, NULL, rmw_= mlwid }, + [CSR_SLWID] =3D { "slwid", worldguard_sumode, NULL, NULL, rmw_= slwid }, + [CSR_MWIDDELEG] =3D { "mwiddeleg", worldguard_sumode, NULL, NULL, rmw_= mwiddeleg }, #endif /* !CONFIG_USER_ONLY */ }; --=20 2.43.0