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Tue, 21 Oct 2025 08:56:38 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Daniel Henrique Barboza , Richard Henderson , Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Zhao Liu , Peter Xu , David Hildenbrand , Michael Rolnik , Helge Deller , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Yoshinori Sato , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu Subject: [PATCH v3 07/18] target/riscv: Add hard-coded CPU state of WG extension Date: Tue, 21 Oct 2025 23:55:37 +0800 Message-ID: <20251021155548.584543-8-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251021155548.584543-1-jim.shu@sifive.com> References: <20251021155548.584543-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=jim.shu@sifive.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1761062304473154100 Content-Type: text/plain; charset="utf-8" Add hard-coded state of WG extension. 'mwid' is the M-mode WID of CPU. 'mwidlist' is the list of allowed WID value of 'mlwid' CSR. These CPU states can be set by CPU option, or can be set by machine code via newly added APIs. If we want different WG configs of CPUs, we should set it by machine code. Signed-off-by: Jim Shu --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_cfg_fields.h.inc | 3 +++ target/riscv/cpu_helper.c | 18 ++++++++++++++++++ 3 files changed, 23 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4c13012442..b121e3bca9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -654,6 +654,8 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, = uint32_t priv, void *rmw_fn_arg); =20 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bi= t); +void riscv_cpu_set_wg_mwid(CPURISCVState *env, uint32_t mwid); +void riscv_cpu_set_wg_mwidlist(CPURISCVState *env, uint32_t mwidlist); #endif /* !CONFIG_USER_ONLY */ =20 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool vir= t_en); diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 44387a8db3..ba309d9c32 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -172,5 +172,8 @@ TYPED_FIELD(uint8_t, pmp_regions, 0) =20 TYPED_FIELD(int8_t, max_satp_mode, -1) =20 +TYPED_FIELD(uint32_t, mwid, 0) +TYPED_FIELD(uint32_t, mwidlist, 0) + #undef BOOL_FIELD #undef TYPED_FIELD diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 63acd70543..d2be660d58 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -135,6 +135,24 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env= , bool virt) #endif } =20 +#ifndef CONFIG_USER_ONLY +void riscv_cpu_set_wg_mwid(CPURISCVState *env, uint32_t mwid) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + cpu->cfg.mwid =3D mwid; +} + +void riscv_cpu_set_wg_mwidlist(CPURISCVState *env, uint32_t mwidlist) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + cpu->cfg.mwidlist =3D mwidlist; +} +#endif /* CONFIG_USER_ONLY */ + RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) { #ifndef CONFIG_USER_ONLY --=20 2.43.0