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Tue, 21 Oct 2025 08:56:21 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Daniel Henrique Barboza , Richard Henderson , Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Zhao Liu , Peter Xu , David Hildenbrand , Michael Rolnik , Helge Deller , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Yoshinori Sato , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu Subject: [PATCH v3 04/18] exec: Add RISC-V WorldGuard WID to MemTxAttrs Date: Tue, 21 Oct 2025 23:55:34 +0800 Message-ID: <20251021155548.584543-5-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251021155548.584543-1-jim.shu@sifive.com> References: <20251021155548.584543-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=jim.shu@sifive.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1761062366728158500 Content-Type: text/plain; charset="utf-8" RISC-V WorldGuard will add 5-bit world_id (WID) to the each memory transaction on the bus. The wgChecker in front of RAM or peripherals MMIO could do the access control based on the WID. It is similar to ARM TrustZone NS bit, but the WID is 5-bit. The common implementation of WID is AXI4 AxUSER signal. Since the '_reserved*' fields in MemTxAttr are for padding the struct to be 8-byte [1], we change the reserved fields from 3 to 2 bytes when adding 5-bit world_id field. [1] Commit 5014e33b1e00d330f13df33c09a3932ac88f8d94 Link: https://lore.kernel.org/r/20250121151322.171832-2-zhao1.liu@intel= .com Signed-off-by: Jim Shu --- include/exec/memattrs.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 52ee955249..6bde90d482 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -57,6 +57,11 @@ typedef struct MemTxAttrs { /* PCI - IOMMU operations, see PCIAddressType */ unsigned int address_type:1; =20 + /* + * RISC-V WorldGuard: the 5-bit WID field of memory access. + */ + unsigned int world_id:5; + /* * Bus masters which don't specify any attributes will get this * (via the MEMTXATTRS_UNSPECIFIED constant), so that we can @@ -66,8 +71,7 @@ typedef struct MemTxAttrs { */ bool unspecified; =20 - uint8_t _reserved1; - uint16_t _reserved2; + uint16_t _reserved1; } MemTxAttrs; =20 QEMU_BUILD_BUG_ON(sizeof(MemTxAttrs) > 8); --=20 2.43.0