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Tsirkin" , Paolo Bonzini Cc: Gert Wollny , qemu-devel@nongnu.org, Gurchetan Singh , Alyssa Ross , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Alex Deucher , Stefano Stabellini , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xenia Ragiadakou , Honglei Huang , Julia Zhang , Chen Jiqian , Rob Clark , Yiwei Zhang , Sergio Lopez Pascual Subject: [PATCH v14 04/10] virtio-gpu: Support asynchronous fencing Date: Tue, 21 Oct 2025 02:39:43 +0300 Message-ID: <20251020233949.506088-5-dmitry.osipenko@collabora.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251020233949.506088-1-dmitry.osipenko@collabora.com> References: <20251020233949.506088-1-dmitry.osipenko@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=136.143.188.15; envelope-from=dmitry.osipenko@collabora.com; helo=sender4-op-o15.zoho.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity dmitry.osipenko@collabora.com) X-ZM-MESSAGEID: 1761003828592154100 Support asynchronous fencing feature of virglrenderer. It allows Qemu to handle fence as soon as it's signalled instead of periodically polling the fence status. This feature is required for enabling DRM context support in Qemu because legacy fencing mode isn't supported for DRM contexts in virglrenderer. Reviewed-by: Akihiko Odaki Acked-by: Michael S. Tsirkin Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Dmitry Osipenko --- hw/display/virtio-gpu-gl.c | 5 ++ hw/display/virtio-gpu-virgl.c | 130 +++++++++++++++++++++++++++++++++ include/hw/virtio/virtio-gpu.h | 11 +++ meson.build | 2 + 4 files changed, 148 insertions(+) diff --git a/hw/display/virtio-gpu-gl.c b/hw/display/virtio-gpu-gl.c index c06a078fb36a..1468c6ed1467 100644 --- a/hw/display/virtio-gpu-gl.c +++ b/hw/display/virtio-gpu-gl.c @@ -169,6 +169,11 @@ static void virtio_gpu_gl_device_unrealize(DeviceState= *qdev) if (gl->renderer_state >=3D RS_INITED) { #if VIRGL_VERSION_MAJOR >=3D 1 qemu_bh_delete(gl->cmdq_resume_bh); + + if (gl->async_fence_bh) { + virtio_gpu_virgl_reset_async_fences(g); + qemu_bh_delete(gl->async_fence_bh); + } #endif if (virtio_gpu_stats_enabled(g->parent_obj.conf)) { timer_free(gl->print_stats); diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c index cd8b367f6fa6..0320d6deca76 100644 --- a/hw/display/virtio-gpu-virgl.c +++ b/hw/display/virtio-gpu-virgl.c @@ -24,6 +24,23 @@ =20 #include =20 +/* + * VIRGL_CHECK_VERSION available since libvirglrenderer 1.0.1 and was fixed + * in 1.1.0. Undefine bugged version of the macro and provide our own. + */ +#if defined(VIRGL_CHECK_VERSION) && \ + VIRGL_VERSION_MAJOR =3D=3D 1 && VIRGL_VERSION_MINOR < 1 +#undef VIRGL_CHECK_VERSION +#endif + +#ifndef VIRGL_CHECK_VERSION +#define VIRGL_CHECK_VERSION(major, minor, micro) \ + (VIRGL_VERSION_MAJOR > (major) || \ + VIRGL_VERSION_MAJOR =3D=3D (major) && VIRGL_VERSION_MINOR > (minor) |= | \ + VIRGL_VERSION_MAJOR =3D=3D (major) && VIRGL_VERSION_MINOR =3D=3D (min= or) && \ + VIRGL_VERSION_MICRO >=3D (micro)) +#endif + struct virtio_gpu_virgl_resource { struct virtio_gpu_simple_resource base; MemoryRegion *mr; @@ -1051,6 +1068,106 @@ static void virgl_write_context_fence(void *opaque,= uint32_t ctx_id, } #endif =20 +void virtio_gpu_virgl_reset_async_fences(VirtIOGPU *g) +{ + struct virtio_gpu_virgl_context_fence *f; + VirtIOGPUGL *gl =3D VIRTIO_GPU_GL(g); + + while (!QSLIST_EMPTY(&gl->async_fenceq)) { + f =3D QSLIST_FIRST(&gl->async_fenceq); + + QSLIST_REMOVE_HEAD(&gl->async_fenceq, next); + + g_free(f); + } +} + +#if VIRGL_CHECK_VERSION(1, 1, 2) +static void virtio_gpu_virgl_async_fence_bh(void *opaque) +{ + QSLIST_HEAD(, virtio_gpu_virgl_context_fence) async_fenceq; + struct virtio_gpu_ctrl_command *cmd, *tmp; + struct virtio_gpu_virgl_context_fence *f; + VirtIOGPU *g =3D opaque; + VirtIOGPUGL *gl =3D VIRTIO_GPU_GL(g); + + if (gl->renderer_state !=3D RS_INITED) { + return; + } + + QSLIST_MOVE_ATOMIC(&async_fenceq, &gl->async_fenceq); + + while (!QSLIST_EMPTY(&async_fenceq)) { + f =3D QSLIST_FIRST(&async_fenceq); + + QSLIST_REMOVE_HEAD(&async_fenceq, next); + + QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) { + /* + * the guest can end up emitting fences out of order + * so we should check all fenced cmds not just the first one. + */ + if (cmd->cmd_hdr.fence_id > f->fence_id) { + continue; + } + if (cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_INFO_RING_IDX) { + if (cmd->cmd_hdr.ring_idx !=3D f->ring_idx) { + continue; + } + if (cmd->cmd_hdr.ctx_id !=3D f->ctx_id) { + continue; + } + } else if (f->ring_idx >=3D 0) { + /* ctx0 GL-query fences don't have ring info */ + continue; + } + virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NOD= ATA); + QTAILQ_REMOVE(&g->fenceq, cmd, next); + g_free(cmd); + } + + trace_virtio_gpu_fence_resp(f->fence_id); + g_free(f); + g->inflight--; + if (virtio_gpu_stats_enabled(g->parent_obj.conf)) { + trace_virtio_gpu_dec_inflight_fences(g->inflight); + } + } +} + +static void +virtio_gpu_virgl_push_async_fence(VirtIOGPU *g, uint32_t ctx_id, + int64_t ring_idx, uint64_t fence_id) +{ + struct virtio_gpu_virgl_context_fence *f; + VirtIOGPUGL *gl =3D VIRTIO_GPU_GL(g); + + f =3D g_new(struct virtio_gpu_virgl_context_fence, 1); + f->ctx_id =3D ctx_id; + f->ring_idx =3D ring_idx; + f->fence_id =3D fence_id; + + QSLIST_INSERT_HEAD_ATOMIC(&gl->async_fenceq, f, next); + + qemu_bh_schedule(gl->async_fence_bh); +} + +static void virgl_write_async_fence(void *opaque, uint32_t fence) +{ + VirtIOGPU *g =3D opaque; + + virtio_gpu_virgl_push_async_fence(g, 0, -1, fence); +} + +static void virgl_write_async_context_fence(void *opaque, uint32_t ctx_id, + uint32_t ring_idx, uint64_t fe= nce) +{ + VirtIOGPU *g =3D opaque; + + virtio_gpu_virgl_push_async_fence(g, ctx_id, ring_idx, fence); +} +#endif + static virgl_renderer_gl_context virgl_create_context(void *opaque, int scanout_idx, struct virgl_renderer_gl_ctx_param *params) @@ -1150,6 +1267,8 @@ void virtio_gpu_virgl_reset_scanout(VirtIOGPU *g) void virtio_gpu_virgl_reset(VirtIOGPU *g) { virgl_renderer_reset(); + + virtio_gpu_virgl_reset_async_fences(g); } =20 int virtio_gpu_virgl_init(VirtIOGPU *g) @@ -1162,6 +1281,12 @@ int virtio_gpu_virgl_init(VirtIOGPU *g) if (qemu_egl_display) { virtio_gpu_3d_cbs.version =3D 4; virtio_gpu_3d_cbs.get_egl_display =3D virgl_get_egl_display; +#if VIRGL_CHECK_VERSION(1, 1, 2) + virtio_gpu_3d_cbs.write_fence =3D virgl_write_async_fence; + virtio_gpu_3d_cbs.write_context_fence =3D virgl_write_async_contex= t_fence; + flags |=3D VIRGL_RENDERER_ASYNC_FENCE_CB; + flags |=3D VIRGL_RENDERER_THREAD_SYNC; +#endif } #endif #ifdef VIRGL_RENDERER_D3D11_SHARE_TEXTURE @@ -1195,6 +1320,11 @@ int virtio_gpu_virgl_init(VirtIOGPU *g) gl->cmdq_resume_bh =3D aio_bh_new(qemu_get_aio_context(), virtio_gpu_virgl_resume_cmdq_bh, g); +#if VIRGL_CHECK_VERSION(1, 1, 2) + gl->async_fence_bh =3D aio_bh_new(qemu_get_aio_context(), + virtio_gpu_virgl_async_fence_bh, + g); +#endif #endif =20 return 0; diff --git a/include/hw/virtio/virtio-gpu.h b/include/hw/virtio/virtio-gpu.h index 9f16f89a36d2..e15c16aa5945 100644 --- a/include/hw/virtio/virtio-gpu.h +++ b/include/hw/virtio/virtio-gpu.h @@ -233,6 +233,13 @@ struct VirtIOGPUClass { Error **errp); }; =20 +struct virtio_gpu_virgl_context_fence { + uint32_t ctx_id; + int64_t ring_idx; + uint64_t fence_id; + QSLIST_ENTRY(virtio_gpu_virgl_context_fence) next; +}; + /* VirtIOGPUGL renderer states */ typedef enum { RS_START, /* starting state */ @@ -250,6 +257,9 @@ struct VirtIOGPUGL { QEMUTimer *print_stats; =20 QEMUBH *cmdq_resume_bh; + + QEMUBH *async_fence_bh; + QSLIST_HEAD(, virtio_gpu_virgl_context_fence) async_fenceq; }; =20 struct VhostUserGPU { @@ -379,5 +389,6 @@ void virtio_gpu_virgl_reset_scanout(VirtIOGPU *g); void virtio_gpu_virgl_reset(VirtIOGPU *g); int virtio_gpu_virgl_init(VirtIOGPU *g); GArray *virtio_gpu_virgl_get_capsets(VirtIOGPU *g); +void virtio_gpu_virgl_reset_async_fences(VirtIOGPU *g); =20 #endif diff --git a/meson.build b/meson.build index e96c28da09b6..e3d48150483e 100644 --- a/meson.build +++ b/meson.build @@ -2597,6 +2597,8 @@ config_host_data.set('CONFIG_VNC_JPEG', jpeg.found()) config_host_data.set('CONFIG_VNC_SASL', sasl.found()) if virgl.found() config_host_data.set('VIRGL_VERSION_MAJOR', virgl.version().split('.')[0= ]) + config_host_data.set('VIRGL_VERSION_MINOR', virgl.version().split('.')[1= ]) + config_host_data.set('VIRGL_VERSION_MICRO', virgl.version().split('.')[2= ]) endif config_host_data.set('CONFIG_VIRTFS', have_virtfs) config_host_data.set('CONFIG_VTE', vte.found()) --=20 2.51.0