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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-427ea5b3d4csm14321834f8f.19.2025.10.20.03.39.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 20 Oct 2025 03:39:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1760956763; x=1761561563; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W8V6t72s6m9O+rQuQWdHSJVeQu4En69ObrbMa64lrwE=; b=lWKyBFS8fQhE2glG10K/BI9LJ+Uzk0lRbzDkzQ3d52HleGTfDRqHozcbahkv58edm2 x2enwj5HJDAmZRhQetxzpLBDbdNPNhc1xXHqfS29w5/Hob543ZxnHupcdyb89OLItTuq R4eahJrNmvLIqaCbX03kixMudDqdwDacpCs9S0fu2erBLQU7ItFadQa7opyGPTaBLqjU ik02UF1BKt1d2jP8YHgfxHeM+lriLhQOceFJ9acdvzLmfsnhtkizCyXkZg0anrrUAZF3 oaJcYD3+zPbZBJMq2j5rCYaj8PH5AKDDDsjUJNQamKk7m9JdR6rxkFGDu99ASxqiI8u/ KQkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760956763; x=1761561563; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W8V6t72s6m9O+rQuQWdHSJVeQu4En69ObrbMa64lrwE=; b=wsQZ2u9R6eDWcrSY9qfsL2pdibIrT7QoRvRTM91V/O/xZMpRr1cI9rcUDWA/KHItjN Vgbn0/7m/IhYNP5TY2TtyUHKsn9+r05bIizcj1tOi+nE1rrOMRM04cwV8pqm+7aefLTR Pltjv9/Q1jLk7tsvIq9AheaEAhC4+z8M1RuS0+kibJXazLaBDbhdQgp/IPGy7oO7SwSZ qkDDuK0I8KIf2OpTo4eHKQEdz6Ds2AY+dwS5jtioB3tDOY/2pEuJhFlIOFVapnrZbbfk 6EPzRlGLr8RG2KvFWNoVrS9MexPGFYslUlBcL5WTZ+JiIoS/NoOHqL/pm7fegMH95F7Q umLA== X-Gm-Message-State: AOJu0YyjfdBekas7DwC1HWkvJeIY2pfzARIdMoaIs7/qY8NiTOXw7ZBT T9ow+GkZIr6lQgcn/et32mlY7bvHqh5wYbtbJ/AR9MMTKFsBmntpxs9iqnYbkRCiZTMZhnOjqCh QD5wLasE= X-Gm-Gg: ASbGncsd/zqdJ6T6t6VszVuSGgbTMoIL9K8DeUxGnwwRPB3zEBx0Y6LoA/ke0T4EXUd Dhg8b1Qx1Urc/ITTQAaMX2n6BDe92WmHuHNdSFZaMLiNIm6gX9cyiCxse5RxNMDUvBc36I+SFsz pPotBxX0Hhgm8BijKzvzCOASe6ulwoI/LO1sLyVUNR2Wfg1AdQbq6mOkwmFLwMPdHW2SMeqqT0k V5WlStsAWRWYRLQynvTvpUYVc8oB/ZcIJuf74GW4O5D9DoR6edQmWBOqTb/MXfdkcTWMTsbdpcZ QOBD3Wl6Ss4sWfquutNb/myM3VIRjoo5/aweCI0+2bLTAlzPtAIKVSsiLdbL8omDsCC2i+uYJvb 5Ij+jetd5tP21aULsfUNJeh9TO+4wRb2UFygMYBJv8S6uP44HYKjV6GRlqG7e3bEYbl+F0Cr6RS 1LQg4H3cywyYN+zjDb/qUEEkhEPDsA4llhCBl1SfKJeXT1ywyOow== X-Google-Smtp-Source: AGHT+IGtRhefuOKzzFl9+PdkwonrQEzKn77Y5Nm+6QawC0+EavDuvCFIl4z0qnwNmWAUflc1D40aEw== X-Received: by 2002:a5d:5f82:0:b0:425:8133:8a89 with SMTP id ffacd0b85a97d-42704d75729mr9332637f8f.22.1760956763315; Mon, 20 Oct 2025 03:39:23 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Nicholas Piggin , qemu-ppc@nongnu.org, kvm@vger.kernel.org, Chinmay Rath , Harsh Prateek Bora , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 13/18] hw/ppc/spapr: Remove SpaprMachineClass::phb_placement callback Date: Mon, 20 Oct 2025 12:38:09 +0200 Message-ID: <20251020103815.78415-14-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251020103815.78415-1-philmd@linaro.org> References: <20251020103815.78415-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760956912950158500 The SpaprMachineClass::phb_placement callback was only used by the pseries-4.0 machine, which got removed. Remove it as now unused, directly calling spapr_phb_placement(). Move spapr_phb_placement() definition to avoid forward declaration. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/ppc/spapr.h | 5 -- hw/ppc/spapr.c | 114 ++++++++++++++++++++--------------------- 2 files changed, 55 insertions(+), 64 deletions(-) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 4c1acd7af5e..82f556f97e1 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -149,11 +149,6 @@ struct SpaprMachineClass { bool pre_5_1_assoc_refpoints; bool pre_5_2_numa_associativity; bool pre_6_2_numa_affinity; - - bool (*phb_placement)(SpaprMachineState *spapr, uint32_t index, - uint64_t *buid, hwaddr *pio, - hwaddr *mmio32, hwaddr *mmio64, - unsigned n_dma, uint32_t *liobns, Error **errp); SpaprResizeHpt resize_hpt_default; SpaprCapabilities default_caps; SpaprIrq *irq; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e861a2e7466..200e68b8bc2 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4067,12 +4067,62 @@ int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachi= neState *spapr, return 0; } =20 +static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, + uint64_t *buid, hwaddr *pio, + hwaddr *mmio32, hwaddr *mmio64, + unsigned n_dma, uint32_t *liobns, Error **= errp) +{ + /* + * New-style PHB window placement. + * + * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window + * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO + * windows. + * + * Some guest kernels can't work with MMIO windows above 1<<46 + * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB + * + * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each + * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the + * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the + * 1TiB 64-bit MMIO windows for each PHB. + */ + const uint64_t base_buid =3D 0x800000020000000ULL; + int i; + + /* Sanity check natural alignments */ + QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) !=3D 0); + QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) !=3D 0); + QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE= ) !=3D 0); + QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != =3D 0); + /* Sanity check bounds */ + QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > + SPAPR_PCI_MEM32_WIN_SIZE); + QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > + SPAPR_PCI_MEM64_WIN_SIZE); + + if (index >=3D SPAPR_MAX_PHBS) { + error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", + SPAPR_MAX_PHBS - 1); + return false; + } + + *buid =3D base_buid + index; + for (i =3D 0; i < n_dma; ++i) { + liobns[i] =3D SPAPR_PCI_LIOBN(index, i); + } + + *pio =3D SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; + *mmio32 =3D SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; + *mmio64 =3D SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; + return true; +} + static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *d= ev, Error **errp) { SpaprMachineState *spapr =3D SPAPR_MACHINE(OBJECT(hotplug_dev)); SpaprPhbState *sphb =3D SPAPR_PCI_HOST_BRIDGE(dev); - SpaprMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); const unsigned windows_supported =3D spapr_phb_windows_supported(sphb); SpaprDrc *drc; =20 @@ -4091,12 +4141,10 @@ static bool spapr_phb_pre_plug(HotplugHandler *hotp= lug_dev, DeviceState *dev, * This will check that sphb->index doesn't exceed the maximum number = of * PHBs for the current machine type. */ - return - smc->phb_placement(spapr, sphb->index, - &sphb->buid, &sphb->io_win_addr, - &sphb->mem_win_addr, &sphb->mem64_win_addr, - windows_supported, sphb->dma_liobn, - errp); + return spapr_phb_placement(spapr, sphb->index, + &sphb->buid, &sphb->io_win_addr, + &sphb->mem_win_addr, &sphb->mem64_win_addr, + windows_supported, sphb->dma_liobn, errp); } =20 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) @@ -4344,57 +4392,6 @@ static const CPUArchIdList *spapr_possible_cpu_arch_= ids(MachineState *machine) return machine->possible_cpus; } =20 -static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, - uint64_t *buid, hwaddr *pio, - hwaddr *mmio32, hwaddr *mmio64, - unsigned n_dma, uint32_t *liobns, Error **= errp) -{ - /* - * New-style PHB window placement. - * - * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window - * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO - * windows. - * - * Some guest kernels can't work with MMIO windows above 1<<46 - * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB - * - * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each - * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the - * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the - * 1TiB 64-bit MMIO windows for each PHB. - */ - const uint64_t base_buid =3D 0x800000020000000ULL; - int i; - - /* Sanity check natural alignments */ - QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) !=3D 0); - QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) !=3D 0); - QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE= ) !=3D 0); - QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != =3D 0); - /* Sanity check bounds */ - QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > - SPAPR_PCI_MEM32_WIN_SIZE); - QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > - SPAPR_PCI_MEM64_WIN_SIZE); - - if (index >=3D SPAPR_MAX_PHBS) { - error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", - SPAPR_MAX_PHBS - 1); - return false; - } - - *buid =3D base_buid + index; - for (i =3D 0; i < n_dma; ++i) { - liobns[i] =3D SPAPR_PCI_LIOBN(index, i); - } - - *pio =3D SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; - *mmio32 =3D SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; - *mmio64 =3D SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; - return true; -} - static ICSState *spapr_ics_get(XICSFabric *dev, int irq) { SpaprMachineState *spapr =3D SPAPR_MACHINE(dev); @@ -4605,7 +4602,6 @@ static void spapr_machine_class_init(ObjectClass *oc,= const void *data) smc->resize_hpt_default =3D SPAPR_RESIZE_HPT_ENABLED; fwc->get_dev_path =3D spapr_get_fw_dev_path; nc->nmi_monitor_handler =3D spapr_nmi; - smc->phb_placement =3D spapr_phb_placement; vhc->cpu_in_nested =3D spapr_cpu_in_nested; vhc->deliver_hv_excp =3D spapr_exit_nested; vhc->hypercall =3D emulate_spapr_hypercall; --=20 2.51.0