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Tsirkin" , Eduardo Habkost , Zhao Liu , kvm@vger.kernel.org, Michael Tokarev , Cameron Esfahani , qemu-block@nongnu.org, Paolo Bonzini , qemu-trivial@nongnu.org, Laurent Vivier , Richard Henderson , Roman Bolshakov , Phil Dennis-Jordan , John Snow , Fabiano Rosas , Gerd Hoffmann , Sunil Muthuswamy , Marcelo Tosatti , Bernhard Beschow Subject: [PATCH v3 09/10] hw/intc/apic: Pass APICCommonState to apic_register_{read, write} Date: Sun, 19 Oct 2025 23:03:02 +0200 Message-ID: <20251019210303.104718-10-shentey@gmail.com> X-Mailer: git-send-email 2.51.1.dirty In-Reply-To: <20251019210303.104718-1-shentey@gmail.com> References: <20251019210303.104718-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=shentey@gmail.com; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1760907944102158500 Content-Type: text/plain; charset="utf-8" As per the previous patch, the APIC instance is already available in apic_msr_{read,write}, so it can be passed along. It turns out that the call to cpu_get_current_apic() is only required in apic_mem_{read,write}, so it has been moved there. Longer term, cpu_get_current_apic() could be removed entirely if apic_mem_{read,write} is tied to a CPU's local address space. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/apic.c | 35 ++++++++++++++++------------------- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/hw/intc/apic.c b/hw/intc/apic.c index ba0eda3921..077ef18686 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -769,17 +769,11 @@ static void apic_timer(void *opaque) apic_timer_update(s, s->next_time); } =20 -static int apic_register_read(int index, uint64_t *value) +static int apic_register_read(APICCommonState *s, int index, uint64_t *val= ue) { - APICCommonState *s; uint32_t val; int ret =3D 0; =20 - s =3D cpu_get_current_apic(); - if (!s) { - return -1; - } - switch(index) { case 0x02: /* id */ if (is_x2apic_mode(s)) { @@ -868,6 +862,7 @@ static int apic_register_read(int index, uint64_t *valu= e) =20 static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size) { + APICCommonState *s =3D cpu_get_current_apic(); uint64_t val; int index; =20 @@ -875,8 +870,12 @@ static uint64_t apic_mem_read(void *opaque, hwaddr add= r, unsigned size) return 0; } =20 + if (!s) { + return -1; + } + index =3D (addr >> 4) & 0xff; - apic_register_read(index, &val); + apic_register_read(s, index, &val); =20 return val; } @@ -891,7 +890,7 @@ int apic_msr_read(APICCommonState *s, int index, uint64= _t *val) return -1; } =20 - return apic_register_read(index, val); + return apic_register_read(s, index, val); } =20 static void apic_send_msi(MSIMessage *msi) @@ -919,15 +918,8 @@ static void apic_send_msi(MSIMessage *msi) apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); } =20 -static int apic_register_write(int index, uint64_t val) +static int apic_register_write(APICCommonState *s, int index, uint64_t val) { - APICCommonState *s; - - s =3D cpu_get_current_apic(); - if (!s) { - return -1; - } - trace_apic_register_write(index, val); =20 switch(index) { @@ -1054,12 +1046,17 @@ static int apic_register_write(int index, uint64_t = val) static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { + APICCommonState *s =3D cpu_get_current_apic(); int index =3D (addr >> 4) & 0xff; =20 if (size < 4) { return; } =20 + if (!s) { + return; + } + if (addr > 0xfff || !index) { /* * MSI and MMIO APIC are at the same memory location, @@ -1073,7 +1070,7 @@ static void apic_mem_write(void *opaque, hwaddr addr,= uint64_t val, return; } =20 - apic_register_write(index, val); + apic_register_write(s, index, val); } =20 int apic_msr_write(APICCommonState *s, int index, uint64_t val) @@ -1086,7 +1083,7 @@ int apic_msr_write(APICCommonState *s, int index, uin= t64_t val) return -1; } =20 - return apic_register_write(index, val); + return apic_register_write(s, index, val); } =20 static void apic_pre_save(APICCommonState *s) --=20 2.51.1.dirty