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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1760734367510158502 To remove any confusion with HVX or other potential store instructions, we'll qualify this context var with "scalar". Reviewed-by: Taylor Simpson Reviewed-by: Matheus Tavares Bernardino Signed-off-by: Brian Cain --- target/hexagon/idef-parser/README.rst | 2 +- target/hexagon/insn.h | 4 ++-- target/hexagon/macros.h | 8 ++++---- target/hexagon/decode.c | 4 ++-- target/hexagon/genptr.c | 3 ++- target/hexagon/idef-parser/parser-helpers.c | 4 ++-- target/hexagon/op_helper.c | 4 ++-- target/hexagon/translate.c | 9 +++++---- target/hexagon/gen_helper_funcs.py | 2 +- 9 files changed, 21 insertions(+), 19 deletions(-) diff --git a/target/hexagon/idef-parser/README.rst b/target/hexagon/idef-pa= rser/README.rst index 7199177ee3..235e3debee 100644 --- a/target/hexagon/idef-parser/README.rst +++ b/target/hexagon/idef-parser/README.rst @@ -637,7 +637,7 @@ tinycode for the Hexagon ``add`` instruction :: =20 ---- 00021094 - mov_i32 pkt_has_store_s1,$0x0 + mov_i32 pkt_has_scalar_store_s1,$0x0 add_i32 tmp0,r2,r2 mov_i32 loc2,tmp0 mov_i32 new_r1,loc2 diff --git a/target/hexagon/insn.h b/target/hexagon/insn.h index 24dcf7fe9f..5d59430da9 100644 --- a/target/hexagon/insn.h +++ b/target/hexagon/insn.h @@ -66,8 +66,8 @@ struct Packet { =20 bool pkt_has_dczeroa; =20 - bool pkt_has_store_s0; - bool pkt_has_store_s1; + bool pkt_has_scalar_store_s0; + bool pkt_has_scalar_store_s1; =20 bool pkt_has_hvx; Insn *vhist_insn; diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 9ba9be408d..088e5961ab 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -83,7 +83,7 @@ */ #define CHECK_NOSHUF(VA, SIZE) \ do { \ - if (insn->slot =3D=3D 0 && ctx->pkt->pkt_has_store_s1) { \ + if (insn->slot =3D=3D 0 && ctx->pkt->pkt_has_scalar_store_s1) { \ probe_noshuf_load(VA, SIZE, ctx->mem_idx); \ process_store(ctx, 1); \ } \ @@ -94,11 +94,11 @@ TCGLabel *noshuf_label =3D gen_new_label(); \ tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, noshuf_label); \ GET_EA; \ - if (insn->slot =3D=3D 0 && ctx->pkt->pkt_has_store_s1) { \ + if (insn->slot =3D=3D 0 && ctx->pkt->pkt_has_scalar_store_s1) { \ probe_noshuf_load(EA, SIZE, ctx->mem_idx); \ } \ gen_set_label(noshuf_label); \ - if (insn->slot =3D=3D 0 && ctx->pkt->pkt_has_store_s1) { \ + if (insn->slot =3D=3D 0 && ctx->pkt->pkt_has_scalar_store_s1) { \ process_store(ctx, 1); \ } \ } while (0) @@ -525,7 +525,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,= int shift) =20 #define fLOAD(NUM, SIZE, SIGN, EA, DST) \ do { \ - check_noshuf(env, pkt_has_store_s1, slot, EA, SIZE, GETPC()); \ + check_noshuf(env, pkt_has_scalar_store_s1, slot, EA, SIZE, GETPC()= ); \ DST =3D (size##SIZE##SIGN##_t)MEM_LOAD##SIZE(env, EA, GETPC()); \ } while (0) #endif diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c index 23deba2426..b5ece60450 100644 --- a/target/hexagon/decode.c +++ b/target/hexagon/decode.c @@ -236,9 +236,9 @@ static void decode_set_insn_attr_fields(Packet *pkt) if (GET_ATTRIB(opcode, A_SCALAR_STORE) && !GET_ATTRIB(opcode, A_MEMSIZE_0B)) { if (pkt->insn[i].slot =3D=3D 0) { - pkt->pkt_has_store_s0 =3D true; + pkt->pkt_has_scalar_store_s0 =3D true; } else { - pkt->pkt_has_store_s1 =3D true; + pkt->pkt_has_scalar_store_s1 =3D true; } } } diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 08fc5413de..cecaece4ae 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -395,7 +395,8 @@ static inline void gen_store_conditional8(DisasContext = *ctx, #ifndef CONFIG_HEXAGON_IDEF_PARSER static TCGv gen_slotval(DisasContext *ctx) { - int slotval =3D (ctx->pkt->pkt_has_store_s1 & 1) | (ctx->insn->slot <<= 1); + int slotval =3D + (ctx->pkt->pkt_has_scalar_store_s1 & 1) | (ctx->insn->slot << 1); return tcg_constant_tl(slotval); } #endif diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/i= def-parser/parser-helpers.c index 542af8d0a6..1dc52b4e02 100644 --- a/target/hexagon/idef-parser/parser-helpers.c +++ b/target/hexagon/idef-parser/parser-helpers.c @@ -1725,7 +1725,7 @@ void gen_cancel(Context *c, YYLTYPE *locp) =20 void gen_load_cancel(Context *c, YYLTYPE *locp) { - OUT(c, locp, "if (insn->slot =3D=3D 0 && pkt->pkt_has_store_s1) {\n"); + OUT(c, locp, "if (insn->slot =3D=3D 0 && pkt->pkt_has_scalar_store_s1)= {\n"); OUT(c, locp, "ctx->s1_store_processed =3D false;\n"); OUT(c, locp, "process_store(ctx, 1);\n"); OUT(c, locp, "}\n"); @@ -1750,7 +1750,7 @@ void gen_load(Context *c, YYLTYPE *locp, HexValue *wi= dth, =20 /* Lookup the effective address EA */ find_variable(c, locp, ea, ea); - OUT(c, locp, "if (insn->slot =3D=3D 0 && pkt->pkt_has_store_s1) {\n"); + OUT(c, locp, "if (insn->slot =3D=3D 0 && pkt->pkt_has_scalar_store_s1)= {\n"); OUT(c, locp, "probe_noshuf_load(", ea, ", ", width, ", ctx->mem_idx);\= n"); OUT(c, locp, "process_store(ctx, 1);\n"); OUT(c, locp, "}\n"); diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 444799d3ad..e2e80ca7ef 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -463,11 +463,11 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonSt= ate *env, int mask) * If the load is in slot 0 and there is a store in slot1 (that * wasn't cancelled), we have to do the store first. */ -static void check_noshuf(CPUHexagonState *env, bool pkt_has_store_s1, +static void check_noshuf(CPUHexagonState *env, bool pkt_has_scalar_store_s= 1, uint32_t slot, target_ulong vaddr, int size, uintptr_t ra) { - if (slot =3D=3D 0 && pkt_has_store_s1 && + if (slot =3D=3D 0 && pkt_has_scalar_store_s1 && ((env->slot_cancelled & (1 << 1)) =3D=3D 0)) { probe_read(env, vaddr, size, MMU_USER_IDX, ra); commit_store(env, 1, ra); diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 50766eafe2..8fce219c0d 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -693,11 +693,11 @@ static void process_store_log(DisasContext *ctx) * the memory accesses overlap. */ Packet *pkt =3D ctx->pkt; - if (pkt->pkt_has_store_s1) { + if (pkt->pkt_has_scalar_store_s1) { g_assert(!pkt->pkt_has_dczeroa); process_store(ctx, 1); } - if (pkt->pkt_has_store_s0) { + if (pkt->pkt_has_scalar_store_s0) { g_assert(!pkt->pkt_has_dczeroa); process_store(ctx, 0); } @@ -822,8 +822,9 @@ static void gen_commit_packet(DisasContext *ctx) * involved in committing the packet. */ Packet *pkt =3D ctx->pkt; - bool has_store_s0 =3D pkt->pkt_has_store_s0; - bool has_store_s1 =3D (pkt->pkt_has_store_s1 && !ctx->s1_store_process= ed); + bool has_store_s0 =3D pkt->pkt_has_scalar_store_s0; + bool has_store_s1 =3D + (pkt->pkt_has_scalar_store_s1 && !ctx->s1_store_processed); bool has_hvx_store =3D pkt_has_hvx_store(pkt); if (pkt->pkt_has_dczeroa) { /* diff --git a/target/hexagon/gen_helper_funcs.py b/target/hexagon/gen_helper= _funcs.py index c1f806ac4b..a9c0e27a80 100755 --- a/target/hexagon/gen_helper_funcs.py +++ b/target/hexagon/gen_helper_funcs.py @@ -69,7 +69,7 @@ def gen_helper_function(f, tag, tagregs, tagimms): if hex_common.need_slot(tag): if "A_LOAD" in hex_common.attribdict[tag]: f.write(hex_common.code_fmt(f"""\ - bool pkt_has_store_s1 =3D slotval & 0x1; + bool pkt_has_scalar_store_s1 =3D slotval & 0x1; """)) f.write(hex_common.code_fmt(f"""\ uint32_t slot =3D slotval >> 1; --=20 2.34.1