From nobody Fri Nov 14 21:03:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760718797; cv=none; d=zohomail.com; s=zohoarc; b=RNWjvz0qAMmU063u1r8dZWve2AkSaMnv+CW35t1+7bZBEtPJq1gI2czvBv0WRFZp1DaYGAlJbEv6uejfN2h3ddZYZPMPnp948rBjceyisIO9xMeh1Y9MkRgH6PTRa4OqhATXabozG3OB22JNI6BBve58OYn+W7kywYJvHGO1kT4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760718797; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+vPqycgqeHYP9wqVvXLdWY9Rm0HF5lWr6/dZ0KCgJxg=; b=myPoMY4iObA811AJuFq9EnkXwa6FaWY5g0K1ykJFYcORvb2MBNuhUXh71RL12aqo18ZzZRO818VKq3742i8ULYGfBg9s7wBoHFCne83oW7h4etRhetL27Mc/dbA+9qqqH3VH0sSGpQKjGc0+xaPy2JRKUKwiuCvDQ3mE/mYzC+8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760718797704274.3134787908566; Fri, 17 Oct 2025 09:33:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v9nNS-0004pc-9j; Fri, 17 Oct 2025 12:32:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9nNQ-0004ow-3I for qemu-devel@nongnu.org; Fri, 17 Oct 2025 12:32:24 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v9nNI-0001Cn-S9 for qemu-devel@nongnu.org; Fri, 17 Oct 2025 12:32:23 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-78af3fe5b17so1876036b3a.2 for ; Fri, 17 Oct 2025 09:32:16 -0700 (PDT) Received: from stoup.. ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29099a7d1bbsm68667715ad.65.2025.10.17.09.32.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Oct 2025 09:32:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1760718735; x=1761323535; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+vPqycgqeHYP9wqVvXLdWY9Rm0HF5lWr6/dZ0KCgJxg=; b=FdB+XdXZcLJHGjYTBLTusrL5fqM+ii20S60KOmCkRuFynaaa1fnDCgHCZxHt/Ox7To MhZOuyhi5Znr1zsw9X9XIUcLxh9OYaGfsPqEgPizLlZD1U8kYACWlJgD1pJxKdHNAc6D 9/B2tKYfGrB9hhBWp/RT6NopqkcCO90SscCRyhqQCT/pFYCOSFV+v/rEbE3SlhYtrJVB YO2N6M8WeyoarXs7s5za0u8K8QnFOImYq5D66wKYJ+TT9tUbXNqFO5SCcsc843dXNy+s CBhTo24byzSwlQgTWGF9tqywbpXMiUwZk/hA7oonIDocom2YrTzMtL8Z2otwStSQtwUr zTcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760718735; x=1761323535; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+vPqycgqeHYP9wqVvXLdWY9Rm0HF5lWr6/dZ0KCgJxg=; b=iGUBHWE8craKop2yJ/hbVoWapN/V9oFcXAiCEYs07AEv5Im75YgPj9UiEGm+XFEL8z wcaKK9gms1a851l9j3G3WLuS1u8QdUTenmdxoWATveb7fYtVGESKLIDna9X6BFmCy5XK +j07daDK29CE9l9zQRpPKT/Qs9T8pZw1xBO/nw/+rFeXcHs6yg0p9LCARZInhP2OZo4K pXc6HSd10OH3UreIGzi1L6dJkAPDpnB07HzBAYgowZIPLG7/uIegXMosL5dxaPwKFlhi nJZiTw8OQyeUXeEKXshoby4u/GyvxJ1hUbGEsmTblqMlAgUyAxTte5agHXkRD7M8ZgIB 0VOg== X-Gm-Message-State: AOJu0YwL43EnfKQzk20Dw1nV8Vq7EztcVJRX1gk/6w9lQ5gQJoL+WJ4+ +4Pvflg6kJa8OIvyNh+NeqNiXF6XSfjHOg8V64JjhZj525J9BCcKUlAHod2Bkj2dZNAeLeV7BEZ 7ZD7y9wE= X-Gm-Gg: ASbGncv7P3DQuGvG9JtkFh3Hmd6nAw11yvR7zD1QGACEJ4V+5XNh0W4J7scEILQMlL4 OlCek6YupL0uOlVaQu3QV1ddP2Er4F+FiwSLstlePFNG0K+E0JEcGOQT50f6citr25aCy4SENkn 2GPB/FuQw5+GWBE56BlalpysEgvBj+T/9l2swVbS6ippuewx0L9s7G5pWQlBep2UBjk8ncdUmB6 kVIiv+fwWMgwl6yzHerP9WZkRwfS5kkn9Q46gTcY9hOrk0zAiHvFN0UGEFSkXmVC6AFeNU4CC8v 0/YJ4EYl2UybV2FFrlbA5DBvulcBlIkrytXOHB5o06M2A00AWurrTNUI9eIYUIxJ/KC43pvd00u 4C3goDHImmpkmnJmIzh3lMIaif8VcP/41uX7xg4gOhoDIy+zkV3AkgmX017qU1d9lX+OGpA0Fr/ AbruMOImm1YEsUD44A X-Google-Smtp-Source: AGHT+IEnGrJdZpLES/C0icMv0B+WfZKFDRIrgCdTg89ILwfi2aq/0+oJzt4ypcpGLCJD6mzbKTqFtQ== X-Received: by 2002:a17:902:e944:b0:26e:e6ab:66fe with SMTP id d9443c01a7336-290c9c89033mr47493965ad.5.1760718734458; Fri, 17 Oct 2025 09:32:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 9/9] tcg/ppc: Remove support for 32-bit hosts Date: Fri, 17 Oct 2025 09:32:06 -0700 Message-ID: <20251017163206.344542-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251017163206.344542-1-richard.henderson@linaro.org> References: <20251017163206.344542-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760718800081154100 From: Philippe Mathieu-Daud=C3=A9 32-bit host support is deprecated since commit 6d701c9bac1 ("meson: Deprecate 32-bit host support"), released as v10.0. The next release being v10.2, we can remove the TCG backend for 32-bit PPC hosts. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-ID: <20251014173900.87497-2-philmd@linaro.org> --- tcg/ppc/tcg-target-has.h | 5 +- tcg/ppc/tcg-target-reg-bits.h | 8 +- tcg/ppc/tcg-target.c.inc | 385 +++++++--------------------------- 3 files changed, 79 insertions(+), 319 deletions(-) diff --git a/tcg/ppc/tcg-target-has.h b/tcg/ppc/tcg-target-has.h index 81ec5aece7..a3711feeae 100644 --- a/tcg/ppc/tcg-target-has.h +++ b/tcg/ppc/tcg-target-has.h @@ -17,12 +17,9 @@ #define have_vsx (cpuinfo & CPUINFO_VSX) =20 /* optional instructions */ -#if TCG_TARGET_REG_BITS =3D=3D 64 #define TCG_TARGET_HAS_extr_i64_i32 0 -#endif =20 -#define TCG_TARGET_HAS_qemu_ldst_i128 \ - (TCG_TARGET_REG_BITS =3D=3D 64 && have_isa_2_07) +#define TCG_TARGET_HAS_qemu_ldst_i128 have_isa_2_07 =20 #define TCG_TARGET_HAS_tst 1 =20 diff --git a/tcg/ppc/tcg-target-reg-bits.h b/tcg/ppc/tcg-target-reg-bits.h index 0efa80e7e0..3a15d7bee4 100644 --- a/tcg/ppc/tcg-target-reg-bits.h +++ b/tcg/ppc/tcg-target-reg-bits.h @@ -7,10 +7,10 @@ #ifndef TCG_TARGET_REG_BITS_H #define TCG_TARGET_REG_BITS_H =20 -#ifdef _ARCH_PPC64 -# define TCG_TARGET_REG_BITS 64 -#else -# define TCG_TARGET_REG_BITS 32 +#ifndef _ARCH_PPC64 +# error Expecting 64-bit host architecture #endif =20 +#define TCG_TARGET_REG_BITS 64 + #endif diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index cd2b68f9e1..3c36b26f25 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -29,35 +29,18 @@ * Apple XCode does not define _CALL_DARWIN. * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV or _CALL_AIX. */ -#if TCG_TARGET_REG_BITS =3D=3D 64 -# ifdef _CALL_AIX +#ifdef _CALL_AIX /* ok */ -# elif defined(_CALL_ELF) && _CALL_ELF =3D=3D 1 +#elif defined(_CALL_ELF) && _CALL_ELF =3D=3D 1 # define _CALL_AIX -# elif defined(_CALL_ELF) && _CALL_ELF =3D=3D 2 +#elif defined(_CALL_ELF) && _CALL_ELF =3D=3D 2 /* ok */ -# else -# error "Unknown ABI" -# endif #else -# if defined(_CALL_SYSV) || defined(_CALL_DARWIN) - /* ok */ -# elif defined(__APPLE__) -# define _CALL_DARWIN -# elif defined(__ELF__) -# define _CALL_SYSV -# else # error "Unknown ABI" -# endif #endif =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND -# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL -#else -# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL -# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF -#endif +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL #ifdef _CALL_SYSV # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN # define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF @@ -81,7 +64,7 @@ #define TCG_VEC_TMP2 TCG_REG_V1 =20 #define TCG_REG_TB TCG_REG_R31 -#define USE_REG_TB (TCG_TARGET_REG_BITS =3D=3D 64 && !have_isa_3_00) +#define USE_REG_TB !have_isa_3_00 =20 /* Shorthand for size of a pointer. Avoid promotion to unsigned. */ #define SZP ((int)sizeof(void *)) @@ -327,8 +310,7 @@ static bool tcg_target_const_match(int64_t sval, int ct, if (uval =3D=3D (uint32_t)uval && mask_operand(uval, &mb, &me)= ) { return 1; } - if (TCG_TARGET_REG_BITS =3D=3D 64 && - mask64_operand(uval << clz64(uval), &mb, &me)) { + if (mask64_operand(uval << clz64(uval), &mb, &me)) { return 1; } return 0; @@ -857,10 +839,8 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, T= CGReg ret, TCGReg arg) return true; } switch (type) { - case TCG_TYPE_I64: - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); - /* fallthru */ case TCG_TYPE_I32: + case TCG_TYPE_I64: if (ret < TCG_REG_V0) { if (arg < TCG_REG_V0) { tcg_out32(s, OR | SAB(arg, ret, arg)); @@ -898,7 +878,6 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) static void tcg_out_rld_rc(TCGContext *s, int op, TCGReg ra, TCGReg rs, int sh, int mb, bool rc) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); sh =3D SH(sh & 0x1f) | (((sh >> 5) & 1) << 1); mb =3D MB64((mb >> 5) | ((mb << 1) & 0x3f)); tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb | rc); @@ -946,13 +925,11 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg dst,= TCGReg src) =20 static void tcg_out_ext32s(TCGContext *s, TCGReg dst, TCGReg src) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out32(s, EXTSW | RA(dst) | RS(src)); } =20 static void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_rld(s, RLDICL, dst, src, 0, 32); } =20 @@ -968,7 +945,6 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg = dst, TCGReg src) =20 static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_mov(s, TCG_TYPE_I32, rd, rn); } =20 @@ -1037,9 +1013,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType t= ype, TCGReg ret, tcg_target_long tmp; int shift; =20 - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); - - if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I32) { + if (type =3D=3D TCG_TYPE_I32) { arg =3D (int32_t)arg; } =20 @@ -1076,7 +1050,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType t= ype, TCGReg ret, =20 /* Load 32-bit immediates with two insns. Note that we've already eliminated bare ADDIS, so we know both insns are required. */ - if (TCG_TARGET_REG_BITS =3D=3D 32 || arg =3D=3D (int32_t)arg) { + if (arg =3D=3D (int32_t)arg) { tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); tcg_out32(s, ORI | SAI(ret, ret, arg)); return; @@ -1227,19 +1201,10 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType= type, unsigned vece, if (have_vsx) { load_insn =3D type =3D=3D TCG_TYPE_V64 ? LXSDX : LXVDSX; load_insn |=3D VRT(ret) | RB(TCG_REG_TMP1); - if (TCG_TARGET_REG_BITS =3D=3D 64) { - new_pool_label(s, val, rel, s->code_ptr, add); - } else { - new_pool_l2(s, rel, s->code_ptr, add, val >> 32, val); - } + new_pool_label(s, val, rel, s->code_ptr, add); } else { load_insn =3D LVX | VRT(ret) | RB(TCG_REG_TMP1); - if (TCG_TARGET_REG_BITS =3D=3D 64) { - new_pool_l2(s, rel, s->code_ptr, add, val, val); - } else { - new_pool_l4(s, rel, s->code_ptr, add, - val >> 32, val, val >> 32, val); - } + new_pool_l2(s, rel, s->code_ptr, add, val, val); } =20 if (USE_REG_TB) { @@ -1351,7 +1316,6 @@ static void tcg_out_andi64(TCGContext *s, TCGReg dst,= TCGReg src, uint64_t c) { int mb, me; =20 - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); if (mask64_operand(c, &mb, &me)) { if (mb =3D=3D 0) { tcg_out_rld(s, RLDICR, dst, src, 0, me); @@ -1543,7 +1507,6 @@ static void tcg_out_ld(TCGContext *s, TCGType type, T= CGReg ret, break; case TCG_TYPE_I64: if (ret < TCG_REG_V0) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_mem_long(s, LD, LDX, ret, base, offset); break; } @@ -1598,7 +1561,6 @@ static void tcg_out_st(TCGContext *s, TCGType type, T= CGReg arg, break; case TCG_TYPE_I64: if (arg < TCG_REG_V0) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_mem_long(s, STD, STDX, arg, base, offset); break; } @@ -1641,7 +1603,7 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType= type, TCGArg val, static void tcg_out_test(TCGContext *s, TCGReg dest, TCGReg arg1, TCGArg a= rg2, bool const_arg2, TCGType type, bool rc) { - int mb, me; + int mb, me, sh; =20 if (!const_arg2) { tcg_out32(s, AND | SAB(arg1, dest, arg2) | rc); @@ -1664,12 +1626,10 @@ static void tcg_out_test(TCGContext *s, TCGReg dest= , TCGReg arg1, TCGArg arg2, tcg_out_rlw_rc(s, RLWINM, dest, arg1, 0, mb, me, rc); return; } - if (TCG_TARGET_REG_BITS =3D=3D 64) { - int sh =3D clz64(arg2); - if (mask64_operand(arg2 << sh, &mb, &me)) { - tcg_out_rld_rc(s, RLDICR, dest, arg1, sh, me, rc); - return; - } + sh =3D clz64(arg2); + if (mask64_operand(arg2 << sh, &mb, &me)) { + tcg_out_rld_rc(s, RLDICR, dest, arg1, sh, me, rc); + return; } /* Constraints should satisfy this. */ g_assert_not_reached(); @@ -1680,8 +1640,6 @@ static void tcg_out_cmp(TCGContext *s, int cond, TCGA= rg arg1, TCGArg arg2, { uint32_t op; =20 - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); - /* * Simplify the comparisons below wrt CMPI. * All of the tests are 16-bit, so a 32-bit sign extend always works. @@ -1747,7 +1705,7 @@ static void tcg_out_cmp(TCGContext *s, int cond, TCGA= rg arg1, TCGArg arg2, static void tcg_out_setcond_eq0(TCGContext *s, TCGType type, TCGReg dst, TCGReg src, bool neg) { - if (neg && (TCG_TARGET_REG_BITS =3D=3D 32 || type =3D=3D TCG_TYPE_I64)= ) { + if (neg && type =3D=3D TCG_TYPE_I64) { /* * X !=3D 0 implies X + -1 generates a carry. * RT =3D (~X + X) + CA @@ -1774,7 +1732,7 @@ static void tcg_out_setcond_eq0(TCGContext *s, TCGTyp= e type, static void tcg_out_setcond_ne0(TCGContext *s, TCGType type, TCGReg dst, TCGReg src, bool neg) { - if (!neg && (TCG_TARGET_REG_BITS =3D=3D 32 || type =3D=3D TCG_TYPE_I64= )) { + if (!neg && type =3D=3D TCG_TYPE_I64) { /* * X !=3D 0 implies X + -1 generates a carry. Extra addition * trickery means: R =3D X-1 + ~X + C =3D X-1 + (-X+1) + C =3D C. @@ -1814,8 +1772,6 @@ static void tcg_out_setcond(TCGContext *s, TCGType ty= pe, TCGCond cond, int sh; bool inv; =20 - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); - /* Ignore high bits of a potential constant arg2. */ if (type =3D=3D TCG_TYPE_I32) { arg2 =3D (uint32_t)arg2; @@ -2117,109 +2073,6 @@ static void tcg_out_cntxz(TCGContext *s, TCGType ty= pe, uint32_t opc, } } =20 -static void tcg_out_cmp2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, - TCGArg bl, bool blconst, TCGArg bh, bool bhconst) -{ - static const struct { uint8_t bit1, bit2; } bits[] =3D { - [TCG_COND_LT ] =3D { CR_LT, CR_LT }, - [TCG_COND_LE ] =3D { CR_LT, CR_GT }, - [TCG_COND_GT ] =3D { CR_GT, CR_GT }, - [TCG_COND_GE ] =3D { CR_GT, CR_LT }, - [TCG_COND_LTU] =3D { CR_LT, CR_LT }, - [TCG_COND_LEU] =3D { CR_LT, CR_GT }, - [TCG_COND_GTU] =3D { CR_GT, CR_GT }, - [TCG_COND_GEU] =3D { CR_GT, CR_LT }, - }; - - TCGCond cond2; - int op, bit1, bit2; - - switch (cond) { - case TCG_COND_EQ: - op =3D CRAND; - goto do_equality; - case TCG_COND_NE: - op =3D CRNAND; - do_equality: - tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32); - tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32); - tcg_out32(s, op | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); - break; - - case TCG_COND_TSTEQ: - case TCG_COND_TSTNE: - if (blconst) { - tcg_out_andi32(s, TCG_REG_R0, al, bl); - } else { - tcg_out32(s, AND | SAB(al, TCG_REG_R0, bl)); - } - if (bhconst) { - tcg_out_andi32(s, TCG_REG_TMP1, ah, bh); - } else { - tcg_out32(s, AND | SAB(ah, TCG_REG_TMP1, bh)); - } - tcg_out32(s, OR | SAB(TCG_REG_R0, TCG_REG_R0, TCG_REG_TMP1) | 1); - break; - - case TCG_COND_LT: - case TCG_COND_LE: - case TCG_COND_GT: - case TCG_COND_GE: - case TCG_COND_LTU: - case TCG_COND_LEU: - case TCG_COND_GTU: - case TCG_COND_GEU: - bit1 =3D bits[cond].bit1; - bit2 =3D bits[cond].bit2; - op =3D (bit1 !=3D bit2 ? CRANDC : CRAND); - cond2 =3D tcg_unsigned_cond(cond); - - tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32); - tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32); - tcg_out32(s, op | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2)); - tcg_out32(s, CROR | BT(0, CR_EQ) | BA(6, bit1) | BB(0, CR_EQ)); - break; - - default: - g_assert_not_reached(); - } -} - -static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, - TCGArg bh, bool const_bh) -{ - tcg_out_cmp2(s, cond, al, ah, bl, const_bl, bh, const_bh); - tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(0)); - tcg_out_rlw(s, RLWINM, ret, TCG_REG_R0, CR_EQ + 0*4 + 1, 31, 31); -} - -#if TCG_TARGET_REG_BITS !=3D 32 -__attribute__((unused)) -#endif -static const TCGOutOpSetcond2 outop_setcond2 =3D { - .base.static_constraint =3D C_O1_I4(r, r, r, rU, rC), - .out =3D tgen_setcond2, -}; - -static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, - TCGArg bh, bool const_bh, TCGLabel *l) -{ - assert(TCG_TARGET_REG_BITS =3D=3D 32); - tcg_out_cmp2(s, cond, al, ah, bl, const_bl, bh, const_bh); - tcg_out_bc_lab(s, TCG_COND_EQ, l); -} - -#if TCG_TARGET_REG_BITS !=3D 32 -__attribute__((unused)) -#endif -static const TCGOutOpBrcond2 outop_brcond2 =3D { - .base.static_constraint =3D C_O0_I4(r, r, rU, rC), - .out =3D tgen_brcond2, -}; - static void tcg_out_mb(TCGContext *s, unsigned a0) { uint32_t insn; @@ -2438,13 +2291,8 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContex= t *s, HostAddress *h, tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off); =20 /* Extract the page index, shifted into place for tlb index. */ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_shri32(s, TCG_REG_R0, addr, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - } else { - tcg_out_shri64(s, TCG_REG_R0, addr, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - } + tcg_out_shri64(s, TCG_REG_R0, addr, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); =20 /* @@ -2453,8 +2301,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, * We will ignore the high bits with tcg_out_cmp(..., addr_type). */ if (cmp_off =3D=3D 0) { - tcg_out32(s, (TCG_TARGET_REG_BITS =3D=3D 64 ? LDUX : LWZUX) - | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)); + tcg_out32(s, LDUX | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TM= P2)); } else { tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP= 2)); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP1, cmp_of= f); @@ -2464,51 +2311,36 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, * Load the TLB addend for use on the fast path. * Do this asap to minimize any load use delay. */ - if (TCG_TARGET_REG_BITS =3D=3D 64 || addr_type =3D=3D TCG_TYPE_I32= ) { - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, - offsetof(CPUTLBEntry, addend)); - } + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, + offsetof(CPUTLBEntry, addend)); =20 /* Clear the non-page, non-alignment bits from the address in R0. = */ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - /* - * We don't support unaligned accesses on 32-bits. - * Preserve the bottom bits and thus trigger a comparison - * failure on unaligned accesses. - */ - if (a_bits < s_bits) { - a_bits =3D s_bits; - } - tcg_out_rlw(s, RLWINM, TCG_REG_R0, addr, 0, + TCGReg t =3D addr; + + /* + * If the access is unaligned, we need to make sure we fail if we + * cross a page boundary. The trick is to add the access size-1 + * to the address before masking the low bits. That will make the + * address overflow to the next page if we cross a page boundary, + * which will then force a mismatch of the TLB compare. + */ + if (a_bits < s_bits) { + unsigned a_mask =3D (1 << a_bits) - 1; + unsigned s_mask =3D (1 << s_bits) - 1; + tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); + t =3D TCG_REG_R0; + } + + /* Mask the address for the requested alignment. */ + if (addr_type =3D=3D TCG_TYPE_I32) { + tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); + } else if (a_bits =3D=3D 0) { + tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS= ); } else { - TCGReg t =3D addr; - - /* - * If the access is unaligned, we need to make sure we fail if= we - * cross a page boundary. The trick is to add the access size= -1 - * to the address before masking the low bits. That will make= the - * address overflow to the next page if we cross a page bounda= ry, - * which will then force a mismatch of the TLB compare. - */ - if (a_bits < s_bits) { - unsigned a_mask =3D (1 << a_bits) - 1; - unsigned s_mask =3D (1 << s_bits) - 1; - tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); - t =3D TCG_REG_R0; - } - - /* Mask the address for the requested alignment. */ - if (addr_type =3D=3D TCG_TYPE_I32) { - tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, - (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); - } else if (a_bits =3D=3D 0) { - tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_= BITS); - } else { - tcg_out_rld(s, RLDICL, TCG_REG_R0, t, - 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bi= ts); - tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE= _BITS, 0); - } + tcg_out_rld(s, RLDICL, TCG_REG_R0, t, + 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits); + tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BIT= S, 0); } =20 /* Full comparison into cr0. */ @@ -2537,7 +2369,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, h->base =3D guest_base ? TCG_GUEST_BASE_REG : 0; } =20 - if (TCG_TARGET_REG_BITS =3D=3D 64 && addr_type =3D=3D TCG_TYPE_I32) { + if (addr_type =3D=3D TCG_TYPE_I32) { /* Zero-extend the guest address for use in the host address. */ tcg_out_ext32u(s, TCG_REG_TMP2, addr); h->index =3D TCG_REG_TMP2; @@ -2554,40 +2386,22 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOp opc =3D get_memop(oi); TCGLabelQemuLdst *ldst; HostAddress h; + uint32_t insn =3D qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; =20 ldst =3D prepare_host_addr(s, &h, addr, oi, true); =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - if (opc & MO_BSWAP) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); - tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); - tcg_out32(s, LWBRX | TAB(datahi, h.base, TCG_REG_R0)); - } else if (h.base !=3D 0) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); - tcg_out32(s, LWZX | TAB(datahi, h.base, h.index)); - tcg_out32(s, LWZX | TAB(datalo, h.base, TCG_REG_R0)); - } else if (h.index =3D=3D datahi) { - tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); - tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); - } else { - tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); - tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); - } + if (!have_isa_2_06 && insn =3D=3D LDBRX) { + tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); + tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); + tcg_out32(s, LWBRX | TAB(TCG_REG_R0, h.base, TCG_REG_R0)); + tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0); + } else if (insn) { + tcg_out32(s, insn | TAB(datalo, h.base, h.index)); } else { - uint32_t insn =3D qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; - if (!have_isa_2_06 && insn =3D=3D LDBRX) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); - tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); - tcg_out32(s, LWBRX | TAB(TCG_REG_R0, h.base, TCG_REG_R0)); - tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0); - } else if (insn) { - tcg_out32(s, insn | TAB(datalo, h.base, h.index)); - } else { - insn =3D qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; - tcg_out32(s, insn | TAB(datalo, h.base, h.index)); - tcg_out_movext(s, TCG_TYPE_REG, datalo, - TCG_TYPE_REG, opc & MO_SSIZE, datalo); - } + insn =3D qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; + tcg_out32(s, insn | TAB(datalo, h.base, h.index)); + tcg_out_movext(s, TCG_TYPE_REG, datalo, + TCG_TYPE_REG, opc & MO_SSIZE, datalo); } =20 if (ldst) { @@ -2604,32 +2418,17 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOp opc =3D get_memop(oi); TCGLabelQemuLdst *ldst; HostAddress h; + uint32_t insn =3D qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)]; =20 ldst =3D prepare_host_addr(s, &h, addr, oi, false); =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - if (opc & MO_BSWAP) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); - tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); - tcg_out32(s, STWBRX | SAB(datahi, h.base, TCG_REG_R0)); - } else if (h.base !=3D 0) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); - tcg_out32(s, STWX | SAB(datahi, h.base, h.index)); - tcg_out32(s, STWX | SAB(datalo, h.base, TCG_REG_R0)); - } else { - tcg_out32(s, STW | TAI(datahi, h.index, 0)); - tcg_out32(s, STW | TAI(datalo, h.index, 4)); - } + if (!have_isa_2_06 && insn =3D=3D STDBRX) { + tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); + tcg_out32(s, ADDI | TAI(TCG_REG_TMP2, h.index, 4)); + tcg_out_shri64(s, TCG_REG_R0, datalo, 32); + tcg_out32(s, STWBRX | SAB(TCG_REG_R0, h.base, TCG_REG_TMP2)); } else { - uint32_t insn =3D qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)]; - if (!have_isa_2_06 && insn =3D=3D STDBRX) { - tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); - tcg_out32(s, ADDI | TAI(TCG_REG_TMP2, h.index, 4)); - tcg_out_shri64(s, TCG_REG_R0, datalo, 32); - tcg_out32(s, STWBRX | SAB(TCG_REG_R0, h.base, TCG_REG_TMP2)); - } else { - tcg_out32(s, insn | SAB(datalo, h.base, h.index)); - } + tcg_out32(s, insn | SAB(datalo, h.base, h.index)); } =20 if (ldst) { @@ -2709,16 +2508,11 @@ static const TCGOutOpQemuLdSt outop_qemu_ld =3D { static void tgen_qemu_ld2(TCGContext *s, TCGType type, TCGReg datalo, TCGReg datahi, TCGReg addr, MemOpIdx oi) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_qemu_ld(s, datalo, datahi, addr, oi, type); - } else { - tcg_out_qemu_ldst_i128(s, datalo, datahi, addr, oi, true); - } + tcg_out_qemu_ldst_i128(s, datalo, datahi, addr, oi, true); } =20 static const TCGOutOpQemuLdSt2 outop_qemu_ld2 =3D { - .base.static_constraint =3D - TCG_TARGET_REG_BITS =3D=3D 64 ? C_N1O1_I1(o, m, r) : C_O2_I1(r, r,= r), + .base.static_constraint =3D C_N1O1_I1(o, m, r), .out =3D tgen_qemu_ld2, }; =20 @@ -2736,16 +2530,11 @@ static const TCGOutOpQemuLdSt outop_qemu_st =3D { static void tgen_qemu_st2(TCGContext *s, TCGType type, TCGReg datalo, TCGReg datahi, TCGReg addr, MemOpIdx oi) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_qemu_st(s, datalo, datahi, addr, oi, type); - } else { - tcg_out_qemu_ldst_i128(s, datalo, datahi, addr, oi, false); - } + tcg_out_qemu_ldst_i128(s, datalo, datahi, addr, oi, false); } =20 static const TCGOutOpQemuLdSt2 outop_qemu_st2 =3D { - .base.static_constraint =3D - TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I3(o, m, r) : C_O0_I3(r, r, r= ), + .base.static_constraint =3D C_O0_I3(o, m, r), .out =3D tgen_qemu_st2, }; =20 @@ -2767,16 +2556,11 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int = count) #elif defined(_CALL_DARWIN) # define LINK_AREA_SIZE (6 * SZR) # define LR_OFFSET (2 * SZR) -#elif TCG_TARGET_REG_BITS =3D=3D 64 +#else # if defined(_CALL_ELF) && _CALL_ELF =3D=3D 2 # define LINK_AREA_SIZE (4 * SZR) # define LR_OFFSET (1 * SZR) # endif -#else /* TCG_TARGET_REG_BITS =3D=3D 32 */ -# if defined(_CALL_SYSV) -# define LINK_AREA_SIZE (2 * SZR) -# define LR_OFFSET (1 * SZR) -# endif #endif #ifndef LR_OFFSET # error "Unhandled abi" @@ -3107,7 +2891,6 @@ static void tgen_eqv(TCGContext *s, TCGType type, tcg_out32(s, EQV | SAB(a1, a0, a2)); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg= a1) { tcg_out_shri64(s, a0, a1, 32); @@ -3117,7 +2900,6 @@ static const TCGOutOpUnary outop_extrh_i64_i32 =3D { .base.static_constraint =3D C_O1_I1(r, r), .out_rr =3D tgen_extrh_i64_i32, }; -#endif =20 static void tgen_divs(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) @@ -3596,7 +3378,6 @@ static const TCGOutOpBswap outop_bswap32 =3D { .out_rr =3D tgen_bswap32, }; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg dst, TCGReg s= rc) { TCGReg t0 =3D dst =3D=3D src ? TCG_REG_R0 : dst; @@ -3639,7 +3420,6 @@ static const TCGOutOpUnary outop_bswap64 =3D { .base.static_constraint =3D C_O1_I1(r, r), .out_rr =3D tgen_bswap64, }; -#endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ =20 static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) { @@ -3776,7 +3556,6 @@ static const TCGOutOpLoad outop_ld16s =3D { .out =3D tgen_ld16s, }; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 static void tgen_ld32u(TCGContext *s, TCGType type, TCGReg dest, TCGReg base, ptrdiff_t offset) { @@ -3798,7 +3577,6 @@ static const TCGOutOpLoad outop_ld32s =3D { .base.static_constraint =3D C_O1_I1(r, r), .out =3D tgen_ld32s, }; -#endif =20 static void tgen_st8(TCGContext *s, TCGType type, TCGReg data, TCGReg base, ptrdiff_t offset) @@ -4278,14 +4056,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, tcg_out_bitsel_vec(s, a0, a1, a2, args[3]); return; =20 - case INDEX_op_dup2_vec: - assert(TCG_TARGET_REG_BITS =3D=3D 32); - /* With inputs a1 =3D xLxx, a2 =3D xHxx */ - tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 =3D xx= HL */ - tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp =3D HL= xx */ - tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 =3D HL= HL */ - return; - case INDEX_op_ppc_mrgh_vec: insn =3D mrgh_op[vece]; break; @@ -4465,7 +4235,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne= d flags) case INDEX_op_ppc_muleu_vec: case INDEX_op_ppc_mulou_vec: case INDEX_op_ppc_pkum_vec: - case INDEX_op_dup2_vec: return C_O1_I2(v, v, v); =20 case INDEX_op_not_vec: @@ -4543,9 +4312,7 @@ static void tcg_target_init(TCGContext *s) #if defined(_CALL_SYSV) tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */ #endif -#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS =3D=3D 64 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ -#endif tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1); @@ -4566,11 +4333,7 @@ typedef struct { /* We're expecting a 2 byte uleb128 encoded value. */ QEMU_BUILD_BUG_ON(FRAME_SIZE >=3D (1 << 14)); =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -# define ELF_HOST_MACHINE EM_PPC64 -#else -# define ELF_HOST_MACHINE EM_PPC -#endif +#define ELF_HOST_MACHINE EM_PPC64 =20 static DebugFrame debug_frame =3D { .cie.len =3D sizeof(DebugFrameCIE)-4, /* length after .len member */ --=20 2.43.0