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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-471144d17cdsm85038635e9.18.2025.10.17.08.30.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Oct 2025 08:30:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1760715031; x=1761319831; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jzTp5dohZBD7ZiEa8fcC1MwOC/QjlTE8j5vm3/Ww3r0=; b=k6gpgP/b/Nw0gK7j+SQdtBUjLikoPXF2eebRB5j/jgAmF1vqzOPN1OP6cPbd3txcVT dQ9Vwt9vLTSvdrN2A4IznrgvFlySCAbHRbDot0AugiLKx8k8qy23OWHtdJV6l+H+dNvT k0LUBTJzjjxbgaAGZpKFtbs6/Nh+8XGoN4bkw+auOvGzwJ1SxR/YWwfA87paWchSutDZ YYBlyFvmYDleySbpxVaXgpNEaK+nKefc0ag49qjCoHi6yytgf3KzVFawGsc+gA8Vu8eq +Ha6THCQUz4NC9o7jfiHPeJswMIhRyfg75/aP8otmJWX/rzyrp3nEqLZT5p45CRxaG9J 33dA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760715031; x=1761319831; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jzTp5dohZBD7ZiEa8fcC1MwOC/QjlTE8j5vm3/Ww3r0=; b=fot3y4F3T1q39AMBVcR43sn77jCXy743L1/zNIVNRpFUF5BymJXXQX/x373qbSsphy YlIfQBinR8IyJ1g5XjfW6hJgD/Xf/ZAyltv5yQ3OiHLUeU40kDMVHLo2yTdy6Tww8yM+ p63DEGVlvAXAQrJpBaJbBBkaMZXpLoOrcfQoUWa8rZ0EVe7vCCRIVFwHFzseTjrzniva 0s57CC+v/CtDk0UqIf03U7GUdGqfREUilSz/cGZs4bqnQTTm3M/U+ctnaySzxTaa3oR2 7OICBdsViPRVITBkT5ZZoI2cmSn7KjAaUo8cQBNcvmCMdGO2pfxqeu5dShpzXbQEklma AwYg== X-Forwarded-Encrypted: i=1; AJvYcCV/w/EErt4KRjPVUMwuMLoQbF7QBeiumw/rdyQSg3pS9Aj/oUqLkHRQOgDVfFllvYta6CmAxmAdy0XU@nongnu.org X-Gm-Message-State: AOJu0YyjaP033GwemT0hOPsJ8wySyIvuYz7p/rgoa0x0eVBdCxqjIKjE pEPzsA44mvbqnXGxEmHHLQR7Ha5AlwTdycSzlKYX+8bEoApVtHEm+9+pDY/Dt5zbn8U= X-Gm-Gg: ASbGncv7UgfMYUjZs61wrmr3YptSL4k1cWFzJkUtiOELBtSCJkWriGKozui4BWaSUGa rNy1jeI1zgVBw2Zmg0l7GZ4vlAgDbzZlULPz0IIch2R8CnnbBxeIHBNkojTwv7FNQnuc28ZlHPJ RWS1ARTwsqOze2cRxStCd3iqz1aL8MzEne+I/I18uPZ6IL0e6aFToXo4P7vqJak4jeQ6p79zK6m xsT5DitRkvWp02JnVuu8Ky0oWvEG74RjAGpOlg94f5+6p9oTCLQW9CXSCuG+lgrLDYr5+WlB6TD jwPWz5NocqHcE34lrxuEmFZb3iLqte5d0mpSGFjTs6fsM2oljCNoEwGyo6kYXHQHeAzI8odDmp1 7Ban5v4ChVlsakHmdV2cHdnUVZfDRj120h5HnW+nC7xbwxdFCpBZdWtfkE8jlpp+4aUnWME8gvS ovY1O6oOYJV3UD2N23XoMl7JVIj6A= X-Google-Smtp-Source: AGHT+IFxFuSOiLLloabMiBtAGjsllNLQ85wFjv5vkKF/QE3MyoouLh6UOQKwOQJTtJEoj6i/Y+zMzA== X-Received: by 2002:a05:600c:8b62:b0:45d:d97c:235e with SMTP id 5b1f17b1804b1-47117876bcdmr29750615e9.12.1760715031174; Fri, 17 Oct 2025 08:30:31 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson , Vacha Bhavsar Subject: [PATCH v2 2/3] target/arm: Implement org.gnu.gdb.aarch64.tls XML feature in gdbstub Date: Fri, 17 Oct 2025 16:30:26 +0100 Message-ID: <20251017153027.969016-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251017153027.969016-1-peter.maydell@linaro.org> References: <20251017153027.969016-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760715172583154100 Content-Type: text/plain; charset="utf-8" GDB expects the TLS registers to be exposed via org.gnu.gdb.aarch64.tls, which will contain either just "tpidr", or else "tpidr" and "tpidr2". This will be important for SME in future, because the lazy state restoration scheme requires GDB to use the TPIDR2 information. GDB doesn't currently implement that, but we should provide the register via the XML so that we are ready when future GDB versions support it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/internals.h | 3 ++ target/arm/gdbstub.c | 6 ++++ target/arm/gdbstub64.c | 63 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 73 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bf221e6f973..47be3076370 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -941,6 +941,7 @@ struct ArchCPU { DynamicGDBFeatureInfo dyn_smereg_feature; DynamicGDBFeatureInfo dyn_m_systemreg_feature; DynamicGDBFeatureInfo dyn_m_secextreg_feature; + DynamicGDBFeatureInfo dyn_tls_feature; =20 /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; diff --git a/target/arm/internals.h b/target/arm/internals.h index b8b07e6477c..97ff54896e6 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1715,6 +1715,7 @@ static inline uint64_t pmu_counter_mask(CPUARMState *= env) =20 GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg); GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cpu, int base_reg); +GDBFeature *arm_gen_dynamic_tls_feature(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg); @@ -1727,6 +1728,8 @@ int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArra= y *buf, int reg); int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg); +int aarch64_gdb_get_tls_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_tls_reg(CPUState *cs, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 1ca3e647a84..8865f27089d 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -583,6 +583,12 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cp= u) 0); } #endif + + /* All AArch64 CPUs have at least TPIDR */ + gdb_register_coprocessor(cs, aarch64_gdb_get_tls_reg, + aarch64_gdb_set_tls_reg, + arm_gen_dynamic_tls_feature(cs, cs->gdb_n= um_regs), + 0); #endif } else { if (arm_feature(env, ARM_FEATURE_NEON)) { diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 5ad00fe771d..3bc7ff45d57 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -387,6 +387,44 @@ int aarch64_gdb_set_sme2_reg(CPUState *cs, uint8_t *bu= f, int reg) return 0; } =20 +int aarch64_gdb_get_tls_reg(CPUState *cs, GByteArray *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (reg) { + case 0: /* TPIDR_EL0 */ + return gdb_get_reg64(buf, env->cp15.tpidr_el[0]); + case 1: /* TPIDR2_EL0 */ + return gdb_get_reg64(buf, env->cp15.tpidr2_el0); + default: + /* gdbstub asked for something out of range */ + break; + } + + return 0; +} + +int aarch64_gdb_set_tls_reg(CPUState *cs, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (reg) { + case 0: /* TPIDR_EL0 */ + env->cp15.tpidr_el[0] =3D ldq_p(buf); + return 8; + case 1: /* TPIDR2_EL0 */ + env->cp15.tpidr2_el0 =3D ldq_p(buf); + return 8; + default: + /* gdbstub asked for something out of range */ + break; + } + + return 0; +} + int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -586,6 +624,31 @@ GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *c= s, int base_reg) return &cpu->dyn_smereg_feature.desc; } =20 +GDBFeature *arm_gen_dynamic_tls_feature(CPUState *cs, int base_reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + GDBFeatureBuilder builder; + int reg =3D 0; + + gdb_feature_builder_init(&builder, &cpu->dyn_tls_feature.desc, + "org.gnu.gdb.aarch64.tls", "tls-registers.xml= ", + base_reg); + + /* + * This feature must always have "tpidr", and may also have "tpidr2" + * if the CPU has that register. + */ + gdb_feature_builder_append_reg(&builder, "tpidr", 64, + reg++, "data_ptr", NULL); + if (cpu_isar_feature(aa64_sme, cpu)) { + gdb_feature_builder_append_reg(&builder, "tpidr2", 64, + reg++, "data_ptr", NULL); + } + gdb_feature_builder_end(&builder); + + return &cpu->dyn_tls_feature.desc; +} + #ifdef CONFIG_USER_ONLY int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg) { --=20 2.43.0