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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-471144d17cdsm85038635e9.18.2025.10.17.08.30.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Oct 2025 08:30:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1760715030; x=1761319830; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AtSS8KnvSb4J83ASd5oqMayj/FmTzdqH/eYszZmtz3A=; b=fcW1Z9eCR24xIojSOJfObrx/9xAuTAoLAvn7vUlcAhlkxF2Zi+X6MjdxSRKBlW78pZ 7dBgj3PBENPMANLO4BqR+Vs94GV3Y63bI8S0DrpJu7Xj7n360ucjiR/qH1QgYvgLsdGC SxkpzZd3EqNHAjBCc3OIyrnMgJx8rnUr3ZSlwk1lmPpJLXvz8hC+OZoQ9TyA4h/UlJia slPVNhGTA3z/zpaPJaSo8YL0D51SitCSrcbUxR4Yy5kPGnR+w2HoRYF7R96pHQe3VHUW wZqYWf/82HTbcNBlghSPT72HeLvIPxnRU1vxwsJuMVVMk1EklpcXHtQbzNK7ekL/ZKTd z/3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760715030; x=1761319830; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AtSS8KnvSb4J83ASd5oqMayj/FmTzdqH/eYszZmtz3A=; b=DHYPW5LxX78Nwqujhm8G3Ndnw1rTyiIDjlBfl69a8k/u1eFSDlR8ZvbvJANHZO34qO PEykF0FjrWywrt0poQ/25jNzqF+Un8a4Qxd8HOhDW/U2sR6Z99MWj8J4X9x0PlI2Np2c mVnTQbBofwziFqtm2ySrlCARV/EAO/lJOWnxxX5aXMirsinJqGg0cDSvzNWoYZHi1ZMj 93fuzyf4YKtSKmqYHgm4pj39LCPMJQfzqCYw/A04AU0eGX2qj5Wh1360byx6fJfyvRIL 6wDrAjZ0HqaoDwQQF3m0Gf4ymjjyhDpBmEJlngnEKMxprtaDEHee1WdjZMJR43B9Q9Wq lt8A== X-Forwarded-Encrypted: i=1; AJvYcCVmFZUx40MsrhTFl/RZEmOHs1Dnr/nvEwlVpCmsJqBIGEZAP7lIW04v6zTmI6qo5FnSBnm2SBfE1X0J@nongnu.org X-Gm-Message-State: AOJu0YymA4Mls1Ca6zoQ+PqnpPCsMuh5Lm99paDlFTD2hXV5t143JTMY jn3LN1wiepXrMu64GLNxgD2ZyNsHMaTU0ZLrjfpCazIvUXtqimLXmUZJTR8IMewtdV8= X-Gm-Gg: ASbGncvxcZ7wLlVNTCXMo3VLdsUAyPbkvBMir7Y9P44fy2OojppLCW/NjC9hHwed5pv 5c58vd/O24WvLBkdS2PqAVO2BT/TekpYyU+dzJTYpGgUlqPohCGg4YrP5NZQcms27HyI2UcgaFf qjHyo+XbQsx52OG5msINUgdGUzY+x8dXsOyT6ncdZpoy4o6TqrhRNUrHM3RJPbJf6CKswscgPH4 ZnoStP3Ih8Qah7C2b6zrduJ7L+aAP0LcP/scVwJAFfBMPSnG0TLmEo0IRAPHsbbfofa5+rB3SDp J31KVqxlsLzJKW7sTDQzYrkM+EDr9RM6NgNIhcDRxItxAzR4w0GfHn12qWCRCMbx+UNVk7ynqz2 8k4JALoUVDcMVLSy43KO9HWKyOYNmx1mkocy4Vf9/2aIKSBpUWmOPAZLy82PXwhWEzmASV7MlmJ GA7sxMLw== X-Google-Smtp-Source: AGHT+IFgsKCvYqY7LCVTEPsuKew7kaQMjAYDwZrazSQgOY26RsfDKQEqVsoXRbmozAVtgC2GT+9uRQ== X-Received: by 2002:a5d:5888:0:b0:426:f38a:a51 with SMTP id ffacd0b85a97d-42704d8d684mr3466148f8f.22.1760715030138; Fri, 17 Oct 2025 08:30:30 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson , Vacha Bhavsar Subject: [PATCH v2 1/3] target/arm: Implement SME2 support in gdbstub Date: Fri, 17 Oct 2025 16:30:25 +0100 Message-ID: <20251017153027.969016-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251017153027.969016-1-peter.maydell@linaro.org> References: <20251017153027.969016-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760715146837154100 For SME2, we need to expose the new ZT0 register in the gdbstub XML. gdb documents that the requirements are: > The =E2=80=98org.gnu.gdb.aarch64.sme2=E2=80=99 feature is optional. If p= resent, > then the =E2=80=98org.gnu.gdb.aarch64.sme=E2=80=99 feature must also be p= resent. > The =E2=80=98org.gnu.gdb.aarch64.sme2=E2=80=99 feature should contain the > following: > > - ZT0 is a register of 512 bits (64 bytes). It is defined as a > vector of bytes. Implement this. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- configs/targets/aarch64-bsd-user.mak | 2 +- configs/targets/aarch64-linux-user.mak | 2 +- configs/targets/aarch64-softmmu.mak | 2 +- configs/targets/aarch64_be-linux-user.mak | 2 +- target/arm/internals.h | 2 + target/arm/gdbstub.c | 6 +++ target/arm/gdbstub64.c | 52 +++++++++++++++++++++++ gdb-xml/aarch64-sme2.xml | 14 ++++++ 8 files changed, 78 insertions(+), 4 deletions(-) create mode 100644 gdb-xml/aarch64-sme2.xml diff --git a/configs/targets/aarch64-bsd-user.mak b/configs/targets/aarch64= -bsd-user.mak index f99c73377a9..7f42e060477 100644 --- a/configs/targets/aarch64-bsd-user.mak +++ b/configs/targets/aarch64-bsd-user.mak @@ -1,4 +1,4 @@ TARGET_ARCH=3Daarch64 TARGET_BASE_ARCH=3Darm -TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/aarch64-pauth.xml +TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/aarch64-pauth.xml gdb-xml/aarch64-sme2.xml TARGET_LONG_BITS=3D64 diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch= 64-linux-user.mak index b779ac3b4a0..bf328b3b80c 100644 --- a/configs/targets/aarch64-linux-user.mak +++ b/configs/targets/aarch64-linux-user.mak @@ -1,6 +1,6 @@ TARGET_ARCH=3Daarch64 TARGET_BASE_ARCH=3Darm -TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/aarch64-pauth.xml gdb-xml/aarch64-mte.xml +TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/aarch64-pauth.xml gdb-xml/aarch64-mte.xml gdb-xml/aarch64-sme2.xml TARGET_HAS_BFLT=3Dy CONFIG_SEMIHOSTING=3Dy CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-= softmmu.mak index 5dfeb35af90..d14bcfc4900 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -1,7 +1,7 @@ TARGET_ARCH=3Daarch64 TARGET_BASE_ARCH=3Darm TARGET_KVM_HAVE_GUEST_DEBUG=3Dy -TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sy= sregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-prof= ile-mve.xml gdb-xml/aarch64-pauth.xml +TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sy= sregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-prof= ile-mve.xml gdb-xml/aarch64-pauth.xml gdb-xml/aarch64-sme2.xml # needed by boot.c TARGET_NEED_FDT=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aa= rch64_be-linux-user.mak index ef9be02290f..284430add7b 100644 --- a/configs/targets/aarch64_be-linux-user.mak +++ b/configs/targets/aarch64_be-linux-user.mak @@ -1,7 +1,7 @@ TARGET_ARCH=3Daarch64 TARGET_BASE_ARCH=3Darm TARGET_BIG_ENDIAN=3Dy -TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/aarch64-pauth.xml gdb-xml/aarch64-mte.xml +TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/aarch64-pauth.xml gdb-xml/aarch64-mte.xml gdb-xml/aarch64-sme2.xml TARGET_HAS_BFLT=3Dy CONFIG_SEMIHOSTING=3Dy CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy diff --git a/target/arm/internals.h b/target/arm/internals.h index f539bbe58e1..b8b07e6477c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1719,6 +1719,8 @@ int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray = *buf, int reg); int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg); +int aarch64_gdb_get_sme2_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_sme2_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 8d2229f5192..1ca3e647a84 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -554,6 +554,12 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cp= u) arm_gen_dynamic_smereg_feature(cs, cs->gdb_num_regs); gdb_register_coprocessor(cs, aarch64_gdb_get_sme_reg, aarch64_gdb_set_sme_reg, sme_feature,= 0); + if (isar_feature_aa64_sme2(&cpu->isar)) { + gdb_register_coprocessor(cs, aarch64_gdb_get_sme2_reg, + aarch64_gdb_set_sme2_reg, + gdb_find_static_feature("aarch64-= sme2.xml"), + 0); + } } /* * Note that we report pauth information via the feature name diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 65d6bbe65fb..5ad00fe771d 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -335,6 +335,58 @@ int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf= , int reg) return 0; } =20 +int aarch64_gdb_get_sme2_reg(CPUState *cs, GByteArray *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + int len =3D 0; + + switch (reg) { + case 0: /* ZT0 */ + for (int i =3D 0; i < ARRAY_SIZE(env->za_state.zt0); i +=3D 2) { + len +=3D gdb_get_reg128(buf, env->za_state.zt0[i + 1], + env->za_state.zt0[i]); + } + return len; + default: + /* gdbstub asked for something out of range */ + qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__,= reg); + break; + } + + return 0; +} + +int aarch64_gdb_set_sme2_reg(CPUState *cs, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + int len =3D 0; + + switch (reg) { + case 0: /* ZT0 */ + for (int i =3D 0; i < ARRAY_SIZE(env->za_state.zt0); i +=3D 2) { + if (target_big_endian()) { + env->za_state.zt0[i + 1] =3D ldq_p(buf); + buf +=3D 8; + env->za_state.zt0[i] =3D ldq_p(buf); + } else { + env->za_state.zt0[i] =3D ldq_p(buf); + buf +=3D 8; + env->za_state.zt0[i + 1] =3D ldq_p(buf); + } + buf +=3D 8; + len +=3D 16; + } + return len; + default: + /* gdbstub asked for something out of range */ + break; + } + + return 0; +} + int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg) { ARMCPU *cpu =3D ARM_CPU(cs); diff --git a/gdb-xml/aarch64-sme2.xml b/gdb-xml/aarch64-sme2.xml new file mode 100644 index 00000000000..43911dae160 --- /dev/null +++ b/gdb-xml/aarch64-sme2.xml @@ -0,0 +1,14 @@ + + + + + + + --=20 2.43.0 From nobody Fri Nov 14 16:59:34 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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This will be important for SME in future, because the lazy state restoration scheme requires GDB to use the TPIDR2 information. GDB doesn't currently implement that, but we should provide the register via the XML so that we are ready when future GDB versions support it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/internals.h | 3 ++ target/arm/gdbstub.c | 6 ++++ target/arm/gdbstub64.c | 63 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 73 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bf221e6f973..47be3076370 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -941,6 +941,7 @@ struct ArchCPU { DynamicGDBFeatureInfo dyn_smereg_feature; DynamicGDBFeatureInfo dyn_m_systemreg_feature; DynamicGDBFeatureInfo dyn_m_secextreg_feature; + DynamicGDBFeatureInfo dyn_tls_feature; =20 /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; diff --git a/target/arm/internals.h b/target/arm/internals.h index b8b07e6477c..97ff54896e6 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1715,6 +1715,7 @@ static inline uint64_t pmu_counter_mask(CPUARMState *= env) =20 GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg); GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cpu, int base_reg); +GDBFeature *arm_gen_dynamic_tls_feature(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg); @@ -1727,6 +1728,8 @@ int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArra= y *buf, int reg); int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg); +int aarch64_gdb_get_tls_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_tls_reg(CPUState *cs, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 1ca3e647a84..8865f27089d 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -583,6 +583,12 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cp= u) 0); } #endif + + /* All AArch64 CPUs have at least TPIDR */ + gdb_register_coprocessor(cs, aarch64_gdb_get_tls_reg, + aarch64_gdb_set_tls_reg, + arm_gen_dynamic_tls_feature(cs, cs->gdb_n= um_regs), + 0); #endif } else { if (arm_feature(env, ARM_FEATURE_NEON)) { diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 5ad00fe771d..3bc7ff45d57 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -387,6 +387,44 @@ int aarch64_gdb_set_sme2_reg(CPUState *cs, uint8_t *bu= f, int reg) return 0; } =20 +int aarch64_gdb_get_tls_reg(CPUState *cs, GByteArray *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (reg) { + case 0: /* TPIDR_EL0 */ + return gdb_get_reg64(buf, env->cp15.tpidr_el[0]); + case 1: /* TPIDR2_EL0 */ + return gdb_get_reg64(buf, env->cp15.tpidr2_el0); + default: + /* gdbstub asked for something out of range */ + break; + } + + return 0; +} + +int aarch64_gdb_set_tls_reg(CPUState *cs, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (reg) { + case 0: /* TPIDR_EL0 */ + env->cp15.tpidr_el[0] =3D ldq_p(buf); + return 8; + case 1: /* TPIDR2_EL0 */ + env->cp15.tpidr2_el0 =3D ldq_p(buf); + return 8; + default: + /* gdbstub asked for something out of range */ + break; + } + + return 0; +} + int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -586,6 +624,31 @@ GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *c= s, int base_reg) return &cpu->dyn_smereg_feature.desc; } =20 +GDBFeature *arm_gen_dynamic_tls_feature(CPUState *cs, int base_reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + GDBFeatureBuilder builder; + int reg =3D 0; + + gdb_feature_builder_init(&builder, &cpu->dyn_tls_feature.desc, + "org.gnu.gdb.aarch64.tls", "tls-registers.xml= ", + base_reg); + + /* + * This feature must always have "tpidr", and may also have "tpidr2" + * if the CPU has that register. + */ + gdb_feature_builder_append_reg(&builder, "tpidr", 64, + reg++, "data_ptr", NULL); + if (cpu_isar_feature(aa64_sme, cpu)) { + gdb_feature_builder_append_reg(&builder, "tpidr2", 64, + reg++, "data_ptr", NULL); + } + gdb_feature_builder_end(&builder); + + return &cpu->dyn_tls_feature.desc; +} + #ifdef CONFIG_USER_ONLY int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg) { --=20 2.43.0 From nobody Fri Nov 14 16:59:34 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760715189; cv=none; d=zohomail.com; s=zohoarc; b=hl210V4BdAOvpnqQXE9hwvkAxJrSl+oBnI43DBy87uZ9RBx9SxL3HOWxY7vj34jv7fsYHSQ2KOk0hRowhZnKjvJJffEnU8d7I3ROH51z7+aFRIlzvcULB698/dc7jJFYjvlrAEm11mJDw+2g7ITDQVV4FE5WQSrL4r7s8Z2GoBI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760715189; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-471144d17cdsm85038635e9.18.2025.10.17.08.30.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Oct 2025 08:30:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1760715032; x=1761319832; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=psius4cHlJsmBDgSNlELg8TK6nCqMNbS0nYX0Lh5t7o=; b=Mqiechj7ANj+AvTQHr4LtS/GbweNWhCxDkhw1/s+p6wQjwYJAXXHcWP5HbMOM5RZjB kEvpqRrqYF1TdL14LG+rjvKBJGsIo75NZcXh4iXJIlqhMEucVH7T1dU1iwgMbfPBCk+h lhN8t6uP0uvaRmnbqUnDz+3ubXZsp2+Po0zkzwhN1z1jqKslR94XMfVCbjcpCkmYjiht Wh5auNossL86tGEGCn+NYkHI+aGoY0C79aznKjrf1VclRp2F/VJP/Bs42h9HHFxq7Bxq JI2HIN+2tj5Av0DPYhQFq6dbx5TMlCDYSVlqL38mSc4E8QHPKntQ3SxBt6fmlr1aqEP0 NYaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760715032; x=1761319832; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=psius4cHlJsmBDgSNlELg8TK6nCqMNbS0nYX0Lh5t7o=; b=PNDZs39H2A2YV8+tmTfzyiMfyKTE/HSQ6gJCg3lK/mnWAcK/ZRQ7VSppogfVizm1Pf VGxsQ+deuCMnWFQ7nEHNjsaurpr1h3EjELgWqtzuX93REg1QCe3p4OAixF0DmY2N1s+0 H02NviDLuNT7RIf8h9j+dtwGGqTmNPNJ58NxnTFaT2GxRQgk2GZPmOBzvuwaKguoSpBT RkBqAboRsB5HSGliakh7jHGBCaIlGpTMHwskmGsPrZJFPd+rfx7ubxk7KuY0RCWKzhOa 9UTDLSxTeyaztk/4NRdPjk0dN+6wEO8RpnibAt7i/FUhIuAaCLCpXmdM9IJXrpWEks8M jcIA== X-Forwarded-Encrypted: i=1; AJvYcCXgyjUOVxtBZfh1foCvJYtoko1bddiPlN7+tHjUGYXJe97+yRDwHI2A2SZyob49kjj8V5hQl+TnHvrh@nongnu.org X-Gm-Message-State: AOJu0YyAOxY6Anw2iQPvSdXjXi7jvlDf37Vv4+bVAluHlAON81D6Z6US zsGNv/0Jxhm02LMA6QJjJsPMQbO+A2JBxrS8pcGWv0w9IUkLym0LQtYIUSlXhVKuIZ0= X-Gm-Gg: ASbGncuDewa1TuHeZ30mnMsGj4UiAkKYJBqFEVYnM9Gls4Hrr/HbGRsm1+4GHQ4afVb cGw5Txbc8XXy8pUTF6wzZiEYaZlKEaNaGN8Jc/bTBwHuRrIWwFuFJ9Oa9lDmN8GaxHvY0d5pA// FLA5M9arqxA9qzoYANFUg1IxlP/9Mt1t1nyseLLFiVwKCV+Tm3jlfDNp3aOK+OcvaZpvFQyPadL ZwUOqHSaJnbUQRjgrbrZnWmAXd9ql2+cdyv6zDX6Qo090+PlkZZTBBRKCiXkgUtY5npnD4J53tE ObBXE6pcpkFH6w/9cXRZxmozUo+Ro5q+H0ChL0Vg+7Fo25Y4FH9m+fSMNhq1oGoNZ+8cKluieFt IMNHn7Sf/wDfOWs7SeObEZb+Njtxjy2mpu5JR2clb0ZaOpSvh++hf61I5ALSgsdcjYykLAeGAlV /qOrBMNg== X-Google-Smtp-Source: AGHT+IF7jINcGz/mkOYP+Ez6vnPD2vp8sCWWCPL2D3TgUpGrrXYwcdETQZlw+BdyZFjiSAli3KQBEg== X-Received: by 2002:a05:600c:5026:b0:470:bcc4:b07c with SMTP id 5b1f17b1804b1-47117925d38mr35605855e9.37.1760715032157; Fri, 17 Oct 2025 08:30:32 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson , Vacha Bhavsar Subject: [PATCH v2 3/3] tests/tcg/aarch64: Add test case for SME2 gdbstub registers Date: Fri, 17 Oct 2025 16:30:27 +0100 Message-ID: <20251017153027.969016-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251017153027.969016-1-peter.maydell@linaro.org> References: <20251017153027.969016-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760715193528158500 Content-Type: text/plain; charset="utf-8" Test the SME2 register exposure over gdbstub, in the same way we already do for SME. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- tests/tcg/aarch64/Makefile.target | 9 ++++++- tests/tcg/aarch64/gdbstub/test-sme2.py | 36 ++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/gdbstub/test-sme2.py diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 55ce34e45ee..9fa86874534 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -164,7 +164,14 @@ run-gdbstub-sysregs-sme-tile-slice: sysregs "selected gdb ($(GDB)) does not support SME ZA tile slices") endif =20 -EXTRA_RUNS +=3D run-gdbstub-sysregs-sme run-gdbstub-sysregs-sme-tile-slice +run-gdbstub-sysregs-sme2: sysregs + $(call run-test, $@, $(GDB_SCRIPT) \ + --gdb $(GDB) \ + --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \ + --bin $< --test $(AARCH64_SRC)/gdbstub/test-sme2.py, \ + gdbstub SME ZA tile slice support) + +EXTRA_RUNS +=3D run-gdbstub-sysregs-sme run-gdbstub-sysregs-sme-tile-slice= run-gdbstub-sysregs-sme2 =20 endif =20 diff --git a/tests/tcg/aarch64/gdbstub/test-sme2.py b/tests/tcg/aarch64/gdb= stub/test-sme2.py new file mode 100644 index 00000000000..a1663fac658 --- /dev/null +++ b/tests/tcg/aarch64/gdbstub/test-sme2.py @@ -0,0 +1,36 @@ +# +# Copyright (C) 2025 Linaro Ltd. +# +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Test the SME2 registers are visible and changeable via gdbstub +# +# This is launched via tests/guest-debug/run-test.py +# + +import gdb +from test_gdbstub import main, report + + +def run_test(): + """Test reads and writes of the SME2 registers""" + frame =3D gdb.selected_frame() + rname =3D "zt0" + zt0 =3D frame.read_register(rname) + report(True, "Reading %s" % rname) + + # Writing to the ZT0 register, byte by byte. + for i in range(0, 64): + cmd =3D "set $zt0[%d] =3D 0x01" % (i) + gdb.execute(cmd) + report(True, "%s" % cmd) + + # Reading from the ZT0 register, byte by byte. + for i in range(0, 64): + reg =3D "$zt0[%d]" % (i) + v =3D gdb.parse_and_eval(reg) + report(str(v.type) =3D=3D "uint8_t", "size of %s" % (reg)) + report(v =3D=3D 0x1, "%s is 0x%x" % (reg, 0x1)) + +main(run_test, expected_arch=3D"aarch64") --=20 2.43.0