From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1760633932; cv=none; d=zohomail.com; s=zohoarc; b=Hs40EF19SRlUcm2/XXQ//dyrlAGf1HLc/5TOcppPhj6WTpZK2UStBDD+8SE09sT0yd/18/16jTMpu5Bhz8K4+/RpZ9LuF5zzkC/2yL+nf2oj/FXLoI1C7KJUXMtNq2yzalp0qo6y28QYhPmDorxJLo/ETV0w+ZoNoPTyINj7LrY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760633932; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nGiC4vvLFeGAkADkjW8ilOYUekcixIQky++Ch/YLq1E=; b=DJl6odM74/LXh/AWL7YFN93H0Msp6lDiA7qTuMbQLl1VwYF4R5hY7PbZqYEEfXuC2d6HImBsxOszjr/wPTQsmBtQ9+fCocqRkAAvOAQ+vnrJiPaO+uLbcdbtP7O40AwfKWjNBXdlb+hDYYMJlwxLOuFjAS0v+040U95mR/l7/LI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760633932066981.8783074599021; Thu, 16 Oct 2025 09:58:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v9RHm-0000kI-Px; Thu, 16 Oct 2025 12:57:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RHk-0000j6-Ra for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:57:04 -0400 Received: from p-east2-cluster3-host8-snip4-10.eps.apple.com ([57.103.77.251] helo=outbound.st.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RHf-0001Y0-Ka for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:57:04 -0400 Received: from outbound.st.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPS id A43D418004B8; Thu, 16 Oct 2025 16:56:52 +0000 (UTC) Received: from localhost.localdomain (unknown [17.42.251.67]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPSA id AC18818015CB; Thu, 16 Oct 2025 16:55:26 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=nGiC4vvLFeGAkADkjW8ilOYUekcixIQky++Ch/YLq1E=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=aNJT16tkt+vUVMUOid7yxBIV7Hv2XqidUy/lyY9mQ7ekLGWclZ5Po/kkaS0aDANnlubOYwfazWHXuXUwzt44+ZbE8TMl3fL0A1GTjqbhLZdot0m3d9sRpQ7i5vPH11tN/8BN/QcLPZk+93LpBWKQCJhDUIYWJrWC6wNe95h3Pnl+9LWJDXGW+GFURJu00fiQ0wTfva2O1X533ESUSTq1HOJ6WwCWrpL7+5FOOCr+ZCumlGJwgIzGmbONME6Wj2jMWddzo65+HliOhPsehKQ9OFbZ6jiN+wI2wQuiXeQvEyN5NIyHXEA2LlCFpBswjsE3qmX0nMjf2ZJqfDBalbwJYg== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. 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Signed-off-by: Sebastian Ott Reviewed-by: Pierrick Bouvier --- target/arm/kvm-consts.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h index 54ae5da7ce..9fba3e886d 100644 --- a/target/arm/kvm-consts.h +++ b/target/arm/kvm-consts.h @@ -97,6 +97,8 @@ MISMATCH_CHECK(QEMU_PSCI_1_0_FN_PSCI_FEATURES, PSCI_1_0_F= N_PSCI_FEATURES); #define QEMU_PSCI_VERSION_0_2 0x00002 #define QEMU_PSCI_VERSION_1_0 0x10000 #define QEMU_PSCI_VERSION_1_1 0x10001 +#define QEMU_PSCI_VERSION_1_2 0x10002 +#define QEMU_PSCI_VERSION_1_3 0x10003 =20 MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_= MP); /* We don't bother to check every possible version value */ --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1760633900; cv=none; d=zohomail.com; s=zohoarc; b=PnOjvDeYkYdzeWRKrJZ2d3EQOOSd1zn3dR5dHgDLvGFViru79kOfbnQYhb3c9VVVcg6x0xhuR58MOccoy6yiFWJBClXddYN5kG7FaEENkyn0z7SvHBBcGX3EuRu/Rr9KKJti7m8w5B5WM3EmF5mebEODmLPMupEYkaPAywTmRDU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760633900; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=aRq3YU5535mG5uSPAFBSlmsbBJkL1R5+IAqIsTf/zZw=; b=WD8fyuAb6UClJjcfIGswHzZ4sqbiv6V5UBmtEGpbaiz2q6MZm3VVM2n6Mh9MpaOJAWPwCTXSAFKIT4rAa/zCq6FT7T25NvgASA17SmtGjb5gMfg62NRcPzpUzWZ2P2sXHTvn+b78taArcl86TtJRj5iBE/FpMOXUQSHEDv3HbrM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760633900229414.12934250346814; Thu, 16 Oct 2025 09:58:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v9RHp-0000m8-7D; Thu, 16 Oct 2025 12:57:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RHm-0000je-1w for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:57:06 -0400 Received: from p-east2-cluster3-host5-snip4-5.eps.apple.com ([57.103.77.196] helo=outbound.st.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RHg-0001YR-T2 for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:57:05 -0400 Received: from outbound.st.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPS id CF92318015CB; Thu, 16 Oct 2025 16:56:53 +0000 (UTC) Received: from localhost.localdomain (unknown [17.42.251.67]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPSA id 2184A18015DD; Thu, 16 Oct 2025 16:55:30 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=aRq3YU5535mG5uSPAFBSlmsbBJkL1R5+IAqIsTf/zZw=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type:x-icloud-hme; b=Z4TrpHlZmLiaLR6Sg1KrtcVpRUdNZUOOVtXdn76Gguh7R0omitbqSciTYNm9CSSTxCLroGH5Oq3BhJkRv78WG/dYtVViwBn9Y/GOzhsNa6Qyr5IeGZ0M7sJYpzy1EObnXCMQ9DpThz/cYBnay7OS/17h1yaweIfgFi8TJL701+T+5saL7iGKWS+dM844t4cKj9gVAzRnLMHTNRNX87ytVF8Jdo9/4rINXtjuxUY13zlMXhJv/pooqU0fjvL6Q7/xPNMb1wIUpiHboUrZ4H0fVnjVNeNvfJ8d+NNY/ds4mZnHRIoJeGzL4aAwjXx4RaKL/sWo30mijvIPSswvS6I0vQ== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/system/hw_accel.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/system/hw_accel.h b/include/system/hw_accel.h index 55497edc29..628a50e066 100644 --- a/include/system/hw_accel.h +++ b/include/system/hw_accel.h @@ -40,4 +40,17 @@ void cpu_synchronize_pre_loadvm(CPUState *cpu); void cpu_synchronize_post_reset(CPUState *cpu); void cpu_synchronize_post_init(CPUState *cpu); =20 +/** + * hwaccel_enabled: + * + * Returns: %true if a hardware accelerator is enabled, %false otherwise. + */ +static inline bool hwaccel_enabled(void) +{ + return hvf_enabled() + || kvm_enabled() + || nvmm_enabled() + || whpx_enabled(); +} + #endif /* QEMU_HW_ACCEL_H */ --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1760634312; cv=none; d=zohomail.com; s=zohoarc; b=lZFJUGrz9qK6gz2m6dSXhl9hNKc9UQ56dgxdLxBIwIWxoa79+3equMnd2QcO4zpXoUqeM3X6pt2THKk6+XOyW9FC87M+YKgYH0WQb2sK1grwJdNZapscCdIOCOb5jivof7CIoFOEOtHFqlkDnZZxeVEqW79241tmYBgaDaXmGTM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760634312; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hPQ3K0b5QowzqJ6moa7Kn8eMt6874wlqxsFHGAQGuIo=; b=gcSastDl8T+aGTL7fbxI8qhBJTPqDqOSbFNSKjxdVx84kTY9TRlGh1TCTP2KV2dMnGnQ8Qa62z4IKVXcXUS6o71lLcrZtZl3Pb8OIfxISTvTqus3sbmGVDOCWsdnTXOI+1zgHCmqVISN0BL5W+7XMDDzHAusUc3/dM4Vx5/qrYI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760634312681400.560880879391; Thu, 16 Oct 2025 10:05:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v9RHv-0000og-Fm; Thu, 16 Oct 2025 12:57:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RHp-0000lx-4R for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:57:09 -0400 Received: from p-east2-cluster3-host4-snip4-10.eps.apple.com ([57.103.77.171] helo=outbound.st.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RHg-0001Yh-82 for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:57:08 -0400 Received: from outbound.st.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPS id EC75D180076E; Thu, 16 Oct 2025 16:56:55 +0000 (UTC) Received: from localhost.localdomain (unknown [17.42.251.67]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPSA id 7291318015C3; Thu, 16 Oct 2025 16:55:33 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=hPQ3K0b5QowzqJ6moa7Kn8eMt6874wlqxsFHGAQGuIo=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=T3wbYzlANMH499iguv1V6EQLexIO4r8EPrXPY56Ljj3J3FF/yLi17qXrLXqK/jtdygYxDGwA2aMSRUMy4lj/otocMBGputBN+rTNrhVqlj9Q0JkjuMMN9JtzLfCxIV3r5X3YOghLIZiUvO/1v316w3y5jtoVu3qsrhXv7EX6/ih1L0w7cMqL1iU9cSbpIZTCkJdxvhZmES3d9dHMil/nTqokJsKtBtwWC/Wyya9iSfrDkerzKceCq3vvL3u6F+qhvhseRpGQy/yP7RoReuyC6tEFV21NgKRP4s6W+Jg5ahdzB9DPfUqZaBXok6+FUH7v13YdF0zhzirCbSCb/LJh9Q== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.77.171; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760634316058158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- tests/qtest/bios-tables-test-allowed-diff.h | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..bfc4d60124 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,2 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/APIC.its_off", --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Igor Mammedov , Paolo Bonzini , Yanan Wang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Shannon Zhao , kvm@vger.kernel.org, Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pedro Barbuda , Zhao Liu , Roman Bolshakov Subject: [PATCH v7 04/24] hw/arm: virt: add GICv2m for the case when ITS is not available Date: Thu, 16 Oct 2025 18:55:00 +0200 Message-ID: <20251016165520.62532-5-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251016165520.62532-1-mohamed@unpredictable.fr> References: <20251016165520.62532-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: NflitDkLeRPflpB13P4irTzFB3BRXTCM X-Proofpoint-ORIG-GUID: NflitDkLeRPflpB13P4irTzFB3BRXTCM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE2MDEyMiBTYWx0ZWRfX5o/RKKSk+Dk7 YxCre0muXCXuL1hDmv0p6WGJWLQCYvFnOnvNFX3AQuMI6QBha2GaVBzHKzpQt0811sQnVytY81T KOG2r/JzgCIkxgB+DUkQdE+Yff5l28Ig9vKs9aIn4hPzsyGYTW6rsfE1ud+6priH3j9Z/FtV8Ti eSIdft/8FaX91kW/uObgfIgPkYNJBe1Ql6d5V7G1KuRnoAi5+S5Kwhln+jRBbyCo6aKHAkK3rKt DlqH2OqxT/7ItwIP3WNj+sSqS5opSFEuCzgnlqEbVNf14k7Pboz+AwGJxigz9JjXj3fM3IeSk= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1030 malwarescore=0 adultscore=0 mlxscore=0 suspectscore=0 spamscore=0 bulkscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510160122 X-JNJ: AAAAAAAB141GGGzy1g/I+KVYGIgsxPYyTtG7ECm+jj6ITc5MLZ2H/pW8+t2T3yz+onpDsTEU+1Nhmmv96EcL1xB3LIQeT+Jj5MnY3Mjh3g3GjsVJpMIX7vxb84uOuCzSARfk9jqLYQVS1/G3huYAT7sEHsRJRYJ3VeAo6Kvs+eRr/hpG2CkZxCxj/lFEylxE8YOPIKVzY9b7rffv6tDpDGEfWgaYHYT+1W8rJvgOqoHI9nm0C3gu6GmtDRv/tYMZ1KKRifWIpzDbX8q2DAqx34orU23yMaxtw55ih75zTNhlbnmOFawGNClq9BxgCTdT+yX7fHlj6KaYD/dr17bJ8qehXAUWvmRD7BheGzo6zycbmlqC6wyyyEgM+cefnCv2ItVPNYTHIFUYmil29mYv7KIRe7VcMeUcT1QC6aTEsEi+3a8hbH2wnsPEIoXEBPlfJSr9zIAyBdrzuOrY0UU/cNWYiDW3d1KjvWpUaCm9tm06v+AZAM5jnHGTSjEcJWLKWnMoRfufaQyJrs5ULI+xzkBoSDjfB3jRb0+apJgjuBlel4EDlM/e2Ba+HI4OSL3n3UXwX/JYORFayco4x+liX7Ikt+w+xFv3CTCtequEeDWYab7yN+5aWGwnURg8IP/iJTeughoTTj1+9E+vZZeSL2pwQsjwfq04Inx4YolryJXve4frf6v7Ug1nB9kutJvIA0OQAH//7/MtFf8hb8U1If9AbIkPZ3jAYcd8PH4OGP5uoFsjtKQx8E/SQ64q/7K2aB+zZouOOZMCKw8dPMQD0yO5F1ZjmI/6Ljfra2PrIr7MVwdID74V2M0WY9EG6e7Xq7Oly77x67M1N3QkOKtPqx7QVgBGLFCmW0ortUZEHk3NKkFCOOHWY5/oYhGX3bD97rfH2A2837KufPC0I3vae/u4sVKU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.77.236; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760633901307158500 Content-Type: text/plain; charset="utf-8" On Hypervisor.framework for macOS and WHPX for Windows, the provided enviro= nment is a GICv3 without ITS. As such, support a GICv3 w/ GICv2m for that scenario. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- hw/arm/virt-acpi-build.c | 4 +++- hw/arm/virt.c | 8 ++++++++ include/hw/arm/virt.h | 2 ++ 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 8bb6b60515..0a6ec74aa0 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -959,7 +959,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].bas= e, 8); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ } - } else { + } + + if (!(vms->gic_version !=3D VIRT_GIC_VERSION_2 && vms->its) && !vms->n= o_gicv3_with_gicv2m) { const uint16_t spi_base =3D vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BA= SE; =20 /* 5.2.12.16 GIC MSI Frame Structure */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 175023897a..61d7bab803 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -956,6 +956,8 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) =20 if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && vms->its) { create_its(vms); + } else if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && !vms->no_gicv3_= with_gicv2m) { + create_v2m(vms); } else if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { create_v2m(vms); } @@ -2447,6 +2449,8 @@ static void machvirt_init(MachineState *machine) vms->ns_el2_virt_timer_irq =3D ns_el2_virt_timer_present() && !vmc->no_ns_el2_virt_timer_irq; =20 + vms->no_gicv3_with_gicv2m =3D vmc->no_gicv3_with_gicv2m; + fdt_add_timer_nodes(vms); fdt_add_cpu_nodes(vms); =20 @@ -3484,6 +3488,7 @@ static void virt_instance_init(Object *obj) vms->its =3D true; /* Allow ITS emulation if the machine version supports it */ vms->tcg_its =3D !vmc->no_tcg_its; + vms->no_gicv3_with_gicv2m =3D false; =20 /* Default disallows iommu instantiation */ vms->iommu =3D VIRT_IOMMU_NONE; @@ -3536,9 +3541,12 @@ DEFINE_VIRT_MACHINE_AS_LATEST(10, 2) =20 static void virt_machine_10_1_options(MachineClass *mc) { + VirtMachineClass *vmc =3D VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_10_2_options(mc); mc->smbios_memory_device_size =3D 2047 * TiB; compat_props_add(mc->compat_props, hw_compat_10_1, hw_compat_10_1_len); + vmc->no_gicv3_with_gicv2m =3D true; } DEFINE_VIRT_MACHINE(10, 1) =20 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 04a09af354..d31348dd61 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -132,6 +132,7 @@ struct VirtMachineClass { bool no_cpu_topology; bool no_tcg_lpa2; bool no_ns_el2_virt_timer_irq; + bool no_gicv3_with_gicv2m; bool no_nested_smmu; }; =20 @@ -180,6 +181,7 @@ struct VirtMachineState { char *oem_id; char *oem_table_id; bool ns_el2_virt_timer_irq; + bool no_gicv3_with_gicv2m; CXLState cxl_devices_state; bool legacy_smmuv3_present; }; --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; 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Thu, 16 Oct 2025 16:56:59 +0000 (UTC) Received: from localhost.localdomain (unknown [17.42.251.67]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPSA id 1B4C818015F7; Thu, 16 Oct 2025 16:55:39 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=9vYko/DI2RK+OqhuWK0dyFWYB5OCgm45PuZW5dC4nJ8=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=Gzby4UYUzpY3g8LA3ulEXCMPcPTQQUS2RUpDEfng7KV8eR/8kRatU59mCSf6dDHjSHWSxYFofepPHbZwQ1kDiEiLY3F7avCgMyhtvhdDcATPd/eL8MVBt5QQC41ntQuZVK1Ka0kUozgmvxIhWXHhZm7xOttxBPEQ4APdKXOPwEXpapTbqdcmd2+5X0Bd579pPpcZ0/aB/KQNMc9dqfrMcVJHdmaCV2HgUlV/gT8bL/9dW9i5iyTibQ+pSAmyobB+legHBSy+Lyc3b/iQGijtFivpEdJ6w2HV6neQPXnwFQ0sYAtkrR+1JVkS6DINoRW4OHPEMH/UbaN1vpFq6r3BLQ== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. Tsirkin" , Igor Mammedov , Paolo Bonzini , Yanan Wang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Shannon Zhao , kvm@vger.kernel.org, Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pedro Barbuda , Zhao Liu , Roman Bolshakov Subject: [PATCH v7 05/24] tests: data: update AArch64 ACPI tables Date: Thu, 16 Oct 2025 18:55:01 +0200 Message-ID: <20251016165520.62532-6-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251016165520.62532-1-mohamed@unpredictable.fr> References: <20251016165520.62532-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: nL2f9-qVKTAOT-czoVdv_a_CelvUcbF5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE2MDEyMiBTYWx0ZWRfX7McmO7U0ku9C Vo7zo9TnQ7Dqp3OkEkuK8UHp8I1ZYgSxc0nMeTY9GVSTrf6junCxUfKvo5JVGudhpczISVV+YAT TNN5rPnhJplCJvbIQFPcCkF+9yuWXnu/mmH+vuAZyPRkg7/gIr5qOvwr9Tb6hm/J2z1RqzTZMP9 ra/1O/wMGZMKKVNArF1TeE4xZEoTQ7NmKALced+StQz3O2H9391SQP98v5a/KkLoRABCwm/y/IF jOujzwEP+/mHcDxTAffFZbHHZxZtwlcf+PQmoEVihccUzUoEpWxnyxPJl1IPizaZnepNw9Ymg= X-Proofpoint-ORIG-GUID: nL2f9-qVKTAOT-czoVdv_a_CelvUcbF5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 malwarescore=0 mlxscore=0 spamscore=0 mlxlogscore=999 clxscore=1030 bulkscore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510160122 X-JNJ: AAAAAAABrUdMCKki9ilHdx9Qzz2Bf5D66wXh2PwhbP78n2nI7EphiiJDoEK87mNlONjy7lPHd1aEdwxgT0usOUl1I3zjVuEdkDhzLTrqMcby9qzqmYG81p5T9RNSyN+TilfYEcracdJZ2NR1oK0Vlll5o8r8Tlm11NNtFlRv5DnmbvCiyyUWE2yRGRolW66qziVSfooOhnj1NIU+xM0QHKRsJWMrdT0eh+P6ghm8WX1z1pfGgRCUR8rGh5CDb6IgizU4iBwigB6Z3ccn5REYtMuZZzLQl2nlr4GB/MbcgXWR7rW0c21vJ6WeK26jPbskBEyuQ3wph+crGO7HNHBUd2PW0JG8uLkJdn8XN3dY1h7meqF4+AE1W6IUUhpxKfbgDjiLowHSZI2/s4Y7kjQWI7PnjH0+mABacJjO9Fj99h0sBKdCD0ENVPaYuxmNrrm2TsdfA46afg2Ct7iW0LOzTVDBHMO0jdvCkYKzSUFsDV4zL1VxCiQXXkjaasaPTI5igGuWb1Yncv5c17XMJ8gjC/Qoz3eQKZWKhde7P4hf2whmVwhBfh3JvYKa9xkYnDOgDGslhq2bitykTIxre7frd0WB2f2hUUOf1KxdbfOanjZv/wWCU4CXYAKqop/SIUOWOvZJ3VZlyDf6get8y+iOI7GIwuFnIM6So/ryum2o/O0V1hyvHq3ehBFaBeqxRfgdD9//SqskkEhuTOwmNJgTU9+HTjEjMeYtQoyIxp4PbGD/TyL+Tl7m9BYMY1CgIxV3r0H0SxSilsLet5jrTpHmcpyXwah4HhMlf6fCxuWZWC5mZT3kXTeeV6tStxu3AYM+JRPvKFltM/RujVcuuPxchEpgG/kQhyt78C/T+dq12C2X3E3VB2WGVGa3hARyveO24sGjQ3CE1poSNAlg/HpUfMPyIgbzdt6f Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.77.247; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760633897553154100 Content-Type: text/plain; charset="utf-8" After the previous commit introducing GICv3 + GICv2m configurations, update the AArch64 ACPI table for the its=3Doff case. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- tests/data/acpi/aarch64/virt/APIC.its_off | Bin 164 -> 188 bytes tests/qtest/bios-tables-test-allowed-diff.h | 1 - 2 files changed, 1 deletion(-) diff --git a/tests/data/acpi/aarch64/virt/APIC.its_off b/tests/data/acpi/aa= rch64/virt/APIC.its_off index 6130cb7d07103b326feb4dcd7034f85808bebadf..16a01a17c0af605daf64f3cd2de= 3572be9e60cab 100644 GIT binary patch delta 43 qcmZ3&xQCI;F~HM#4+8@Oi@`*$SrWVwKqeS4aeydBAa-B~U;qHCpaq8j delta 18 ZcmdnPxP+0*F~HM#2?GNI3&%vRSpY3v1aANU diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index bfc4d60124..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,2 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/aarch64/virt/APIC.its_off", --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1760633960; cv=none; d=zohomail.com; s=zohoarc; b=GLIP7s9Q44H5pl2uimEfnqhCDV6StptrdGb+w+QvR6UfO6SN2LluvVlagvnSGg4xuhP6ncK9+ERxp/HeRdlh3cxoXoIEuGblmh1+l9IVCHJOOn9CTkoCGr3nEe+l9BduniIH92dQs2/xuiTDFd0D1xA5geVe06vClBBhRu80f5c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760633960; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/6NY7U3Atkanr4qfTcQ0H73EJM7+21eqXZpVtymAXL0=; b=Y0tNG/W2soaUA1qfwjlzaSHXZQi0tXiza5RDeG0Zo7lNrz4pHaVg0XXHwpQk3/DD4MgV4pRvl+gZTA+1WITmQtU4VhKp6cvmDMj1I6GcWTicXIZqiSKe6wE6B47IgjzPv/2+2rdr68NCWU9lexzKZz2X1xDHVDCayf6LzdiXrys= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760633960314237.97555487453212; Thu, 16 Oct 2025 09:59:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v9RI5-0000vA-Sx; Thu, 16 Oct 2025 12:57:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RI4-0000uK-67 for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:57:24 -0400 Received: from p-east2-cluster1-host7-snip4-10.eps.apple.com ([57.103.76.73] helo=outbound.st.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RHq-0001Zp-5h for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:57:23 -0400 Received: from outbound.st.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPS id C19DC18011C6; Thu, 16 Oct 2025 16:57:01 +0000 (UTC) Received: from localhost.localdomain (unknown [17.42.251.67]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPSA id 700411802068; Thu, 16 Oct 2025 16:55:43 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=/6NY7U3Atkanr4qfTcQ0H73EJM7+21eqXZpVtymAXL0=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type:x-icloud-hme; b=AajyLOgvL9vXcLc4zHr44Tsie+0WlXrijFDniaGACSDFgiiJzEUbIwvy3YKRjm/14uxkEkevnmyk9TAkieBct5lqD9MQTqy1As1IaqCusQxvVOauGL9NwjPTW+aPODLswFJYIr0BJ/1kiWK5baAwgraIVFK0v9FNgFuUpcS17ydQuJZ0HjE9JePoasmmA1aBog+Z00ugimnVGkMJYavcbIwxcP8MO6qHih9IrTZO3n1K5s84aUDDASsxYdw+7G250HwDpYVVIMdpfHQ+zpfviJmyF0CTEEGxXRv7HUY8knLLnBbCGmvBEIrlw1mz18OZ0Vz0wbLBej+Hr3hQgK8G7w== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. 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Signed-off-by: Mohamed Mediouni Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- MAINTAINERS | 2 ++ accel/meson.build | 1 + accel/whpx/meson.build | 6 ++++++ {target/i386 =3D> accel}/whpx/whpx-accel-ops.c | 4 ++-- {target/i386/whpx =3D> include/system}/whpx-accel-ops.h | 4 ++-- {target/i386/whpx =3D> include/system}/whpx-internal.h | 5 +++-- target/i386/whpx/meson.build | 1 - target/i386/whpx/whpx-all.c | 4 ++-- target/i386/whpx/whpx-apic.c | 2 +- 9 files changed, 19 insertions(+), 10 deletions(-) create mode 100644 accel/whpx/meson.build rename {target/i386 =3D> accel}/whpx/whpx-accel-ops.c (97%) rename {target/i386/whpx =3D> include/system}/whpx-accel-ops.h (92%) rename {target/i386/whpx =3D> include/system}/whpx-internal.h (98%) diff --git a/MAINTAINERS b/MAINTAINERS index 0c766961f3..c25e22ffdb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -547,9 +547,11 @@ F: include/system/hvf_int.h WHPX CPUs M: Sunil Muthuswamy S: Supported +F: accel/whpx/ F: target/i386/whpx/ F: accel/stubs/whpx-stub.c F: include/system/whpx.h +F: include/system/whpx-accel-ops.h =20 MSHV M: Magnus Kulke diff --git a/accel/meson.build b/accel/meson.build index 983dfd0bd5..289b7420ff 100644 --- a/accel/meson.build +++ b/accel/meson.build @@ -6,6 +6,7 @@ user_ss.add(files('accel-user.c')) subdir('tcg') if have_system subdir('hvf') + subdir('whpx') subdir('qtest') subdir('kvm') subdir('xen') diff --git a/accel/whpx/meson.build b/accel/whpx/meson.build new file mode 100644 index 0000000000..7b3d6f1c1c --- /dev/null +++ b/accel/whpx/meson.build @@ -0,0 +1,6 @@ +whpx_ss =3D ss.source_set() +whpx_ss.add(files( + 'whpx-accel-ops.c', +)) + +specific_ss.add_all(when: 'CONFIG_WHPX', if_true: whpx_ss) diff --git a/target/i386/whpx/whpx-accel-ops.c b/accel/whpx/whpx-accel-ops.c similarity index 97% rename from target/i386/whpx/whpx-accel-ops.c rename to accel/whpx/whpx-accel-ops.c index f75886128d..c84a25c273 100644 --- a/target/i386/whpx/whpx-accel-ops.c +++ b/accel/whpx/whpx-accel-ops.c @@ -16,8 +16,8 @@ #include "qemu/guest-random.h" =20 #include "system/whpx.h" -#include "whpx-internal.h" -#include "whpx-accel-ops.h" +#include "system/whpx-internal.h" +#include "system/whpx-accel-ops.h" =20 static void *whpx_cpu_thread_fn(void *arg) { diff --git a/target/i386/whpx/whpx-accel-ops.h b/include/system/whpx-accel-= ops.h similarity index 92% rename from target/i386/whpx/whpx-accel-ops.h rename to include/system/whpx-accel-ops.h index 54cfc25a14..ed9d4c49f4 100644 --- a/target/i386/whpx/whpx-accel-ops.h +++ b/include/system/whpx-accel-ops.h @@ -7,8 +7,8 @@ * See the COPYING file in the top-level directory. */ =20 -#ifndef TARGET_I386_WHPX_ACCEL_OPS_H -#define TARGET_I386_WHPX_ACCEL_OPS_H +#ifndef SYSTEM_WHPX_ACCEL_OPS_H +#define SYSTEM_WHPX_ACCEL_OPS_H =20 #include "system/cpus.h" =20 diff --git a/target/i386/whpx/whpx-internal.h b/include/system/whpx-interna= l.h similarity index 98% rename from target/i386/whpx/whpx-internal.h rename to include/system/whpx-internal.h index 6633e9c4ca..e61375d554 100644 --- a/target/i386/whpx/whpx-internal.h +++ b/include/system/whpx-internal.h @@ -1,5 +1,6 @@ -#ifndef TARGET_I386_WHPX_INTERNAL_H -#define TARGET_I386_WHPX_INTERNAL_H +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef SYSTEM_WHPX_INTERNAL_H +#define SYSTEM_WHPX_INTERNAL_H =20 #include #include diff --git a/target/i386/whpx/meson.build b/target/i386/whpx/meson.build index 9c54aaad39..c3aaaff9fd 100644 --- a/target/i386/whpx/meson.build +++ b/target/i386/whpx/meson.build @@ -1,5 +1,4 @@ i386_system_ss.add(when: 'CONFIG_WHPX', if_true: files( 'whpx-all.c', 'whpx-apic.c', - 'whpx-accel-ops.c', )) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 256761834c..106a352980 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -31,8 +31,8 @@ #include "accel/accel-cpu-target.h" #include =20 -#include "whpx-internal.h" -#include "whpx-accel-ops.h" +#include "system/whpx-internal.h" +#include "system/whpx-accel-ops.h" =20 #include #include diff --git a/target/i386/whpx/whpx-apic.c b/target/i386/whpx/whpx-apic.c index e1ef6d4e6d..badb404b63 100644 --- a/target/i386/whpx/whpx-apic.c +++ b/target/i386/whpx/whpx-apic.c @@ -18,7 +18,7 @@ #include "hw/pci/msi.h" #include "system/hw_accel.h" #include "system/whpx.h" -#include "whpx-internal.h" +#include "system/whpx-internal.h" =20 struct whpx_lapic_state { struct { --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Igor Mammedov , Paolo Bonzini , Yanan Wang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Shannon Zhao , kvm@vger.kernel.org, Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pedro Barbuda , Zhao Liu , Roman Bolshakov , Pierrick Bouvier Subject: [PATCH v7 07/24] whpx: reshuffle common code Date: Thu, 16 Oct 2025 18:55:03 +0200 Message-ID: <20251016165520.62532-8-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251016165520.62532-1-mohamed@unpredictable.fr> References: <20251016165520.62532-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE2MDEyMiBTYWx0ZWRfX01IW8HsFhCAt PTWd9u0dF0HG3wnU+lld1HeMmy4fnonbOwNFtWDPCgIrQnA9tNilSJNweHUkOpSTuwb6TPizEpv o5qo6eHqc+2U2txSrBiKZkIQXyuevAynmMa266viRW1ZRUNU6Ay6+6qS2KGabhBbMmoqCksyYHZ m1iMqiE5hanIYAk0VVMSRFUhD0wnsZQmHqfFd9pEAwq0VciMvTXsqfyNUy7f0/Xa0TXF8bvtZGL 6keuhN9O+6Qm6w2H2VW5vdWAIoDxzGCu/JQheGIObiYIe7UcdO+jx0BJ5eRvV6FzdaYJ9+NYw= X-Proofpoint-GUID: jyVvEK-PZvU1Daf0Zv5Pm9qiOHZECpxx X-Proofpoint-ORIG-GUID: jyVvEK-PZvU1Daf0Zv5Pm9qiOHZECpxx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 adultscore=0 clxscore=1030 phishscore=0 malwarescore=0 mlxscore=0 spamscore=0 bulkscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510160122 X-JNJ: AAAAAAABJfdc0ZiI4mVm8EW5GpcSFS9Wr4Xep1wb8sD/n8xkDnDk8MQQTqLmFaQkd7G71DaX8PSLmM5ibpC41c/z+yNzsl7aYRwvEqNSjlY6Sd2bYzHzQWYAsdIO3iwu6sUuZzcxQK10cuJfV5iPF3bmYkbUnCx0D/WgTtOtMFx5sOZxyCxheq8OGyLSNyLQfuogahe6PGBK5jLWmD4Ibdez8N8xVBdiJZK67eHxb/u5OV6sFgFgWCFvX/WV6zik1LZAS42S5qRdnhQ2ZkKyn4YFOKd5NoO+SV1Qut4W7TSuYkiUSpRvoCqHvLuJDFoT81CxgApURrby4kOvkW6chQ0sucnLrjQrbRDVedMA8XL1w1HDb4nYgKPSPjYpjoXKwqCx8OZwdAL3oGKk7WqNE/oGfCZDt3Q8ENMjUj/NxU7ZQ7bxCd0hmtK1qb09Yd3mQiWAmkcJExZTlwnrmTpFxyXx+DqcoU1QUN5xFcnhSk4r9vHOL/oJYSnenRRjhGaXFkmy1OEF1I4FXx44umCi6APK4ZnYagdYGrNCcOc5jeXgau0LdqbDVA/dsw0fWZkFedzHfJ1IWXJGEv3zt5xBSnEgBUn/iAYEJnCMSKv/wzcXpnPqG40hCd9oo9i3y8rnlcg71Q8vm1QNL/mfZGG72UZLrM5zMltzfRubtwy3hZoTxX4592RLjKs0SsvXVgpsR0RthJQ38w+Zahv2gPT/xhyIQc4qfHWKpwWGZnqyxBQYzA1095D9GRvLJPK5Y6pUGrg4KnAnSjiHkzKVjJyCyXATncFB7f76Nppks7kXd/2A2B4UoZgnCf2QeR3dDrjnYi3Ctm1F2WGiaAH1VF0nt5TwGHRHuTWlW2igtFiYdaHiv15a43Wt7xEDBTfba0Ky Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.76.18; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760633913389154100 Content-Type: text/plain; charset="utf-8" Some code can be shared between x86_64 and arm64 WHPX. Do so as much as rea= sonable. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- MAINTAINERS | 2 + accel/whpx/meson.build | 1 + accel/whpx/whpx-common.c | 562 +++++++++++++++++++++++++++++++++++ include/system/whpx-all.h | 20 ++ include/system/whpx-common.h | 21 ++ target/i386/whpx/whpx-all.c | 551 +--------------------------------- 6 files changed, 616 insertions(+), 541 deletions(-) create mode 100644 accel/whpx/whpx-common.c create mode 100644 include/system/whpx-all.h create mode 100644 include/system/whpx-common.h diff --git a/MAINTAINERS b/MAINTAINERS index c25e22ffdb..a516e66642 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -552,6 +552,8 @@ F: target/i386/whpx/ F: accel/stubs/whpx-stub.c F: include/system/whpx.h F: include/system/whpx-accel-ops.h +F: include/system/whpx-common.h +F: include/system/whpx-internal.h =20 MSHV M: Magnus Kulke diff --git a/accel/whpx/meson.build b/accel/whpx/meson.build index 7b3d6f1c1c..fad28dddcb 100644 --- a/accel/whpx/meson.build +++ b/accel/whpx/meson.build @@ -1,6 +1,7 @@ whpx_ss =3D ss.source_set() whpx_ss.add(files( 'whpx-accel-ops.c', + 'whpx-common.c' )) =20 specific_ss.add_all(when: 'CONFIG_WHPX', if_true: whpx_ss) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c new file mode 100644 index 0000000000..66c9238586 --- /dev/null +++ b/accel/whpx/whpx-common.c @@ -0,0 +1,562 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU Windows Hypervisor Platform accelerator (WHPX) + * + * Copyright Microsoft Corp. 2017 + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "system/address-spaces.h" +#include "system/ioport.h" +#include "gdbstub/helpers.h" +#include "qemu/accel.h" +#include "accel/accel-ops.h" +#include "system/whpx.h" +#include "system/cpus.h" +#include "system/runstate.h" +#include "qemu/main-loop.h" +#include "hw/boards.h" +#include "hw/intc/ioapic.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "qapi/qapi-types-common.h" +#include "qapi/qapi-visit-common.h" +#include "migration/blocker.h" +#include "accel/accel-cpu-target.h" +#include + +#include "system/whpx-internal.h" +#include "system/whpx-accel-ops.h" +#include "system/whpx-common.h" +#include "system/whpx-all.h" + +#include +#include + +bool whpx_allowed; +static bool whp_dispatch_initialized; +static HMODULE hWinHvPlatform; +static HMODULE hWinHvEmulation; + +struct whpx_state whpx_global; +struct WHPDispatch whp_dispatch; + +/* Tries to find a breakpoint at the specified address. */ +struct whpx_breakpoint *whpx_lookup_breakpoint_by_addr(uint64_t address) +{ + struct whpx_state *whpx =3D &whpx_global; + int i; + + if (whpx->breakpoints.breakpoints) { + for (i =3D 0; i < whpx->breakpoints.breakpoints->used; i++) { + if (address =3D=3D whpx->breakpoints.breakpoints->data[i].addr= ess) { + return &whpx->breakpoints.breakpoints->data[i]; + } + } + } + + return NULL; +} + +/* + * This function is called when the a VCPU is about to start and no other + * VCPUs have been started so far. Since the VCPU start order could be + * arbitrary, it doesn't have to be VCPU#0. + * + * It is used to commit the breakpoints into memory, and configure WHPX + * to intercept debug exceptions. + * + * Note that whpx_set_exception_exit_bitmap() cannot be called if one or + * more VCPUs are already running, so this is the best place to do it. + */ +int whpx_first_vcpu_starting(CPUState *cpu) +{ + struct whpx_state *whpx =3D &whpx_global; + + g_assert(bql_locked()); + + if (!QTAILQ_EMPTY(&cpu->breakpoints) || + (whpx->breakpoints.breakpoints && + whpx->breakpoints.breakpoints->used)) { + CPUBreakpoint *bp; + int i =3D 0; + bool update_pending =3D false; + + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + if (i >=3D whpx->breakpoints.original_address_count || + bp->pc !=3D whpx->breakpoints.original_addresses[i]) { + update_pending =3D true; + } + + i++; + } + + if (i !=3D whpx->breakpoints.original_address_count) { + update_pending =3D true; + } + + if (update_pending) { + /* + * The CPU breakpoints have changed since the last call to + * whpx_translate_cpu_breakpoints(). WHPX breakpoints must + * now be recomputed. + */ + whpx_translate_cpu_breakpoints(&whpx->breakpoints, cpu, i); + } + /* Actually insert the breakpoints into the memory. */ + whpx_apply_breakpoints(whpx->breakpoints.breakpoints, cpu, true); + } + HRESULT hr; + uint64_t exception_mask; + if (whpx->step_pending || + (whpx->breakpoints.breakpoints && + whpx->breakpoints.breakpoints->used)) { + /* + * We are either attempting to single-step one or more CPUs, or + * have one or more breakpoints enabled. Both require intercepting + * the WHvX64ExceptionTypeBreakpointTrap exception. + */ + exception_mask =3D 1UL << WHvX64ExceptionTypeDebugTrapOrFault; + } else { + /* Let the guest handle all exceptions. */ + exception_mask =3D 0; + } + hr =3D whpx_set_exception_exit_bitmap(exception_mask); + if (!SUCCEEDED(hr)) { + error_report("WHPX: Failed to update exception exit mask," + "hr=3D%08lx.", hr); + return 1; + } + return 0; +} + +/* + * This function is called when the last VCPU has finished running. + * It is used to remove any previously set breakpoints from memory. + */ +int whpx_last_vcpu_stopping(CPUState *cpu) +{ + whpx_apply_breakpoints(whpx_global.breakpoints.breakpoints, cpu, false= ); + return 0; +} + +static void do_whpx_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data a= rg) +{ + if (!cpu->vcpu_dirty) { + whpx_get_registers(cpu); + cpu->vcpu_dirty =3D true; + } +} + +static void do_whpx_cpu_synchronize_post_reset(CPUState *cpu, + run_on_cpu_data arg) +{ + whpx_set_registers(cpu, WHPX_SET_RESET_STATE); + cpu->vcpu_dirty =3D false; +} + +static void do_whpx_cpu_synchronize_post_init(CPUState *cpu, + run_on_cpu_data arg) +{ + whpx_set_registers(cpu, WHPX_SET_FULL_STATE); + cpu->vcpu_dirty =3D false; +} + +static void do_whpx_cpu_synchronize_pre_loadvm(CPUState *cpu, + run_on_cpu_data arg) +{ + cpu->vcpu_dirty =3D true; +} + +/* + * CPU support. + */ + +void whpx_cpu_synchronize_state(CPUState *cpu) +{ + if (!cpu->vcpu_dirty) { + run_on_cpu(cpu, do_whpx_cpu_synchronize_state, RUN_ON_CPU_NULL); + } +} + +void whpx_cpu_synchronize_post_reset(CPUState *cpu) +{ + run_on_cpu(cpu, do_whpx_cpu_synchronize_post_reset, RUN_ON_CPU_NULL); +} + +void whpx_cpu_synchronize_post_init(CPUState *cpu) +{ + run_on_cpu(cpu, do_whpx_cpu_synchronize_post_init, RUN_ON_CPU_NULL); +} + +void whpx_cpu_synchronize_pre_loadvm(CPUState *cpu) +{ + run_on_cpu(cpu, do_whpx_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL); +} + +static void whpx_pre_resume_vm(AccelState *as, bool step_pending) +{ + whpx_global.step_pending =3D step_pending; +} + +/* + * Vcpu support. + */ + +int whpx_vcpu_exec(CPUState *cpu) +{ + int ret; + int fatal; + + for (;;) { + if (cpu->exception_index >=3D EXCP_INTERRUPT) { + ret =3D cpu->exception_index; + cpu->exception_index =3D -1; + break; + } + + fatal =3D whpx_vcpu_run(cpu); + + if (fatal) { + error_report("WHPX: Failed to exec a virtual processor"); + abort(); + } + } + + return ret; +} + +void whpx_destroy_vcpu(CPUState *cpu) +{ + struct whpx_state *whpx =3D &whpx_global; + + whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index= ); + AccelCPUState *vcpu =3D cpu->accel; + whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator); + g_free(cpu->accel); +} + + +void whpx_vcpu_kick(CPUState *cpu) +{ + struct whpx_state *whpx =3D &whpx_global; + whp_dispatch.WHvCancelRunVirtualProcessor( + whpx->partition, cpu->cpu_index, 0); +} + +/* + * Memory support. + */ + +static void whpx_update_mapping(hwaddr start_pa, ram_addr_t size, + void *host_va, int add, int rom, + const char *name) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + + /* + if (add) { + printf("WHPX: ADD PA:%p Size:%p, Host:%p, %s, '%s'\n", + (void*)start_pa, (void*)size, host_va, + (rom ? "ROM" : "RAM"), name); + } else { + printf("WHPX: DEL PA:%p Size:%p, Host:%p, '%s'\n", + (void*)start_pa, (void*)size, host_va, name); + } + */ + + if (add) { + hr =3D whp_dispatch.WHvMapGpaRange(whpx->partition, + host_va, + start_pa, + size, + (WHvMapGpaRangeFlagRead | + WHvMapGpaRangeFlagExecute | + (rom ? 0 : WHvMapGpaRangeFlagWri= te))); + } else { + hr =3D whp_dispatch.WHvUnmapGpaRange(whpx->partition, + start_pa, + size); + } + + if (FAILED(hr)) { + error_report("WHPX: Failed to %s GPA range '%s' PA:%p, Size:%p byt= es," + " Host:%p, hr=3D%08lx", + (add ? "MAP" : "UNMAP"), name, + (void *)(uintptr_t)start_pa, (void *)size, host_va, h= r); + } +} + +static void whpx_process_section(MemoryRegionSection *section, int add) +{ + MemoryRegion *mr =3D section->mr; + hwaddr start_pa =3D section->offset_within_address_space; + ram_addr_t size =3D int128_get64(section->size); + unsigned int delta; + uint64_t host_va; + + if (!memory_region_is_ram(mr)) { + return; + } + + delta =3D qemu_real_host_page_size() - (start_pa & ~qemu_real_host_pag= e_mask()); + delta &=3D ~qemu_real_host_page_mask(); + if (delta > size) { + return; + } + start_pa +=3D delta; + size -=3D delta; + size &=3D qemu_real_host_page_mask(); + if (!size || (start_pa & ~qemu_real_host_page_mask())) { + return; + } + + host_va =3D (uintptr_t)memory_region_get_ram_ptr(mr) + + section->offset_within_region + delta; + + whpx_update_mapping(start_pa, size, (void *)(uintptr_t)host_va, add, + memory_region_is_rom(mr), mr->name); +} + +static void whpx_region_add(MemoryListener *listener, + MemoryRegionSection *section) +{ + memory_region_ref(section->mr); + whpx_process_section(section, 1); +} + +static void whpx_region_del(MemoryListener *listener, + MemoryRegionSection *section) +{ + whpx_process_section(section, 0); + memory_region_unref(section->mr); +} + +static void whpx_transaction_begin(MemoryListener *listener) +{ +} + +static void whpx_transaction_commit(MemoryListener *listener) +{ +} + +static void whpx_log_sync(MemoryListener *listener, + MemoryRegionSection *section) +{ + MemoryRegion *mr =3D section->mr; + + if (!memory_region_is_ram(mr)) { + return; + } + + memory_region_set_dirty(mr, 0, int128_get64(section->size)); +} + +static MemoryListener whpx_memory_listener =3D { + .name =3D "whpx", + .begin =3D whpx_transaction_begin, + .commit =3D whpx_transaction_commit, + .region_add =3D whpx_region_add, + .region_del =3D whpx_region_del, + .log_sync =3D whpx_log_sync, + .priority =3D MEMORY_LISTENER_PRIORITY_ACCEL, +}; + +void whpx_memory_init(void) +{ + memory_listener_register(&whpx_memory_listener, &address_space_memory); +} + +/* + * Load the functions from the given library, using the given handle. If a + * handle is provided, it is used, otherwise the library is opened. The + * handle will be updated on return with the opened one. + */ +static bool load_whp_dispatch_fns(HMODULE *handle, + WHPFunctionList function_list) +{ + HMODULE hLib =3D *handle; + + #define WINHV_PLATFORM_DLL "WinHvPlatform.dll" + #define WINHV_EMULATION_DLL "WinHvEmulation.dll" + #define WHP_LOAD_FIELD_OPTIONAL(return_type, function_name, signature)= \ + whp_dispatch.function_name =3D \ + (function_name ## _t)GetProcAddress(hLib, #function_name); \ + + #define WHP_LOAD_FIELD(return_type, function_name, signature) \ + whp_dispatch.function_name =3D \ + (function_name ## _t)GetProcAddress(hLib, #function_name); \ + if (!whp_dispatch.function_name) { \ + error_report("Could not load function %s", #function_name); \ + goto error; \ + } \ + + #define WHP_LOAD_LIB(lib_name, handle_lib) \ + if (!handle_lib) { \ + handle_lib =3D LoadLibrary(lib_name); \ + if (!handle_lib) { \ + error_report("Could not load library %s.", lib_name); \ + goto error; \ + } \ + } \ + + switch (function_list) { + case WINHV_PLATFORM_FNS_DEFAULT: + WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib) + LIST_WINHVPLATFORM_FUNCTIONS(WHP_LOAD_FIELD) + break; + case WINHV_EMULATION_FNS_DEFAULT: + WHP_LOAD_LIB(WINHV_EMULATION_DLL, hLib) + LIST_WINHVEMULATION_FUNCTIONS(WHP_LOAD_FIELD) + break; + case WINHV_PLATFORM_FNS_SUPPLEMENTAL: + WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib) + LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL(WHP_LOAD_FIELD_OPTIONAL) + break; + } + + *handle =3D hLib; + return true; + +error: + if (hLib) { + FreeLibrary(hLib); + } + + return false; +} + +static void whpx_set_kernel_irqchip(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + struct whpx_state *whpx =3D &whpx_global; + OnOffSplit mode; + + if (!visit_type_OnOffSplit(v, name, &mode, errp)) { + return; + } + + switch (mode) { + case ON_OFF_SPLIT_ON: + whpx->kernel_irqchip_allowed =3D true; + whpx->kernel_irqchip_required =3D true; + break; + + case ON_OFF_SPLIT_OFF: + whpx->kernel_irqchip_allowed =3D false; + whpx->kernel_irqchip_required =3D false; + break; + + case ON_OFF_SPLIT_SPLIT: + error_setg(errp, "WHPX: split irqchip currently not supported"); + error_append_hint(errp, + "Try without kernel-irqchip or with kernel-irqchip=3Don|off"); + break; + + default: + /* + * The value was checked in visit_type_OnOffSplit() above. If + * we get here, then something is wrong in QEMU. + */ + abort(); + } +} + +static void whpx_cpu_accel_class_init(ObjectClass *oc, const void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_instance_init =3D whpx_cpu_instance_init; +} + +static const TypeInfo whpx_cpu_accel_type =3D { + .name =3D ACCEL_CPU_NAME("whpx"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D whpx_cpu_accel_class_init, + .abstract =3D true, +}; + +/* + * Partition support + */ + +bool whpx_apic_in_platform(void) +{ + return whpx_global.apic_in_platform; +} + +static void whpx_accel_class_init(ObjectClass *oc, const void *data) +{ + AccelClass *ac =3D ACCEL_CLASS(oc); + ac->name =3D "WHPX"; + ac->init_machine =3D whpx_accel_init; + ac->pre_resume_vm =3D whpx_pre_resume_vm; + ac->allowed =3D &whpx_allowed; + + object_class_property_add(oc, "kernel-irqchip", "on|off|split", + NULL, whpx_set_kernel_irqchip, + NULL, NULL); + object_class_property_set_description(oc, "kernel-irqchip", + "Configure WHPX in-kernel irqchip"); +} + +static void whpx_accel_instance_init(Object *obj) +{ + struct whpx_state *whpx =3D &whpx_global; + + memset(whpx, 0, sizeof(struct whpx_state)); + /* Turn on kernel-irqchip, by default */ + whpx->kernel_irqchip_allowed =3D true; +} + +static const TypeInfo whpx_accel_type =3D { + .name =3D ACCEL_CLASS_NAME("whpx"), + .parent =3D TYPE_ACCEL, + .instance_init =3D whpx_accel_instance_init, + .class_init =3D whpx_accel_class_init, +}; + +static void whpx_type_init(void) +{ + type_register_static(&whpx_accel_type); + type_register_static(&whpx_cpu_accel_type); +} + +bool init_whp_dispatch(void) +{ + if (whp_dispatch_initialized) { + return true; + } + + if (!load_whp_dispatch_fns(&hWinHvPlatform, WINHV_PLATFORM_FNS_DEFAULT= )) { + goto error; + } + + if (!load_whp_dispatch_fns(&hWinHvEmulation, WINHV_EMULATION_FNS_DEFAU= LT)) { + goto error; + } + + assert(load_whp_dispatch_fns(&hWinHvPlatform, + WINHV_PLATFORM_FNS_SUPPLEMENTAL)); + whp_dispatch_initialized =3D true; + + return true; +error: + if (hWinHvPlatform) { + FreeLibrary(hWinHvPlatform); + } + if (hWinHvEmulation) { + FreeLibrary(hWinHvEmulation); + } + return false; +} + +type_init(whpx_type_init); diff --git a/include/system/whpx-all.h b/include/system/whpx-all.h new file mode 100644 index 0000000000..f13cdf7f66 --- /dev/null +++ b/include/system/whpx-all.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef SYSTEM_WHPX_ALL_H +#define SYSTEM_WHPX_ALL_H + +/* Called by whpx-common */ +int whpx_vcpu_run(CPUState *cpu); +void whpx_get_registers(CPUState *cpu); +void whpx_set_registers(CPUState *cpu, int level); +int whpx_accel_init(AccelState *as, MachineState *ms); +void whpx_cpu_instance_init(CPUState *cs); +HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions); +void whpx_apply_breakpoints( +struct whpx_breakpoint_collection *breakpoints, + CPUState *cpu, + bool resuming); +void whpx_translate_cpu_breakpoints( + struct whpx_breakpoints *breakpoints, + CPUState *cpu, + int cpu_breakpoint_count); +#endif diff --git a/include/system/whpx-common.h b/include/system/whpx-common.h new file mode 100644 index 0000000000..e549c7539c --- /dev/null +++ b/include/system/whpx-common.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef SYSTEM_WHPX_COMMON_H +#define SYSTEM_WHPX_COMMON_H + +struct AccelCPUState { + WHV_EMULATOR_HANDLE emulator; + bool window_registered; + bool interruptable; + bool ready_for_pic_interrupt; + uint64_t tpr; + uint64_t apic_base; + bool interruption_pending; + /* Must be the last field as it may have a tail */ + WHV_RUN_VP_EXIT_CONTEXT exit_ctx; +}; + +int whpx_first_vcpu_starting(CPUState *cpu); +int whpx_last_vcpu_stopping(CPUState *cpu); +void whpx_memory_init(void); +struct whpx_breakpoint *whpx_lookup_breakpoint_by_addr(uint64_t address); +#endif diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 106a352980..d1f8e49cb2 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -33,6 +33,8 @@ =20 #include "system/whpx-internal.h" #include "system/whpx-accel-ops.h" +#include "system/whpx-all.h" +#include "system/whpx-common.h" =20 #include #include @@ -232,28 +234,9 @@ typedef enum WhpxStepMode { WHPX_STEP_EXCLUSIVE, } WhpxStepMode; =20 -struct AccelCPUState { - WHV_EMULATOR_HANDLE emulator; - bool window_registered; - bool interruptable; - bool ready_for_pic_interrupt; - uint64_t tpr; - uint64_t apic_base; - bool interruption_pending; - - /* Must be the last field as it may have a tail */ - WHV_RUN_VP_EXIT_CONTEXT exit_ctx; -}; - -bool whpx_allowed; -static bool whp_dispatch_initialized; -static HMODULE hWinHvPlatform, hWinHvEmulation; static uint32_t max_vcpu_index; static WHV_PROCESSOR_XSAVE_FEATURES whpx_xsave_cap; =20 -struct whpx_state whpx_global; -struct WHPDispatch whp_dispatch; - static bool whpx_has_xsave(void) { return whpx_xsave_cap.XsaveSupport; @@ -379,7 +362,7 @@ static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8) return cr8 << 4; } =20 -static void whpx_set_registers(CPUState *cpu, int level) +void whpx_set_registers(CPUState *cpu, int level) { struct whpx_state *whpx =3D &whpx_global; AccelCPUState *vcpu =3D cpu->accel; @@ -594,7 +577,7 @@ static void whpx_get_xcrs(CPUState *cpu) cpu_env(cpu)->xcr0 =3D xcr0.Reg64; } =20 -static void whpx_get_registers(CPUState *cpu) +void whpx_get_registers(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; AccelCPUState *vcpu =3D cpu->accel; @@ -934,7 +917,7 @@ static int whpx_handle_portio(CPUState *cpu, * The 'exceptions' argument accepts a bitmask, e.g: * (1 << WHvX64ExceptionTypeDebugTrapOrFault) | (...) */ -static HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions) +HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions) { struct whpx_state *whpx =3D &whpx_global; WHV_PARTITION_PROPERTY prop =3D { 0, }; @@ -1084,23 +1067,6 @@ static HRESULT whpx_vcpu_configure_single_stepping(C= PUState *cpu, return S_OK; } =20 -/* Tries to find a breakpoint at the specified address. */ -static struct whpx_breakpoint *whpx_lookup_breakpoint_by_addr(uint64_t add= ress) -{ - struct whpx_state *whpx =3D &whpx_global; - int i; - - if (whpx->breakpoints.breakpoints) { - for (i =3D 0; i < whpx->breakpoints.breakpoints->used; i++) { - if (address =3D=3D whpx->breakpoints.breakpoints->data[i].addr= ess) { - return &whpx->breakpoints.breakpoints->data[i]; - } - } - } - - return NULL; -} - /* * Linux uses int3 (0xCC) during startup (see int3_selftest()) and for * debugging user-mode applications. Since the WHPX API does not offer @@ -1136,7 +1102,7 @@ static const uint8_t whpx_breakpoint_instruction =3D = 0xF1; * memory, but doesn't actually do it. The memory accessing is done in * whpx_apply_breakpoints(). */ -static void whpx_translate_cpu_breakpoints( +void whpx_translate_cpu_breakpoints( struct whpx_breakpoints *breakpoints, CPUState *cpu, int cpu_breakpoint_count) @@ -1230,7 +1196,7 @@ static void whpx_translate_cpu_breakpoints( * Passing resuming=3Dtrue will try to set all previously unset breakpoin= ts. * Passing resuming=3Dfalse will remove all inserted ones. */ -static void whpx_apply_breakpoints( +void whpx_apply_breakpoints( struct whpx_breakpoint_collection *breakpoints, CPUState *cpu, bool resuming) @@ -1306,93 +1272,6 @@ static void whpx_apply_breakpoints( } } =20 -/* - * This function is called when the a VCPU is about to start and no other - * VCPUs have been started so far. Since the VCPU start order could be - * arbitrary, it doesn't have to be VCPU#0. - * - * It is used to commit the breakpoints into memory, and configure WHPX - * to intercept debug exceptions. - * - * Note that whpx_set_exception_exit_bitmap() cannot be called if one or - * more VCPUs are already running, so this is the best place to do it. - */ -static int whpx_first_vcpu_starting(CPUState *cpu) -{ - struct whpx_state *whpx =3D &whpx_global; - HRESULT hr; - - g_assert(bql_locked()); - - if (!QTAILQ_EMPTY(&cpu->breakpoints) || - (whpx->breakpoints.breakpoints && - whpx->breakpoints.breakpoints->used)) { - CPUBreakpoint *bp; - int i =3D 0; - bool update_pending =3D false; - - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (i >=3D whpx->breakpoints.original_address_count || - bp->pc !=3D whpx->breakpoints.original_addresses[i]) { - update_pending =3D true; - } - - i++; - } - - if (i !=3D whpx->breakpoints.original_address_count) { - update_pending =3D true; - } - - if (update_pending) { - /* - * The CPU breakpoints have changed since the last call to - * whpx_translate_cpu_breakpoints(). WHPX breakpoints must - * now be recomputed. - */ - whpx_translate_cpu_breakpoints(&whpx->breakpoints, cpu, i); - } - - /* Actually insert the breakpoints into the memory. */ - whpx_apply_breakpoints(whpx->breakpoints.breakpoints, cpu, true); - } - - uint64_t exception_mask; - if (whpx->step_pending || - (whpx->breakpoints.breakpoints && - whpx->breakpoints.breakpoints->used)) { - /* - * We are either attempting to single-step one or more CPUs, or - * have one or more breakpoints enabled. Both require intercepting - * the WHvX64ExceptionTypeBreakpointTrap exception. - */ - - exception_mask =3D 1UL << WHvX64ExceptionTypeDebugTrapOrFault; - } else { - /* Let the guest handle all exceptions. */ - exception_mask =3D 0; - } - - hr =3D whpx_set_exception_exit_bitmap(exception_mask); - if (!SUCCEEDED(hr)) { - error_report("WHPX: Failed to update exception exit mask," - "hr=3D%08lx.", hr); - return 1; - } - - return 0; -} - -/* - * This function is called when the last VCPU has finished running. - * It is used to remove any previously set breakpoints from memory. - */ -static int whpx_last_vcpu_stopping(CPUState *cpu) -{ - whpx_apply_breakpoints(whpx_global.breakpoints.breakpoints, cpu, false= ); - return 0; -} - /* Returns the address of the next instruction that is about to be execute= d. */ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exit_context_valid) { @@ -1633,7 +1512,7 @@ static void whpx_vcpu_process_async_events(CPUState *= cpu) } } =20 -static int whpx_vcpu_run(CPUState *cpu) +int whpx_vcpu_run(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; @@ -2056,65 +1935,6 @@ static int whpx_vcpu_run(CPUState *cpu) return ret < 0; } =20 -static void do_whpx_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data a= rg) -{ - if (!cpu->vcpu_dirty) { - whpx_get_registers(cpu); - cpu->vcpu_dirty =3D true; - } -} - -static void do_whpx_cpu_synchronize_post_reset(CPUState *cpu, - run_on_cpu_data arg) -{ - whpx_set_registers(cpu, WHPX_SET_RESET_STATE); - cpu->vcpu_dirty =3D false; -} - -static void do_whpx_cpu_synchronize_post_init(CPUState *cpu, - run_on_cpu_data arg) -{ - whpx_set_registers(cpu, WHPX_SET_FULL_STATE); - cpu->vcpu_dirty =3D false; -} - -static void do_whpx_cpu_synchronize_pre_loadvm(CPUState *cpu, - run_on_cpu_data arg) -{ - cpu->vcpu_dirty =3D true; -} - -/* - * CPU support. - */ - -void whpx_cpu_synchronize_state(CPUState *cpu) -{ - if (!cpu->vcpu_dirty) { - run_on_cpu(cpu, do_whpx_cpu_synchronize_state, RUN_ON_CPU_NULL); - } -} - -void whpx_cpu_synchronize_post_reset(CPUState *cpu) -{ - run_on_cpu(cpu, do_whpx_cpu_synchronize_post_reset, RUN_ON_CPU_NULL); -} - -void whpx_cpu_synchronize_post_init(CPUState *cpu) -{ - run_on_cpu(cpu, do_whpx_cpu_synchronize_post_init, RUN_ON_CPU_NULL); -} - -void whpx_cpu_synchronize_pre_loadvm(CPUState *cpu) -{ - run_on_cpu(cpu, do_whpx_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL); -} - -static void whpx_pre_resume_vm(AccelState *as, bool step_pending) -{ - whpx_global.step_pending =3D step_pending; -} - /* * Vcpu support. */ @@ -2243,295 +2063,18 @@ error: return ret; } =20 -int whpx_vcpu_exec(CPUState *cpu) -{ - int ret; - int fatal; - - for (;;) { - if (cpu->exception_index >=3D EXCP_INTERRUPT) { - ret =3D cpu->exception_index; - cpu->exception_index =3D -1; - break; - } - - fatal =3D whpx_vcpu_run(cpu); - - if (fatal) { - error_report("WHPX: Failed to exec a virtual processor"); - abort(); - } - } - - return ret; -} - -void whpx_destroy_vcpu(CPUState *cpu) -{ - struct whpx_state *whpx =3D &whpx_global; - AccelCPUState *vcpu =3D cpu->accel; - - whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index= ); - whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator); - g_free(cpu->accel); -} - -void whpx_vcpu_kick(CPUState *cpu) -{ - struct whpx_state *whpx =3D &whpx_global; - whp_dispatch.WHvCancelRunVirtualProcessor( - whpx->partition, cpu->cpu_index, 0); -} - -/* - * Memory support. - */ - -static void whpx_update_mapping(hwaddr start_pa, ram_addr_t size, - void *host_va, int add, int rom, - const char *name) -{ - struct whpx_state *whpx =3D &whpx_global; - HRESULT hr; - - /* - if (add) { - printf("WHPX: ADD PA:%p Size:%p, Host:%p, %s, '%s'\n", - (void*)start_pa, (void*)size, host_va, - (rom ? "ROM" : "RAM"), name); - } else { - printf("WHPX: DEL PA:%p Size:%p, Host:%p, '%s'\n", - (void*)start_pa, (void*)size, host_va, name); - } - */ - - if (add) { - hr =3D whp_dispatch.WHvMapGpaRange(whpx->partition, - host_va, - start_pa, - size, - (WHvMapGpaRangeFlagRead | - WHvMapGpaRangeFlagExecute | - (rom ? 0 : WHvMapGpaRangeFlagWri= te))); - } else { - hr =3D whp_dispatch.WHvUnmapGpaRange(whpx->partition, - start_pa, - size); - } - - if (FAILED(hr)) { - error_report("WHPX: Failed to %s GPA range '%s' PA:%p, Size:%p byt= es," - " Host:%p, hr=3D%08lx", - (add ? "MAP" : "UNMAP"), name, - (void *)(uintptr_t)start_pa, (void *)size, host_va, h= r); - } -} - -static void whpx_process_section(MemoryRegionSection *section, int add) -{ - MemoryRegion *mr =3D section->mr; - hwaddr start_pa =3D section->offset_within_address_space; - ram_addr_t size =3D int128_get64(section->size); - unsigned int delta; - uint64_t host_va; - - if (!memory_region_is_ram(mr)) { - return; - } - - delta =3D qemu_real_host_page_size() - (start_pa & ~qemu_real_host_pag= e_mask()); - delta &=3D ~qemu_real_host_page_mask(); - if (delta > size) { - return; - } - start_pa +=3D delta; - size -=3D delta; - size &=3D qemu_real_host_page_mask(); - if (!size || (start_pa & ~qemu_real_host_page_mask())) { - return; - } - - host_va =3D (uintptr_t)memory_region_get_ram_ptr(mr) - + section->offset_within_region + delta; - - whpx_update_mapping(start_pa, size, (void *)(uintptr_t)host_va, add, - memory_region_is_rom(mr), mr->name); -} - -static void whpx_region_add(MemoryListener *listener, - MemoryRegionSection *section) -{ - memory_region_ref(section->mr); - whpx_process_section(section, 1); -} - -static void whpx_region_del(MemoryListener *listener, - MemoryRegionSection *section) -{ - whpx_process_section(section, 0); - memory_region_unref(section->mr); -} - -static void whpx_transaction_begin(MemoryListener *listener) -{ -} - -static void whpx_transaction_commit(MemoryListener *listener) -{ -} - -static void whpx_log_sync(MemoryListener *listener, - MemoryRegionSection *section) -{ - MemoryRegion *mr =3D section->mr; - - if (!memory_region_is_ram(mr)) { - return; - } - - memory_region_set_dirty(mr, 0, int128_get64(section->size)); -} - -static MemoryListener whpx_memory_listener =3D { - .name =3D "whpx", - .begin =3D whpx_transaction_begin, - .commit =3D whpx_transaction_commit, - .region_add =3D whpx_region_add, - .region_del =3D whpx_region_del, - .log_sync =3D whpx_log_sync, - .priority =3D MEMORY_LISTENER_PRIORITY_ACCEL, -}; - -static void whpx_memory_init(void) -{ - memory_listener_register(&whpx_memory_listener, &address_space_memory); -} - -/* - * Load the functions from the given library, using the given handle. If a - * handle is provided, it is used, otherwise the library is opened. The - * handle will be updated on return with the opened one. - */ -static bool load_whp_dispatch_fns(HMODULE *handle, - WHPFunctionList function_list) -{ - HMODULE hLib =3D *handle; - - #define WINHV_PLATFORM_DLL "WinHvPlatform.dll" - #define WINHV_EMULATION_DLL "WinHvEmulation.dll" - #define WHP_LOAD_FIELD_OPTIONAL(return_type, function_name, signature)= \ - whp_dispatch.function_name =3D \ - (function_name ## _t)GetProcAddress(hLib, #function_name); \ - - #define WHP_LOAD_FIELD(return_type, function_name, signature) \ - whp_dispatch.function_name =3D \ - (function_name ## _t)GetProcAddress(hLib, #function_name); \ - if (!whp_dispatch.function_name) { \ - error_report("Could not load function %s", #function_name); \ - goto error; \ - } \ - - #define WHP_LOAD_LIB(lib_name, handle_lib) \ - if (!handle_lib) { \ - handle_lib =3D LoadLibrary(lib_name); \ - if (!handle_lib) { \ - error_report("Could not load library %s.", lib_name); \ - goto error; \ - } \ - } \ - - switch (function_list) { - case WINHV_PLATFORM_FNS_DEFAULT: - WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib) - LIST_WINHVPLATFORM_FUNCTIONS(WHP_LOAD_FIELD) - break; - - case WINHV_EMULATION_FNS_DEFAULT: - WHP_LOAD_LIB(WINHV_EMULATION_DLL, hLib) - LIST_WINHVEMULATION_FUNCTIONS(WHP_LOAD_FIELD) - break; - - case WINHV_PLATFORM_FNS_SUPPLEMENTAL: - WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib) - LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL(WHP_LOAD_FIELD_OPTIONAL) - break; - } - - *handle =3D hLib; - return true; - -error: - if (hLib) { - FreeLibrary(hLib); - } - - return false; -} - -static void whpx_set_kernel_irqchip(Object *obj, Visitor *v, - const char *name, void *opaque, - Error **errp) -{ - struct whpx_state *whpx =3D &whpx_global; - OnOffSplit mode; - - if (!visit_type_OnOffSplit(v, name, &mode, errp)) { - return; - } - - switch (mode) { - case ON_OFF_SPLIT_ON: - whpx->kernel_irqchip_allowed =3D true; - whpx->kernel_irqchip_required =3D true; - break; - - case ON_OFF_SPLIT_OFF: - whpx->kernel_irqchip_allowed =3D false; - whpx->kernel_irqchip_required =3D false; - break; - - case ON_OFF_SPLIT_SPLIT: - error_setg(errp, "WHPX: split irqchip currently not supported"); - error_append_hint(errp, - "Try without kernel-irqchip or with kernel-irqchip=3Don|off"); - break; - - default: - /* - * The value was checked in visit_type_OnOffSplit() above. If - * we get here, then something is wrong in QEMU. - */ - abort(); - } -} - -static void whpx_cpu_instance_init(CPUState *cs) +void whpx_cpu_instance_init(CPUState *cs) { X86CPU *cpu =3D X86_CPU(cs); =20 host_cpu_instance_init(cpu); } =20 -static void whpx_cpu_accel_class_init(ObjectClass *oc, const void *data) -{ - AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); - - acc->cpu_instance_init =3D whpx_cpu_instance_init; -} - -static const TypeInfo whpx_cpu_accel_type =3D { - .name =3D ACCEL_CPU_NAME("whpx"), - - .parent =3D TYPE_ACCEL_CPU, - .class_init =3D whpx_cpu_accel_class_init, - .abstract =3D true, -}; - /* * Partition support */ =20 -static int whpx_accel_init(AccelState *as, MachineState *ms) +int whpx_accel_init(AccelState *as, MachineState *ms) { struct whpx_state *whpx; int ret; @@ -2714,77 +2257,3 @@ error: =20 return ret; } - -bool whpx_apic_in_platform(void) { - return whpx_global.apic_in_platform; -} - -static void whpx_accel_class_init(ObjectClass *oc, const void *data) -{ - AccelClass *ac =3D ACCEL_CLASS(oc); - ac->name =3D "WHPX"; - ac->init_machine =3D whpx_accel_init; - ac->pre_resume_vm =3D whpx_pre_resume_vm; - ac->allowed =3D &whpx_allowed; - - object_class_property_add(oc, "kernel-irqchip", "on|off|split", - NULL, whpx_set_kernel_irqchip, - NULL, NULL); - object_class_property_set_description(oc, "kernel-irqchip", - "Configure WHPX in-kernel irqchip"); -} - -static void whpx_accel_instance_init(Object *obj) -{ - struct whpx_state *whpx =3D &whpx_global; - - memset(whpx, 0, sizeof(struct whpx_state)); - /* Turn on kernel-irqchip, by default */ - whpx->kernel_irqchip_allowed =3D true; -} - -static const TypeInfo whpx_accel_type =3D { - .name =3D ACCEL_CLASS_NAME("whpx"), - .parent =3D TYPE_ACCEL, - .instance_init =3D whpx_accel_instance_init, - .class_init =3D whpx_accel_class_init, -}; - -static void whpx_type_init(void) -{ - type_register_static(&whpx_accel_type); - type_register_static(&whpx_cpu_accel_type); -} - -bool init_whp_dispatch(void) -{ - if (whp_dispatch_initialized) { - return true; - } - - if (!load_whp_dispatch_fns(&hWinHvPlatform, WINHV_PLATFORM_FNS_DEFAULT= )) { - goto error; - } - - if (!load_whp_dispatch_fns(&hWinHvEmulation, WINHV_EMULATION_FNS_DEFAU= LT)) { - goto error; - } - - assert(load_whp_dispatch_fns(&hWinHvPlatform, - WINHV_PLATFORM_FNS_SUPPLEMENTAL)); - whp_dispatch_initialized =3D true; - - return true; -error: - if (hWinHvPlatform) { - FreeLibrary(hWinHvPlatform); - } - - if (hWinHvEmulation) { - FreeLibrary(hWinHvEmulation); - } - - return false; -} - -type_init(whpx_type_init); --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1760633920; cv=none; d=zohomail.com; s=zohoarc; b=VGh2Kdz2HOkLCz2GWFK6phVYGeBF2212kbTV0Bna9Mn1GcFvuWc98YKYUtV0tqtXfnIVyq+jh+kJx9Flfb5YNWq+MtyoRhoLvkohVtsdNmb/yLxTVk777jX0se+fIUBbzE5spV3qR5Q4o9u8J1LZhR0Wjj+41T1hBvA/8amyiCA= ARC-Message-Signature: i=1; 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bh=hP9mipJJlzEp8BAG964JLQLLOKiV7YupjQ0pPg2yZ4w=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=P1YybNG4h/afzc31t5JKrk+Ro30CCIRUcIs9btvVmE8ZR1c5y32KZpiILT459adniFeouKiYH7dXd8YYjfIPIi/XIiR3OuzJESBKQhc6AVgzkjHY/sA0NKmfceZWUyDGrGIEWBuCE+YHfG7FNnBcFAOLcplXXCtx0VwoK/om+NIlyhms7s/T5v6Gya9MOzM5b+/i1eSYR/YiQROYCujRY3UF1yjbtZGybXl9KLvsYXJuLSnTm/BFRfqGqI09VCszNhxv6lCDqrkb3MNELJf3vaRNv9LCllR/5rDGjQukK0knDasaZGaaHeZAgbZnzIpwk8NaXAyxe9ttMnYrbs1SwA== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. Tsirkin" , Igor Mammedov , Paolo Bonzini , Yanan Wang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Shannon Zhao , kvm@vger.kernel.org, Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pedro Barbuda , Zhao Liu , Roman Bolshakov , Pierrick Bouvier Subject: [PATCH v7 08/24] whpx: ifdef out winhvemulation on non-x86_64 Date: Thu, 16 Oct 2025 18:55:04 +0200 Message-ID: <20251016165520.62532-9-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251016165520.62532-1-mohamed@unpredictable.fr> References: <20251016165520.62532-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: BIBHmbkbIcoNOF3xP2060srcDzIfcEwg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE2MDEyMiBTYWx0ZWRfX+L7V6sM0ly+w 0JVy2IliT9nDKb5ST+tMU8irr4TkOiwZGqlR7SRrXjEQPwXz+ZrCIhPh7HLp6rMknnQiEDbs8Sn OFNHqBwk0Y2ulNThG64aErKieb6iyutzM0GZ55d6HG77sf/NtK2DkmDJ0BIlMI+vlr0KaI12fsD M1kuSTJ3PDHUjEPPCx410R5p7tZp/ZvS0zcrEJty/rLoGXHnTMzhFRxTdS30BFYs2PPH+PSMJKq PhZ38OJj1bgWRa0Tj4pW3ag9BbMW85NlH12AEfdpQH2sxngWd1J4Xq0eeFsIyqT3O7D0OeNUs= X-Proofpoint-GUID: BIBHmbkbIcoNOF3xP2060srcDzIfcEwg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1030 phishscore=0 suspectscore=0 adultscore=0 mlxlogscore=766 bulkscore=0 malwarescore=0 spamscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510160122 X-JNJ: AAAAAAABxmB7T2oLXTufbol1toOlvGlC9GSprD2ZN0jDB/s5IZC4wz1mhFk8RlixS4r49vz1l0ZdrcPjD32GZGVsvptHG4t1eqr+HeHxNefqi+REcXV9gzvsqwvmQtjxPZDeHyQh012OjhZwDraQZ96fhHIR0X6TEEze3JxWKB1D1AxyCO2qJB2VBC0h1kbUsYOW3TVDya+gE96lmlzxvnxyBz5UQcGddTDfk59eEPITZVxpBVyXqxEFxQYuBF+fqURCmgCtOzeNgDfHdO9f5ayVruvTjYfUh15YC8JuPHKpHJTOMbiJnorGzsPuwYZynW0rMLfJHLHsyMeVw2ae+jt45ty0/CIpwwn4SZxfwnZq42gEdbjDMee8WBvIlh2fQm6KkhNOXVRjuc3Qu3NtbQ2cTQHu93aQCzEEF6QSUcucF+f6MnQg34rFC05qf+afnjQxBdFfV/4ZC2MOJg8WhM90NC5iv/zFdX6AGotiY2KoFiDkj+TFgnHp6VbgLNOOc++mEukSsJq2WWFoSZbQ3+lEu/V9yszAAmdzs0HejmqDF3OiSuE0tLj/9kQ5/LimXN2v5GZrVU1x7WrToTQk9eQHr819kGMRtXcFNDczfOsUBKT/Kv1ARmpuwQq/yNSuAodYbx8I+tLzc69AzhZ466vGEVl1D3gOkbwW8e/66D22+Wow2pkMTMXC4flbq4tRuFNAAYlOPECSxqYGyxOFnXIkJp1nRu848H3hWeAVnQoBcSNG1/bpnQxA7cnnAhO6IPkQCzNox2FILqwJokXDOWu5KaOvCn2KeTWh57/7p86cuFWD9psdE3XnUgsPBFr80ysVwYCmFFkBIoTASF5VTGTGDv7ckEQoh6c32JpacmKAdNY1Mdzfxr7hFtaoqBQkye7gwqziDm11aqJFnV5H8mB+TMy+ug== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.76.63; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760633925190158500 Content-Type: text/plain; charset="utf-8" winhvemulation is x86_64 only. In the future, we might want to get rid of winhvemulation usage entirely. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- accel/whpx/whpx-common.c | 14 ++++++++++++-- include/system/whpx-common.h | 2 ++ include/system/whpx-internal.h | 7 ++++++- 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index 66c9238586..95664a1df7 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -41,7 +41,9 @@ bool whpx_allowed; static bool whp_dispatch_initialized; static HMODULE hWinHvPlatform; +#ifdef __x86_64__ static HMODULE hWinHvEmulation; +#endif =20 struct whpx_state whpx_global; struct WHPDispatch whp_dispatch; @@ -236,8 +238,10 @@ void whpx_destroy_vcpu(CPUState *cpu) struct whpx_state *whpx =3D &whpx_global; =20 whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index= ); +#ifdef __x86_64__ AccelCPUState *vcpu =3D cpu->accel; whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator); +#endif g_free(cpu->accel); } =20 @@ -412,8 +416,12 @@ static bool load_whp_dispatch_fns(HMODULE *handle, LIST_WINHVPLATFORM_FUNCTIONS(WHP_LOAD_FIELD) break; case WINHV_EMULATION_FNS_DEFAULT: +#ifdef __x86_64__ WHP_LOAD_LIB(WINHV_EMULATION_DLL, hLib) LIST_WINHVEMULATION_FUNCTIONS(WHP_LOAD_FIELD) +#else + g_assert_not_reached(); +#endif break; case WINHV_PLATFORM_FNS_SUPPLEMENTAL: WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib) @@ -539,11 +547,11 @@ bool init_whp_dispatch(void) if (!load_whp_dispatch_fns(&hWinHvPlatform, WINHV_PLATFORM_FNS_DEFAULT= )) { goto error; } - +#ifdef __x86_64__ if (!load_whp_dispatch_fns(&hWinHvEmulation, WINHV_EMULATION_FNS_DEFAU= LT)) { goto error; } - +#endif assert(load_whp_dispatch_fns(&hWinHvPlatform, WINHV_PLATFORM_FNS_SUPPLEMENTAL)); whp_dispatch_initialized =3D true; @@ -553,9 +561,11 @@ error: if (hWinHvPlatform) { FreeLibrary(hWinHvPlatform); } +#ifdef __x86_64__ if (hWinHvEmulation) { FreeLibrary(hWinHvEmulation); } +#endif return false; } =20 diff --git a/include/system/whpx-common.h b/include/system/whpx-common.h index e549c7539c..7a7c607e0a 100644 --- a/include/system/whpx-common.h +++ b/include/system/whpx-common.h @@ -3,7 +3,9 @@ #define SYSTEM_WHPX_COMMON_H =20 struct AccelCPUState { +#ifdef __x86_64__ WHV_EMULATOR_HANDLE emulator; +#endif bool window_registered; bool interruptable; bool ready_for_pic_interrupt; diff --git a/include/system/whpx-internal.h b/include/system/whpx-internal.h index e61375d554..e57d2c8526 100644 --- a/include/system/whpx-internal.h +++ b/include/system/whpx-internal.h @@ -4,8 +4,9 @@ =20 #include #include +#ifdef __x86_64__ #include - +#endif typedef enum WhpxBreakpointState { WHPX_BP_CLEARED =3D 0, WHPX_BP_SET_PENDING, @@ -98,12 +99,16 @@ void whpx_apic_get(DeviceState *s); =20 /* Define function typedef */ LIST_WINHVPLATFORM_FUNCTIONS(WHP_DEFINE_TYPE) +#ifdef __x86_64__ LIST_WINHVEMULATION_FUNCTIONS(WHP_DEFINE_TYPE) +#endif LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL(WHP_DEFINE_TYPE) =20 struct WHPDispatch { LIST_WINHVPLATFORM_FUNCTIONS(WHP_DECLARE_MEMBER) +#ifdef __x86_64__ LIST_WINHVEMULATION_FUNCTIONS(WHP_DECLARE_MEMBER) +#endif LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL(WHP_DECLARE_MEMBER) }; =20 --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 16 Oct 2025 12:58:04 -0400 Received: from outbound.st.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPS id 1262618004AB; Thu, 16 Oct 2025 16:57:08 +0000 (UTC) Received: from localhost.localdomain (unknown [17.42.251.67]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPSA id BB51318024C4; Thu, 16 Oct 2025 16:55:53 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=zNv66cYWOjcoM4iD8mPZ0d3N5D4+2q07Wwy2NtrQNPs=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=Hd3sta3GaVRNz92RcL4nm9rqJ7Ho/uokvK2HVmFI7XrQ+i+twA2Shvatl7OHG3r3hSCulm82tsbpUgzNf0k3XrCVI74zyE+3LGg5v6ZP/aX7cgmg19jh35aYmNNGo8hcF5ZHGnpGH1ZkcKHRJiqm6BBg8rwsZbsmpxH+g6BJM/sapn7qKxTttxzzkdG3sKg9hemOHJ6mWgQSBI4rLe6WGyJemIzPz5oywseV1+3slQcDMRZJwefe7HPAPQZ1z7OPgee1BLmLG7foTw91r/f84GZKLMRvItJjBLbpCwFOlce0e7WcHTR0FsVNp9cPmSZLNDoQhXjqxmAs47dYGu8Hig== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. Tsirkin" , Igor Mammedov , Paolo Bonzini , Yanan Wang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Shannon Zhao , kvm@vger.kernel.org, Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pedro Barbuda , Zhao Liu , Roman Bolshakov , Pierrick Bouvier Subject: [PATCH v7 09/24] whpx: common: add WHPX_INTERCEPT_DEBUG_TRAPS define Date: Thu, 16 Oct 2025 18:55:05 +0200 Message-ID: <20251016165520.62532-10-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251016165520.62532-1-mohamed@unpredictable.fr> References: <20251016165520.62532-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE2MDEyMiBTYWx0ZWRfX/Se7HJt5ynqq roJse5cXmIDGwIRZMaWA6H1I5UTUJqK+cKTCvbOJGuujitBOmO+06nJXJRBTtJ/GPuX3o8VSY0I o1QhBe1fQMrTUSoJ95DOq7V8kGvVITsd+wpV287dm2aTTKjdp/zwYz/kYWe5Bwv/KG8YZJFdXdL n7M0XiF8UL6PNIknHnlRqQWWQvt5Ii6cMk1UEELm43EorttynVXy7PtcmKJTCJrBusi3pfUKnlH ma6xq+181+P77RAzK729cfyK1jCZYw/8z/FDUJHxs8Od8/FZWM4V2Qkm9q/pQkK51G0ozdk4g= X-Proofpoint-GUID: IhWrKx3FAqHIMTyMmBewRi40WIQl1-Xm X-Proofpoint-ORIG-GUID: IhWrKx3FAqHIMTyMmBewRi40WIQl1-Xm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 adultscore=0 clxscore=1030 phishscore=0 malwarescore=0 mlxscore=0 spamscore=0 bulkscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510160122 X-JNJ: AAAAAAABKQbKhGNJsKWtHaM0uPJhTwSnS1oTiWx3YNJODY4fPbxw6apQMVH9n6rgjIZYhRnDazA9zfU0QuI7MvErSkMGrX4AHqmAipWgO4R4KIoC/D8OIPWD8OGAaMmElA0pK9Jo0Y+LLxYCu67FV5xpToXLT65oO3GMCZvLhJGF4MOehOPqRJgV18RmyAW8vQkx6MKMSqZfDfVWHrRJcL22VCTtPFOcxIuLNJGfQ9kHBQJTqCay1ISlMgSDJz+OJveXzNQmmO94XV47yDocXtPmg9yMCf8mQ9dyvFJsuNzGDhUT+3LCENHQbwvBIQiVbCn6NHq7L7S3BgajNKbHXJv366j2irUA4cddJ9f0eyxsG/DMd+CEE3sbCRr9DXpqUwaBNklT42IHI/2WwxEUhYUklzLj9gzt1VnwKPLGKS/5HZwgHplfbD1N8r344/R2v351zRSxraQ3m+9ZHVeWGTaKA309Lh+FcwYJUvcbrc4dO+9HDsRHU4crxTWW9t2/UZ/f8AH5zPZUwvTMicfRw0+gwG2d8wNrNr30dn54hEhOG+Hzjhs03uVFekIjtAB4pLgfJ/QNjcg9xBPYBfT0+hlt6qx1GBzFUjHOnYk7MBfTTrGWSDW+pwXgP+Wdt8pAjF1t7OO2P0JICIoYJuIrGQN2awX6w4xxZ+fWRMHqgSYmmLvZlXL25634Aglv8dAzN6mefl9xnqOxoohX30P4rc9X2ZMCgQAdBjZSdGKvYlgG2LFtjj3UJWt2VTbA1zoVJ7o1Q/aXFE45C1eXoyEzANGCrzMF6jOCByHPZo8fMzKMv7+XsXUeP2/+SUnohPJpFFzTwmnd/xCJ9PoejLIMt6JI/oUUsH/yZ44vJwB/btZULfN6a8jw/hQ7d6ZTcvzJt28OCukPIASSKpWl61jcLF2uZs5fnPXqSsISg5FGwyhj Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.76.103; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760634078992154100 Content-Type: text/plain; charset="utf-8" As of why: WHPX on arm64 doesn't have debug trap support as of today. Keep the exception bitmap interface for now - despite that being entirely u= navailable on arm64 too. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- accel/whpx/whpx-common.c | 2 +- include/system/whpx-common.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index 95664a1df7..c0ff6cacb8 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -123,7 +123,7 @@ int whpx_first_vcpu_starting(CPUState *cpu) * have one or more breakpoints enabled. Both require intercepting * the WHvX64ExceptionTypeBreakpointTrap exception. */ - exception_mask =3D 1UL << WHvX64ExceptionTypeDebugTrapOrFault; + exception_mask =3D 1UL << WHPX_INTERCEPT_DEBUG_TRAPS; } else { /* Let the guest handle all exceptions. */ exception_mask =3D 0; diff --git a/include/system/whpx-common.h b/include/system/whpx-common.h index 7a7c607e0a..73b9f7c119 100644 --- a/include/system/whpx-common.h +++ b/include/system/whpx-common.h @@ -20,4 +20,7 @@ int whpx_first_vcpu_starting(CPUState *cpu); int whpx_last_vcpu_stopping(CPUState *cpu); void whpx_memory_init(void); struct whpx_breakpoint *whpx_lookup_breakpoint_by_addr(uint64_t address); + +/* On x64: same as WHvX64ExceptionTypeDebugTrapOrFault */ +#define WHPX_INTERCEPT_DEBUG_TRAPS 1 #endif --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1760634273; cv=none; d=zohomail.com; s=zohoarc; b=ESwFoGUD0Q/0f6Y6NClbjsGq6S/+3ZnLhrIvQ8BqwwoSYJhHwueRWA4enAW8kS9ieNVWflsUuQm5bmt0yBtklWFU3qmxm/w1h7+L4hHvGe0z/0Rs5nVSt8axqLRyMaKbC7RknCGR+iVg7zHKvcRfJjIKM9yq5HTSypqpfXZjgwU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760634273; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=h7u/XWsux0pmMZnA7+paR99F4ZhLVNBkIu/tmCtAH0I=; b=aUGcMJXJ92EqgknQ+wi+jnCcY+nQbnCy5nVCn5ZHYoMMYR7Nv6SfDAE77Yo27Zm+bonYayHWkRuhLret/ZpWkjP66sy4gC0qEHchhqY10rWdYiviD1/6ctzfoD9HRk0KhwmHYqmDKyqD3L21HP7EGFGEYVhrq6ZAZKAuQYnqsyk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760634273728686.3587074830513; Thu, 16 Oct 2025 10:04:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v9RIA-0000y2-Qh; Thu, 16 Oct 2025 12:57:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RI7-0000wx-SA for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:57:27 -0400 Received: from p-east2-cluster1-host4-snip4-10.eps.apple.com ([57.103.76.23] helo=outbound.st.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RHu-0001aX-IR for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:57:27 -0400 Received: from outbound.st.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPS id 2606918001FD; Thu, 16 Oct 2025 16:57:09 +0000 (UTC) Received: from localhost.localdomain (unknown [17.42.251.67]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPSA id 30FF318024C9; Thu, 16 Oct 2025 16:55:57 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=h7u/XWsux0pmMZnA7+paR99F4ZhLVNBkIu/tmCtAH0I=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=GxHSKKP5KfdhVWTmVMHw3jnFn1icmcpaUD4AkHd5J4a/5DL9r4L4f7UqPpyROS6voss6jzEIbNLr/Z1S/wob2rlIVqnftqdWIK/YF253oAH+5y2TyY8qLbzJDzA0az/PlRPHnfLWGzgc0nFUA9FFFAq+Q+3ESaSCSVQpln9Nlyu1yvW9KMr/7ImhKfaUfBe/OQBmf7mgzliJbRUANOsg86/VuWq15j0EkAC6Yq3ani2z3WjA9T+IO7mW1wjYEWNoDzviZaPspiHum8Ofbo6b4wxAS7NfCrwrs3/JHRkKQcj+40qhY003yY5yzT9oChSJTBlVirxWT1QShfcAypatbQ== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. Tsirkin" , Igor Mammedov , Paolo Bonzini , Yanan Wang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Shannon Zhao , kvm@vger.kernel.org, Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pedro Barbuda , Zhao Liu , Roman Bolshakov , Pierrick Bouvier Subject: [PATCH v7 10/24] hw, target, accel: whpx: change apic_in_platform to kernel_irqchip Date: Thu, 16 Oct 2025 18:55:06 +0200 Message-ID: <20251016165520.62532-11-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251016165520.62532-1-mohamed@unpredictable.fr> References: <20251016165520.62532-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: bNNSvIik7Ue097Ccdwp2dYK7CeAQcsAP X-Proofpoint-GUID: bNNSvIik7Ue097Ccdwp2dYK7CeAQcsAP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE2MDEyMyBTYWx0ZWRfX5sEZ/CG/5J6E ioC8LiV6uVceX5Gs06uMbiGwECs5U0DH6EPFxtnThYEq6eGFblYra5oAVonjF1chQqNY0EhPZoz 2DFv75iZSk9S7c4U1Sma46YXOYAcLEaoCDk9gGJSedSAsLtlUW0FJ3H6Ex3lE4o9/IL3cJOIdp9 j7w6cXOwT2bnsmCDUpkL0aGCq+BwNfRlSDEQffe/b9RoXasU+wqLwRhbZE72QKZlPGqzJalPb+l ZfNgkLbhdPP/7XFTgMe2GhAQGqPRHLYB4TDue4ocn+tivlEvOEl5HP/ecsTQn2wCf+iwNUau4= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 clxscore=1030 bulkscore=0 malwarescore=0 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510160123 X-JNJ: AAAAAAABg3kEB3Drvjcchx/D8pXJbOWXPSRCp646G7z8pQnooXrmfVOmUjllUzjsUxqaX1z9E15KgZfqmInD4lip4/veg19NR5Rg8tLuzQuJ2Qvr2NYPhhucgn0fQZxGSAYZZuJhhaC7LgpK2Jk6wSgTuA2n+Gw5Apy5vZkaD8meOyvWoQT5524si4n6DYUHQro5EKFIIca9FJHnwgss9RW5EKLr4o0VGw9OP8ybz7Kl7dejQ/JLAO/52rClr8msJQNPw8u4UiirEihHtsyuWuh6LnyAL18RuFkI5zVTOhrRr4izOahdFrcRUIb3QAKMqoTKriXb9eLRkUZqeQLAXtJhnwhHeqoeHPv51OixeWvRArTUp6KV7sGjwrHqrTZxUKjNUIMUZZNceA6Ixl3zZZcF4N00V2hIPWlJ3LIW7WzP56hRFApFLKJnJXV2ba+7qm0s6E/Qp5uqDhuRM0gjZcBVo5hRyH6yfU37m+1qKU0yx1w0+YOgXF+GDTflI/RmOe4tsxi7YP4UsyDouZktzsJ1OHFpE0/D6RDzOERBOFvYrb1w5ugB+I4FYffX4JjDauJwJVcy52KVx08XIAmWCAmpbdeGRp8BoyDKCCXJw2AOm3I1BSyxecYJJZASWAkBymw8rr0UWEy5fo6GZ75zvc7DbQf1WwRSIt/CDbar8/wEse7v52bKf2DBfpotU0xvHgeRxdEz4qAqOw17haPwUfSpFHghtmjyd9nX5nV7YyBSENFGqK5hhCagb3dYTHvOWPwn2ZspHb1rV/6Nyu69vw97jwY+lTnOWqtCfqq1mS4hptxe76bzVe6JitX9QLF5d9Hiptc1TEH1xLJuEJjoloMiv8iee7b2VAWb+UuE4Gqu7X5TWy0MYwj+lgtboND3Mp2cGciEabZ+wuap4pL0bA2Au4fdfjQNW9Q8knpT Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.76.23; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760634275306154100 Content-Type: text/plain; charset="utf-8" Change terminology to match the KVM one, as APIC is x86-specific. Signed-off-by: Mohamed Mediouni Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/whpx/whpx-accel-ops.c | 2 +- accel/whpx/whpx-common.c | 4 ++-- hw/i386/x86-cpu.c | 4 ++-- include/system/whpx-internal.h | 2 +- include/system/whpx.h | 4 ++-- target/i386/cpu-apic.c | 2 +- target/i386/whpx/whpx-all.c | 14 +++++++------- 7 files changed, 16 insertions(+), 16 deletions(-) diff --git a/accel/whpx/whpx-accel-ops.c b/accel/whpx/whpx-accel-ops.c index c84a25c273..50fadea0fd 100644 --- a/accel/whpx/whpx-accel-ops.c +++ b/accel/whpx/whpx-accel-ops.c @@ -78,7 +78,7 @@ static void whpx_kick_vcpu_thread(CPUState *cpu) =20 static bool whpx_vcpu_thread_is_idle(CPUState *cpu) { - return !whpx_apic_in_platform(); + return !whpx_irqchip_in_kernel(); } =20 static void whpx_accel_ops_class_init(ObjectClass *oc, const void *data) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index c0ff6cacb8..18d93225c1 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -496,9 +496,9 @@ static const TypeInfo whpx_cpu_accel_type =3D { * Partition support */ =20 -bool whpx_apic_in_platform(void) +bool whpx_irqchip_in_kernel(void) { - return whpx_global.apic_in_platform; + return whpx_global.kernel_irqchip; } =20 static void whpx_accel_class_init(ObjectClass *oc, const void *data) diff --git a/hw/i386/x86-cpu.c b/hw/i386/x86-cpu.c index c876e6709e..778607e7ca 100644 --- a/hw/i386/x86-cpu.c +++ b/hw/i386/x86-cpu.c @@ -45,7 +45,7 @@ static void pic_irq_request(void *opaque, int irq, int le= vel) =20 trace_x86_pic_interrupt(irq, level); if (cpu_is_apic_enabled(cpu->apic_state) && !kvm_irqchip_in_kernel() && - !whpx_apic_in_platform()) { + !whpx_irqchip_in_kernel()) { CPU_FOREACH(cs) { cpu =3D X86_CPU(cs); if (apic_accept_pic_intr(cpu->apic_state)) { @@ -71,7 +71,7 @@ int cpu_get_pic_interrupt(CPUX86State *env) X86CPU *cpu =3D env_archcpu(env); int intno; =20 - if (!kvm_irqchip_in_kernel() && !whpx_apic_in_platform()) { + if (!kvm_irqchip_in_kernel() && !whpx_irqchip_in_kernel()) { intno =3D apic_get_interrupt(cpu->apic_state); if (intno >=3D 0) { return intno; diff --git a/include/system/whpx-internal.h b/include/system/whpx-internal.h index e57d2c8526..366bc525a3 100644 --- a/include/system/whpx-internal.h +++ b/include/system/whpx-internal.h @@ -42,7 +42,7 @@ struct whpx_state { =20 bool kernel_irqchip_allowed; bool kernel_irqchip_required; - bool apic_in_platform; + bool kernel_irqchip; }; =20 extern struct whpx_state whpx_global; diff --git a/include/system/whpx.h b/include/system/whpx.h index 00f6a3e523..98fe045ba1 100644 --- a/include/system/whpx.h +++ b/include/system/whpx.h @@ -26,10 +26,10 @@ #ifdef CONFIG_WHPX_IS_POSSIBLE extern bool whpx_allowed; #define whpx_enabled() (whpx_allowed) -bool whpx_apic_in_platform(void); +bool whpx_irqchip_in_kernel(void); #else /* !CONFIG_WHPX_IS_POSSIBLE */ #define whpx_enabled() 0 -#define whpx_apic_in_platform() (0) +#define whpx_irqchip_in_kernel() (0) #endif /* !CONFIG_WHPX_IS_POSSIBLE */ =20 #endif /* QEMU_WHPX_H */ diff --git a/target/i386/cpu-apic.c b/target/i386/cpu-apic.c index 242a05fdbe..d4d371a616 100644 --- a/target/i386/cpu-apic.c +++ b/target/i386/cpu-apic.c @@ -32,7 +32,7 @@ APICCommonClass *apic_get_class(Error **errp) apic_type =3D "kvm-apic"; } else if (xen_enabled()) { apic_type =3D "xen-apic"; - } else if (whpx_apic_in_platform()) { + } else if (whpx_irqchip_in_kernel()) { apic_type =3D "whpx-apic"; } =20 diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index d1f8e49cb2..feabbec427 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -607,7 +607,7 @@ void whpx_get_registers(CPUState *cpu) hr); } =20 - if (whpx_apic_in_platform()) { + if (whpx_irqchip_in_kernel()) { /* * Fetch the TPR value from the emulated APIC. It may get overwrit= ten * below with the value from CR8 returned by @@ -749,7 +749,7 @@ void whpx_get_registers(CPUState *cpu) =20 assert(idx =3D=3D RTL_NUMBER_OF(whpx_register_names)); =20 - if (whpx_apic_in_platform()) { + if (whpx_irqchip_in_kernel()) { whpx_apic_get(x86_cpu->apic_state); } =20 @@ -1379,7 +1379,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) } =20 /* Get pending hard interruption or replay one that was overwritten */ - if (!whpx_apic_in_platform()) { + if (!whpx_irqchip_in_kernel()) { if (!vcpu->interruption_pending && vcpu->interruptable && (env->eflags & IF_MASK)) { assert(!new_int.InterruptionPending); @@ -1552,7 +1552,7 @@ int whpx_vcpu_run(CPUState *cpu) =20 if (exclusive_step_mode =3D=3D WHPX_STEP_NONE) { whpx_vcpu_process_async_events(cpu); - if (cpu->halted && !whpx_apic_in_platform()) { + if (cpu->halted && !whpx_irqchip_in_kernel()) { cpu->exception_index =3D EXCP_HLT; qatomic_set(&cpu->exit_request, false); return 0; @@ -1641,7 +1641,7 @@ int whpx_vcpu_run(CPUState *cpu) break; =20 case WHvRunVpExitReasonX64ApicEoi: - assert(whpx_apic_in_platform()); + assert(whpx_irqchip_in_kernel()); ioapic_eoi_broadcast(vcpu->exit_ctx.ApicEoi.InterruptVector); break; =20 @@ -2186,7 +2186,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } } else { - whpx->apic_in_platform =3D true; + whpx->kernel_irqchip =3D true; } } =20 @@ -2195,7 +2195,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) prop.ExtendedVmExits.X64MsrExit =3D 1; prop.ExtendedVmExits.X64CpuidExit =3D 1; prop.ExtendedVmExits.ExceptionExit =3D 1; - if (whpx_apic_in_platform()) { + if (whpx_irqchip_in_kernel()) { prop.ExtendedVmExits.X64ApicInitSipiExitTrap =3D 1; } =20 --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; 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Tsirkin" , Igor Mammedov , Paolo Bonzini , Yanan Wang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Shannon Zhao , kvm@vger.kernel.org, Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pedro Barbuda , Zhao Liu , Roman Bolshakov , Pierrick Bouvier Subject: [PATCH v7 11/24] whpx: interrupt controller support Date: Thu, 16 Oct 2025 18:55:07 +0200 Message-ID: <20251016165520.62532-12-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251016165520.62532-1-mohamed@unpredictable.fr> References: <20251016165520.62532-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: ij9Jl4SlC-7INuxTJ1mUi_3iDZUqeDH6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE2MDEyMyBTYWx0ZWRfX/QrxNaeeQTdy fHlUdk0wH9Aj+aun2W3mhu3hs+LGFUgNGeKvGAgWfEnVCzkZy1MfMtMYISG/BPwdWPo5KUNaotE 3z9sTdnvqD+oT0x1sC5YNT8jqcPBX0BcQI3AUPIYVnd+cc8vo5RrXVeUveMaCPDMCCQPlswjfEZ 6Q3XGCESNN1kFqQw86zK+mBQ5dF1CRg9v+4s90UzxeN8KQaBi7zNXCVlQZgQehQtVJJvX70E1DN 91//cLF/x3xpB7F7ryDPIRKnc6FPLj0p5xqVN4wSwBfKKA8toOqK5hs68313H4cLloDYob7Vw= X-Proofpoint-ORIG-GUID: ij9Jl4SlC-7INuxTJ1mUi_3iDZUqeDH6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 bulkscore=0 clxscore=1030 mlxlogscore=999 malwarescore=0 adultscore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510160123 X-JNJ: AAAAAAABY7+4GDdIDw5GQUEgFW2BnkK/l9SsyT4vf/BiQONJKlv48y5DY/rta7xhC+rlUXZWptZUmucCnLQI6ycerXL89EU67pA69LqhdBG/wEkSogh2sV4Wf8+2+dz6z6o5bhLlnqu5aHHoDsP/QHWnBdyl35gBzVww7TYyvl4Eo3/LSes8TKu//nJfcFS92+EIrWlrLWpKiJNxMG95PoMxEw4IzAQ0sTt2VMyfCPBn4J9HNj1zYJ8Ven92utiuMGsyQS3iWDSgFV+CV8sIZ5yPBx8V6bIB5ueuJStr/hqEYUDR2QOHxcx8Yz5LpljqcQVJpHbA+WeI2Pd066ZXezm14VpNgWM6kF4w3H9i9xBFHlusyldlyn5okR23jWu9R7SUosPxPTSBfMcR90Lz+9Csmz4rjBZpmIxf/A+7A4CaFh+QcSO4CWFMSAGtiLq8DTgLCS9C+xc30vTw0uAx1OsNdtHOW/nGreYcRapRUJxzatk32tc6k0wFMForIqp8OdjBFK6FbQ9EsAn5QSIS4xJ8MXocb5/pv2/pP9NuBYrCvk5ffwnX0PfazT+ZhPG0xEP3yrnTWivqLf+hQ1P0sTa4UVHM1baSqw3t/6FVWMPZAfmVbOr6KBnxiJgs0h46ea39TbHr/VHtsXpPfLXDln0NqFevFUGwR450dklDpwIrhyyyvXQEjAZTXkMWZt1PFzGiQ+hOWE5o7zP39yDVqmo7hv4Qid3VMAu5FIt7SmAWCnm+nxgAKFOz90HUEj7KcDdMUwdrCzwQpQxNbTh5PZ1kn57N9NRrgx5r64uSyuc6qzGxQwQgqNcslhVioXt5Y/csFFyx6Jt+6Xy1wDiHCMuQWd0SFNQHrwkjvaCerqTxjPDyItlZChlWjBLet9w/A17AhxRtjvAusdvxt2paOKY1jBFI9Jn9UQPA8Q== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.76.123; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760634198669158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- hw/arm/virt.c | 3 + hw/intc/arm_gicv3_common.c | 3 + hw/intc/arm_gicv3_whpx.c | 239 +++++++++++++++++++++++++++++ hw/intc/meson.build | 1 + include/hw/intc/arm_gicv3_common.h | 3 + 5 files changed, 249 insertions(+) create mode 100644 hw/intc/arm_gicv3_whpx.c diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 61d7bab803..9121eb37eb 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -47,6 +47,7 @@ #include "system/tcg.h" #include "system/kvm.h" #include "system/hvf.h" +#include "system/whpx.h" #include "system/qtest.h" #include "system/system.h" #include "hw/loader.h" @@ -2105,6 +2106,8 @@ static void finalize_gic_version(VirtMachineState *vm= s) /* KVM w/o kernel irqchip can only deal with GICv2 */ gics_supported |=3D VIRT_GIC_VERSION_2_MASK; accel_name =3D "KVM with kernel-irqchip=3Doff"; + } else if (whpx_enabled()) { + gics_supported |=3D VIRT_GIC_VERSION_3_MASK; } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { gics_supported |=3D VIRT_GIC_VERSION_2_MASK; if (module_object_class_by_name("arm-gicv3")) { diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 2d0df6da86..1fd1e329e8 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -32,6 +32,7 @@ #include "gicv3_internal.h" #include "hw/arm/linux-boot-if.h" #include "system/kvm.h" +#include "system/whpx.h" =20 =20 static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs) @@ -663,6 +664,8 @@ const char *gicv3_class_name(void) { if (kvm_irqchip_in_kernel()) { return "kvm-arm-gicv3"; + } else if (whpx_enabled()) { + return TYPE_WHPX_GICV3; } else { if (kvm_enabled()) { error_report("Userspace GICv3 is not supported with KVM"); diff --git a/hw/intc/arm_gicv3_whpx.c b/hw/intc/arm_gicv3_whpx.c new file mode 100644 index 0000000000..88a05e5901 --- /dev/null +++ b/hw/intc/arm_gicv3_whpx.c @@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ARM Generic Interrupt Controller using HVF platform support + * + * Copyright (c) 2025 Mohamed Mediouni + * Based on vGICv3 KVM code by Pavel Fedin + * + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/intc/arm_gicv3_common.h" +#include "qemu/error-report.h" +#include "qemu/module.h" +#include "system/runstate.h" +#include "system/whpx.h" +#include "system/whpx-internal.h" +#include "gicv3_internal.h" +#include "vgic_common.h" +#include "qom/object.h" +#include "target/arm/cpregs.h" + +#include "hw/arm/bsa.h" +#include +#include +#include + +struct WHPXARMGICv3Class { + ARMGICv3CommonClass parent_class; + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +typedef struct WHPXARMGICv3Class WHPXARMGICv3Class; + +/* This is reusing the GICv3State typedef from ARM_GICV3_ITS_COMMON */ +DECLARE_OBJ_CHECKERS(GICv3State, WHPXARMGICv3Class, + WHPX_GICV3, TYPE_WHPX_GICV3); + +/* TODO: Implement GIC state save-restore */ +static void whpx_gicv3_check(GICv3State *s) +{ +} + +static void whpx_gicv3_put(GICv3State *s) +{ + whpx_gicv3_check(s); +} + +static void whpx_gicv3_get(GICv3State *s) +{ +} + +static void whpx_gicv3_set_irq(void *opaque, int irq, int level) +{ + struct whpx_state *whpx =3D &whpx_global; + + GICv3State *s =3D (GICv3State *)opaque; + if (irq > s->num_irq) { + return; + } + WHV_INTERRUPT_TYPE interrupt_type =3D WHvArm64InterruptTypeFixed; + WHV_INTERRUPT_CONTROL interrupt_control =3D { + interrupt_type =3D WHvArm64InterruptTypeFixed, + .RequestedVector =3D GIC_INTERNAL + irq, .InterruptControl.Asserted = =3D level}; + + whp_dispatch.WHvRequestInterrupt(whpx->partition, &interrupt_control, + sizeof(interrupt_control)); +} + +static void whpx_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + GICv3State *s; + GICv3CPUState *c; + + c =3D (GICv3CPUState *)env->gicv3state; + s =3D c->gic; + + c->icc_pmr_el1 =3D 0; + /* + * Architecturally the reset value of the ICC_BPR registers + * is UNKNOWN. We set them all to 0 here; when the kernel + * uses these values to program the ICH_VMCR_EL2 fields that + * determine the guest-visible ICC_BPR register values, the + * hardware's "writing a value less than the minimum sets + * the field to the minimum value" behaviour will result in + * them effectively resetting to the correct minimum value + * for the host GIC. + */ + c->icc_bpr[GICV3_G0] =3D 0; + c->icc_bpr[GICV3_G1] =3D 0; + c->icc_bpr[GICV3_G1NS] =3D 0; + + c->icc_sre_el1 =3D 0x7; + memset(c->icc_apr, 0, sizeof(c->icc_apr)); + memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen)); + + if (s->migration_blocker) { + return; + } + + c->icc_ctlr_el1[GICV3_S] =3D c->icc_ctlr_el1[GICV3_NS]; +} + +static void whpx_gicv3_reset_hold(Object *obj, ResetType type) +{ + GICv3State *s =3D ARM_GICV3_COMMON(obj); + WHPXARMGICv3Class *kgc =3D WHPX_GICV3_GET_CLASS(s); + + if (kgc->parent_phases.hold) { + kgc->parent_phases.hold(obj, type); + } + + whpx_gicv3_put(s); +} + + +/* + * CPU interface registers of GIC needs to be reset on CPU reset. + * For the calling arm_gicv3_icc_reset() on CPU reset, we register + * below ARMCPRegInfo. As we reset the whole cpu interface under single + * register reset, we define only one register of CPU interface instead + * of defining all the registers. + */ +static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { + { .name =3D "ICC_CTLR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 12, .opc2 =3D 4, + /* + * If ARM_CP_NOP is used, resetfn is not called, + * So ARM_CP_NO_RAW is appropriate type. + */ + .type =3D ARM_CP_NO_RAW, + .access =3D PL1_RW, + .readfn =3D arm_cp_read_zero, + .writefn =3D arm_cp_write_ignore, + /* + * We hang the whole cpu interface reset routine off here + * rather than parcelling it out into one little function + * per register + */ + .resetfn =3D whpx_gicv3_icc_reset, + }, +}; + +static void whpx_set_reg(CPUState *cpu, WHV_REGISTER_NAME reg, WHV_REGISTE= R_VALUE val) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters(whpx->partition, c= pu->cpu_index, + ®, 1, &val); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set register %08x, hr=3D%08lx", reg,= hr); + } +} + +static void whpx_gicv3_realize(DeviceState *dev, Error **errp) +{ + GICv3State *s =3D WHPX_GICV3(dev); + WHPXARMGICv3Class *kgc =3D WHPX_GICV3_GET_CLASS(s); + Error *local_err =3D NULL; + int i; + + kgc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + if (s->revision !=3D 3) { + error_setg(errp, "unsupported GIC revision %d for platform GIC", + s->revision); + } + + if (s->security_extn) { + error_setg(errp, "the platform vGICv3 does not implement the " + "security extensions"); + return; + } + + if (s->nmi_support) { + error_setg(errp, "NMI is not supported with the platform GIC"); + return; + } + + if (s->nb_redist_regions > 1) { + error_setg(errp, "Multiple VGICv3 redistributor regions are not " + "supported by WHPX"); + error_append_hint(errp, "A maximum of %d VCPUs can be used", + s->redist_region_count[0]); + return; + } + + gicv3_init_irqs_and_mmio(s, whpx_gicv3_set_irq, NULL); + + for (i =3D 0; i < s->num_cpu; i++) { + CPUState *cpu_state =3D qemu_get_cpu(i); + ARMCPU *cpu =3D ARM_CPU(cpu_state); + WHV_REGISTER_VALUE val =3D {.Reg64 =3D 0x080A0000 + (GICV3_REDIST_= SIZE * i)}; + whpx_set_reg(cpu_state, WHvArm64RegisterGicrBaseGpa, val); + define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); + } + + if (s->maint_irq) { + error_setg(errp, "Nested virtualisation not currently supported by= WHPX."); + return; + } +} + +static void whpx_gicv3_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + ARMGICv3CommonClass *agcc =3D ARM_GICV3_COMMON_CLASS(klass); + WHPXARMGICv3Class *kgc =3D WHPX_GICV3_CLASS(klass); + + agcc->pre_save =3D whpx_gicv3_get; + agcc->post_load =3D whpx_gicv3_put; + + device_class_set_parent_realize(dc, whpx_gicv3_realize, + &kgc->parent_realize); + resettable_class_set_parent_phases(rc, NULL, whpx_gicv3_reset_hold, NU= LL, + &kgc->parent_phases); +} + +static const TypeInfo whpx_arm_gicv3_info =3D { + .name =3D TYPE_WHPX_GICV3, + .parent =3D TYPE_ARM_GICV3_COMMON, + .instance_size =3D sizeof(GICv3State), + .class_init =3D whpx_gicv3_class_init, + .class_size =3D sizeof(WHPXARMGICv3Class), +}; + +static void whpx_gicv3_register_types(void) +{ + type_register_static(&whpx_arm_gicv3_info); +} + +type_init(whpx_gicv3_register_types) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index faae20b93d..96742df090 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -41,6 +41,7 @@ specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic= .c', 'apic_common.c')) arm_common_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_= common.c')) arm_common_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files('arm_gicv3_cpui= f.c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'= )) +specific_ss.add(when: ['CONFIG_WHPX', 'TARGET_AARCH64'], if_true: files('a= rm_gicv3_whpx.c')) specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: f= iles('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) arm_common_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c')) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 38aa1961c5..5f4af811f6 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -310,6 +310,9 @@ typedef struct ARMGICv3CommonClass ARMGICv3CommonClass; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.76.15; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760634212768158501 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- accel/whpx/whpx-common.c | 1 + target/arm/meson.build | 1 + target/arm/whpx/meson.build | 3 + target/arm/whpx/whpx-all.c | 848 ++++++++++++++++++++++++++++++++++++ 4 files changed, 853 insertions(+) create mode 100644 target/arm/whpx/meson.build create mode 100644 target/arm/whpx/whpx-all.c diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index 18d93225c1..c69792e638 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -16,6 +16,7 @@ #include "gdbstub/helpers.h" #include "qemu/accel.h" #include "accel/accel-ops.h" +#include "system/memory.h" #include "system/whpx.h" #include "system/cpus.h" #include "system/runstate.h" diff --git a/target/arm/meson.build b/target/arm/meson.build index 3df7e03654..61277a627c 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -59,6 +59,7 @@ arm_common_system_ss.add(files( )) =20 subdir('hvf') +subdir('whpx') =20 if 'CONFIG_TCG' in config_all_accel subdir('tcg') diff --git a/target/arm/whpx/meson.build b/target/arm/whpx/meson.build new file mode 100644 index 0000000000..1de2ef0283 --- /dev/null +++ b/target/arm/whpx/meson.build @@ -0,0 +1,3 @@ +arm_system_ss.add(when: 'CONFIG_WHPX', if_true: files( + 'whpx-all.c', +)) diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c new file mode 100644 index 0000000000..7ef900a5ca --- /dev/null +++ b/target/arm/whpx/whpx-all.c @@ -0,0 +1,848 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU Windows Hypervisor Platform accelerator (WHPX) + * + * Copyright (c) 2025 Mohamed Mediouni + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "system/address-spaces.h" +#include "system/ioport.h" +#include "gdbstub/helpers.h" +#include "qemu/accel.h" +#include "accel/accel-ops.h" +#include "system/whpx.h" +#include "system/cpus.h" +#include "system/runstate.h" +#include "qemu/main-loop.h" +#include "hw/boards.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "qapi/qapi-types-common.h" +#include "qapi/qapi-visit-common.h" +#include "migration/blocker.h" +#include "accel/accel-cpu-target.h" +#include + +#include "syndrome.h" +#include "cpu.h" +#include "cpregs.h" +#include "internals.h" + +#include "system/whpx-internal.h" +#include "system/whpx-accel-ops.h" +#include "system/whpx-all.h" +#include "system/whpx-common.h" +#include "hw/arm/bsa.h" +#include "arm-powerctl.h" + +#include +#include + +struct whpx_reg_match { + WHV_REGISTER_NAME reg; + uint64_t offset; +}; + +static const struct whpx_reg_match whpx_reg_match[] =3D { + { WHvArm64RegisterX0, offsetof(CPUARMState, xregs[0]) }, + { WHvArm64RegisterX1, offsetof(CPUARMState, xregs[1]) }, + { WHvArm64RegisterX2, offsetof(CPUARMState, xregs[2]) }, + { WHvArm64RegisterX3, offsetof(CPUARMState, xregs[3]) }, + { WHvArm64RegisterX4, offsetof(CPUARMState, xregs[4]) }, + { WHvArm64RegisterX5, offsetof(CPUARMState, xregs[5]) }, + { WHvArm64RegisterX6, offsetof(CPUARMState, xregs[6]) }, + { WHvArm64RegisterX7, offsetof(CPUARMState, xregs[7]) }, + { WHvArm64RegisterX8, offsetof(CPUARMState, xregs[8]) }, + { WHvArm64RegisterX9, offsetof(CPUARMState, xregs[9]) }, + { WHvArm64RegisterX10, offsetof(CPUARMState, xregs[10]) }, + { WHvArm64RegisterX11, offsetof(CPUARMState, xregs[11]) }, + { WHvArm64RegisterX12, offsetof(CPUARMState, xregs[12]) }, + { WHvArm64RegisterX13, offsetof(CPUARMState, xregs[13]) }, + { WHvArm64RegisterX14, offsetof(CPUARMState, xregs[14]) }, + { WHvArm64RegisterX15, offsetof(CPUARMState, xregs[15]) }, + { WHvArm64RegisterX16, offsetof(CPUARMState, xregs[16]) }, + { WHvArm64RegisterX17, offsetof(CPUARMState, xregs[17]) }, + { WHvArm64RegisterX18, offsetof(CPUARMState, xregs[18]) }, + { WHvArm64RegisterX19, offsetof(CPUARMState, xregs[19]) }, + { WHvArm64RegisterX20, offsetof(CPUARMState, xregs[20]) }, + { WHvArm64RegisterX21, offsetof(CPUARMState, xregs[21]) }, + { WHvArm64RegisterX22, offsetof(CPUARMState, xregs[22]) }, + { WHvArm64RegisterX23, offsetof(CPUARMState, xregs[23]) }, + { WHvArm64RegisterX24, offsetof(CPUARMState, xregs[24]) }, + { WHvArm64RegisterX25, offsetof(CPUARMState, xregs[25]) }, + { WHvArm64RegisterX26, offsetof(CPUARMState, xregs[26]) }, + { WHvArm64RegisterX27, offsetof(CPUARMState, xregs[27]) }, + { WHvArm64RegisterX28, offsetof(CPUARMState, xregs[28]) }, + { WHvArm64RegisterFp, offsetof(CPUARMState, xregs[29]) }, + { WHvArm64RegisterLr, offsetof(CPUARMState, xregs[30]) }, + { WHvArm64RegisterPc, offsetof(CPUARMState, pc) }, +}; + +static const struct whpx_reg_match whpx_fpreg_match[] =3D { + { WHvArm64RegisterQ0, offsetof(CPUARMState, vfp.zregs[0]) }, + { WHvArm64RegisterQ1, offsetof(CPUARMState, vfp.zregs[1]) }, + { WHvArm64RegisterQ2, offsetof(CPUARMState, vfp.zregs[2]) }, + { WHvArm64RegisterQ3, offsetof(CPUARMState, vfp.zregs[3]) }, + { WHvArm64RegisterQ4, offsetof(CPUARMState, vfp.zregs[4]) }, + { WHvArm64RegisterQ5, offsetof(CPUARMState, vfp.zregs[5]) }, + { WHvArm64RegisterQ6, offsetof(CPUARMState, vfp.zregs[6]) }, + { WHvArm64RegisterQ7, offsetof(CPUARMState, vfp.zregs[7]) }, + { WHvArm64RegisterQ8, offsetof(CPUARMState, vfp.zregs[8]) }, + { WHvArm64RegisterQ9, offsetof(CPUARMState, vfp.zregs[9]) }, + { WHvArm64RegisterQ10, offsetof(CPUARMState, vfp.zregs[10]) }, + { WHvArm64RegisterQ11, offsetof(CPUARMState, vfp.zregs[11]) }, + { WHvArm64RegisterQ12, offsetof(CPUARMState, vfp.zregs[12]) }, + { WHvArm64RegisterQ13, offsetof(CPUARMState, vfp.zregs[13]) }, + { WHvArm64RegisterQ14, offsetof(CPUARMState, vfp.zregs[14]) }, + { WHvArm64RegisterQ15, offsetof(CPUARMState, vfp.zregs[15]) }, + { WHvArm64RegisterQ16, offsetof(CPUARMState, vfp.zregs[16]) }, + { WHvArm64RegisterQ17, offsetof(CPUARMState, vfp.zregs[17]) }, + { WHvArm64RegisterQ18, offsetof(CPUARMState, vfp.zregs[18]) }, + { WHvArm64RegisterQ19, offsetof(CPUARMState, vfp.zregs[19]) }, + { WHvArm64RegisterQ20, offsetof(CPUARMState, vfp.zregs[20]) }, + { WHvArm64RegisterQ21, offsetof(CPUARMState, vfp.zregs[21]) }, + { WHvArm64RegisterQ22, offsetof(CPUARMState, vfp.zregs[22]) }, + { WHvArm64RegisterQ23, offsetof(CPUARMState, vfp.zregs[23]) }, + { WHvArm64RegisterQ24, offsetof(CPUARMState, vfp.zregs[24]) }, + { WHvArm64RegisterQ25, offsetof(CPUARMState, vfp.zregs[25]) }, + { WHvArm64RegisterQ26, offsetof(CPUARMState, vfp.zregs[26]) }, + { WHvArm64RegisterQ27, offsetof(CPUARMState, vfp.zregs[27]) }, + { WHvArm64RegisterQ28, offsetof(CPUARMState, vfp.zregs[28]) }, + { WHvArm64RegisterQ29, offsetof(CPUARMState, vfp.zregs[29]) }, + { WHvArm64RegisterQ30, offsetof(CPUARMState, vfp.zregs[30]) }, + { WHvArm64RegisterQ31, offsetof(CPUARMState, vfp.zregs[31]) }, +}; + +#define WHPX_SYSREG(crn, crm, op0, op1, op2) \ + ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) + +struct whpx_sreg_match { + WHV_REGISTER_NAME reg; + uint32_t key; + bool global; + uint32_t cp_idx; +}; + +static struct whpx_sreg_match whpx_sreg_match[] =3D { + { WHvArm64RegisterDbgbvr0El1, WHPX_SYSREG(0, 0, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr0El1, WHPX_SYSREG(0, 0, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr0El1, WHPX_SYSREG(0, 0, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr0El1, WHPX_SYSREG(0, 0, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr0El1, WHPX_SYSREG(0, 1, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr0El1, WHPX_SYSREG(0, 1, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr0El1, WHPX_SYSREG(0, 1, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr0El1, WHPX_SYSREG(0, 1, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr2El1, WHPX_SYSREG(0, 2, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr2El1, WHPX_SYSREG(0, 2, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr2El1, WHPX_SYSREG(0, 2, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr2El1, WHPX_SYSREG(0, 2, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr3El1, WHPX_SYSREG(0, 3, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr3El1, WHPX_SYSREG(0, 3, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr3El1, WHPX_SYSREG(0, 3, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr3El1, WHPX_SYSREG(0, 3, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr4El1, WHPX_SYSREG(0, 4, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr4El1, WHPX_SYSREG(0, 4, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr4El1, WHPX_SYSREG(0, 4, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr4El1, WHPX_SYSREG(0, 4, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr5El1, WHPX_SYSREG(0, 5, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr5El1, WHPX_SYSREG(0, 5, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr5El1, WHPX_SYSREG(0, 5, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr5El1, WHPX_SYSREG(0, 5, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr6El1, WHPX_SYSREG(0, 6, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr6El1, WHPX_SYSREG(0, 6, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr6El1, WHPX_SYSREG(0, 6, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr6El1, WHPX_SYSREG(0, 6, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr7El1, WHPX_SYSREG(0, 7, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr7El1, WHPX_SYSREG(0, 7, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr7El1, WHPX_SYSREG(0, 7, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr7El1, WHPX_SYSREG(0, 7, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr8El1, WHPX_SYSREG(0, 8, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr8El1, WHPX_SYSREG(0, 8, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr8El1, WHPX_SYSREG(0, 8, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr8El1, WHPX_SYSREG(0, 8, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr9El1, WHPX_SYSREG(0, 9, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr9El1, WHPX_SYSREG(0, 9, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr9El1, WHPX_SYSREG(0, 9, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr9El1, WHPX_SYSREG(0, 9, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr10El1, WHPX_SYSREG(0, 10, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr10El1, WHPX_SYSREG(0, 10, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr10El1, WHPX_SYSREG(0, 10, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr10El1, WHPX_SYSREG(0, 10, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr11El1, WHPX_SYSREG(0, 11, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr11El1, WHPX_SYSREG(0, 11, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr11El1, WHPX_SYSREG(0, 11, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr11El1, WHPX_SYSREG(0, 11, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr12El1, WHPX_SYSREG(0, 12, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr12El1, WHPX_SYSREG(0, 12, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr12El1, WHPX_SYSREG(0, 12, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr12El1, WHPX_SYSREG(0, 12, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr13El1, WHPX_SYSREG(0, 13, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr13El1, WHPX_SYSREG(0, 13, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr13El1, WHPX_SYSREG(0, 13, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr13El1, WHPX_SYSREG(0, 13, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr14El1, WHPX_SYSREG(0, 14, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr14El1, WHPX_SYSREG(0, 14, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr14El1, WHPX_SYSREG(0, 14, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr14El1, WHPX_SYSREG(0, 14, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr15El1, WHPX_SYSREG(0, 15, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr15El1, WHPX_SYSREG(0, 15, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr15El1, WHPX_SYSREG(0, 15, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr15El1, WHPX_SYSREG(0, 15, 2, 0, 7) }, +#ifdef SYNC_NO_RAW_REGS + /* + * The registers below are manually synced on init because they are + * marked as NO_RAW. We still list them to make number space sync easi= er. + */ + { WHvArm64RegisterMidrEl1, WHPX_SYSREG(0, 0, 3, 0, 0) }, + { WHvArm64RegisterMpidrEl1, WHPX_SYSREG(0, 0, 3, 0, 5) }, + { WHvArm64RegisterIdPfr0El1, WHPX_SYSREG(0, 4, 3, 0, 0) }, +#endif + { WHvArm64RegisterIdAa64Pfr1El1, WHPX_SYSREG(0, 4, 3, 0, 1), true }, + { WHvArm64RegisterIdAa64Dfr0El1, WHPX_SYSREG(0, 5, 3, 0, 0), true }, + { WHvArm64RegisterIdAa64Dfr1El1, WHPX_SYSREG(0, 5, 3, 0, 1), true }, + { WHvArm64RegisterIdAa64Isar0El1, WHPX_SYSREG(0, 6, 3, 0, 0), true }, + { WHvArm64RegisterIdAa64Isar1El1, WHPX_SYSREG(0, 6, 3, 0, 1), true }, +#ifdef SYNC_NO_MMFR0 + /* We keep the hardware MMFR0 around. HW limits are there anyway */ + { WHvArm64RegisterIdAa64Mmfr0El1, WHPX_SYSREG(0, 7, 3, 0, 0) }, +#endif + { WHvArm64RegisterIdAa64Mmfr1El1, WHPX_SYSREG(0, 7, 3, 0, 1), true }, + { WHvArm64RegisterIdAa64Mmfr2El1, WHPX_SYSREG(0, 7, 3, 0, 2), true }, + { WHvArm64RegisterIdAa64Mmfr3El1, WHPX_SYSREG(0, 7, 3, 0, 3), true }, + + { WHvArm64RegisterMdscrEl1, WHPX_SYSREG(0, 2, 2, 0, 2) }, + { WHvArm64RegisterSctlrEl1, WHPX_SYSREG(1, 0, 3, 0, 0) }, + { WHvArm64RegisterCpacrEl1, WHPX_SYSREG(1, 0, 3, 0, 2) }, + { WHvArm64RegisterTtbr0El1, WHPX_SYSREG(2, 0, 3, 0, 0) }, + { WHvArm64RegisterTtbr1El1, WHPX_SYSREG(2, 0, 3, 0, 1) }, + { WHvArm64RegisterTcrEl1, WHPX_SYSREG(2, 0, 3, 0, 2) }, + + { WHvArm64RegisterApiAKeyLoEl1, WHPX_SYSREG(2, 1, 3, 0, 0) }, + { WHvArm64RegisterApiAKeyHiEl1, WHPX_SYSREG(2, 1, 3, 0, 1) }, + { WHvArm64RegisterApiBKeyLoEl1, WHPX_SYSREG(2, 1, 3, 0, 2) }, + { WHvArm64RegisterApiBKeyHiEl1, WHPX_SYSREG(2, 1, 3, 0, 3) }, + { WHvArm64RegisterApdAKeyLoEl1, WHPX_SYSREG(2, 2, 3, 0, 0) }, + { WHvArm64RegisterApdAKeyHiEl1, WHPX_SYSREG(2, 2, 3, 0, 1) }, + { WHvArm64RegisterApdBKeyLoEl1, WHPX_SYSREG(2, 2, 3, 0, 2) }, + { WHvArm64RegisterApdBKeyHiEl1, WHPX_SYSREG(2, 2, 3, 0, 3) }, + { WHvArm64RegisterApgAKeyLoEl1, WHPX_SYSREG(2, 3, 3, 0, 0) }, + { WHvArm64RegisterApgAKeyHiEl1, WHPX_SYSREG(2, 3, 3, 0, 1) }, + + { WHvArm64RegisterSpsrEl1, WHPX_SYSREG(4, 0, 3, 0, 0) }, + { WHvArm64RegisterElrEl1, WHPX_SYSREG(4, 0, 3, 0, 1) }, + { WHvArm64RegisterSpEl1, WHPX_SYSREG(4, 1, 3, 0, 0) }, + { WHvArm64RegisterEsrEl1, WHPX_SYSREG(5, 2, 3, 0, 0) }, + { WHvArm64RegisterFarEl1, WHPX_SYSREG(6, 0, 3, 0, 0) }, + { WHvArm64RegisterParEl1, WHPX_SYSREG(7, 4, 3, 0, 0) }, + { WHvArm64RegisterMairEl1, WHPX_SYSREG(10, 2, 3, 0, 0) }, + { WHvArm64RegisterVbarEl1, WHPX_SYSREG(12, 0, 3, 0, 0) }, + { WHvArm64RegisterContextidrEl1, WHPX_SYSREG(13, 0, 3, 0, 1) }, + { WHvArm64RegisterTpidrEl1, WHPX_SYSREG(13, 0, 3, 0, 4) }, + { WHvArm64RegisterCntkctlEl1, WHPX_SYSREG(14, 1, 3, 0, 0) }, + { WHvArm64RegisterCsselrEl1, WHPX_SYSREG(0, 0, 3, 2, 0) }, + { WHvArm64RegisterTpidrEl0, WHPX_SYSREG(13, 0, 3, 3, 2) }, + { WHvArm64RegisterTpidrroEl0, WHPX_SYSREG(13, 0, 3, 3, 3) }, + { WHvArm64RegisterCntvCtlEl0, WHPX_SYSREG(14, 3, 3, 3, 1) }, + { WHvArm64RegisterCntvCvalEl0, WHPX_SYSREG(14, 3, 3, 3, 2) }, + { WHvArm64RegisterSpEl1, WHPX_SYSREG(4, 1, 3, 4, 0) }, +}; + +static void flush_cpu_state(CPUState *cpu) +{ + if (cpu->vcpu_dirty) { + whpx_set_registers(cpu, WHPX_SET_RUNTIME_STATE); + cpu->vcpu_dirty =3D false; + } +} + +HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions) +{ + if (exceptions !=3D 0) { + return E_NOTIMPL; + } + return ERROR_SUCCESS; +} +void whpx_apply_breakpoints( +struct whpx_breakpoint_collection *breakpoints, + CPUState *cpu, + bool resuming) +{ + +} +void whpx_translate_cpu_breakpoints( + struct whpx_breakpoints *breakpoints, + CPUState *cpu, + int cpu_breakpoint_count) +{ + +} + +static void whpx_get_reg(CPUState *cpu, WHV_REGISTER_NAME reg, WHV_REGISTE= R_VALUE* val) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + + flush_cpu_state(cpu); + + hr =3D whp_dispatch.WHvGetVirtualProcessorRegisters(whpx->partition, c= pu->cpu_index, + ®, 1, val); + + if (FAILED(hr)) { + error_report("WHPX: Failed to get register %08x, hr=3D%08lx", reg,= hr); + } +} + +static void whpx_set_reg(CPUState *cpu, WHV_REGISTER_NAME reg, WHV_REGISTE= R_VALUE val) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters(whpx->partition, c= pu->cpu_index, + ®, 1, &val); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set register %08x, hr=3D%08lx", reg,= hr); + } +} + +static void whpx_get_global_reg(WHV_REGISTER_NAME reg, WHV_REGISTER_VALUE = *val) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + + hr =3D whp_dispatch.WHvGetVirtualProcessorRegisters(whpx->partition, W= HV_ANY_VP, + ®, 1, val); + + if (FAILED(hr)) { + error_report("WHPX: Failed to get register %08x, hr=3D%08lx", reg,= hr); + } +} + +static void whpx_set_global_reg(WHV_REGISTER_NAME reg, WHV_REGISTER_VALUE = val) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters(whpx->partition, W= HV_ANY_VP, + ®, 1, &val); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set register %08x, hr=3D%08lx", reg,= hr); + } +} + +static uint64_t whpx_get_gp_reg(CPUState *cpu, int rt) +{ + assert(rt <=3D 31); + if (rt =3D=3D 31) { + return 0; + } + WHV_REGISTER_NAME reg =3D WHvArm64RegisterX0 + rt; + WHV_REGISTER_VALUE val; + whpx_get_reg(cpu, reg, &val); + + return val.Reg64; +} + +static void whpx_set_gp_reg(CPUState *cpu, int rt, uint64_t val) +{ + assert(rt < 31); + WHV_REGISTER_NAME reg =3D WHvArm64RegisterX0 + rt; + WHV_REGISTER_VALUE reg_val =3D {.Reg64 =3D val}; + + whpx_set_reg(cpu, reg, reg_val); +} + +static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx) +{ + uint64_t syndrome =3D ctx->Syndrome; + + bool isv =3D syndrome & ARM_EL_ISV; + bool iswrite =3D (syndrome >> 6) & 1; + bool sse =3D (syndrome >> 21) & 1; + uint32_t sas =3D (syndrome >> 22) & 3; + uint32_t len =3D 1 << sas; + uint32_t srt =3D (syndrome >> 16) & 0x1f; + uint32_t cm =3D (syndrome >> 8) & 0x1; + uint64_t val =3D 0; + + assert(!cm); + assert(isv); + + if (iswrite) { + val =3D whpx_get_gp_reg(cpu, srt); + address_space_write(&address_space_memory, + ctx->Gpa, + MEMTXATTRS_UNSPECIFIED, &val, len); + } else { + address_space_read(&address_space_memory, + ctx->Gpa, + MEMTXATTRS_UNSPECIFIED, &val, len); + if (sse) { + val =3D sextract64(val, 0, len * 8); + } + whpx_set_gp_reg(cpu, srt, val); + } + + return 0; +} + +static void whpx_psci_cpu_off(ARMCPU *arm_cpu) +{ + int32_t ret =3D arm_set_cpu_off(arm_cpu_mp_affinity(arm_cpu)); + assert(ret =3D=3D QEMU_ARM_POWERCTL_RET_SUCCESS); +} + +int whpx_vcpu_run(CPUState *cpu) +{ + HRESULT hr; + struct whpx_state *whpx =3D &whpx_global; + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + AccelCPUState *vcpu =3D cpu->accel; + int ret; + + + g_assert(bql_locked()); + + if (whpx->running_cpus++ =3D=3D 0) { + ret =3D whpx_first_vcpu_starting(cpu); + if (ret !=3D 0) { + return ret; + } + } + + bql_unlock(); + + + cpu_exec_start(cpu); + do { + bool advance_pc =3D false; + if (cpu->vcpu_dirty) { + whpx_set_registers(cpu, WHPX_SET_RUNTIME_STATE); + cpu->vcpu_dirty =3D false; + } + + if (qatomic_read(&cpu->exit_request)) { + whpx_vcpu_kick(cpu); + } + + hr =3D whp_dispatch.WHvRunVirtualProcessor( + whpx->partition, cpu->cpu_index, + &vcpu->exit_ctx, sizeof(vcpu->exit_ctx)); + + if (FAILED(hr)) { + error_report("WHPX: Failed to exec a virtual processor," + " hr=3D%08lx", hr); + ret =3D -1; + break; + } + + switch (vcpu->exit_ctx.ExitReason) { + case WHvRunVpExitReasonGpaIntercept: + case WHvRunVpExitReasonUnmappedGpa: + advance_pc =3D true; + + if (vcpu->exit_ctx.MemoryAccess.Syndrome >> 8 & 0x1) { + error_report("WHPX: cached access to unmapped memory" + "Pc =3D 0x%llx Gva =3D 0x%llx Gpa =3D 0x%llx", + vcpu->exit_ctx.MemoryAccess.Header.Pc, + vcpu->exit_ctx.MemoryAccess.Gpa, + vcpu->exit_ctx.MemoryAccess.Gva); + break; + } + + ret =3D whpx_handle_mmio(cpu, &vcpu->exit_ctx.MemoryAccess); + break; + case WHvRunVpExitReasonCanceled: + cpu->exception_index =3D EXCP_INTERRUPT; + ret =3D 1; + break; + case WHvRunVpExitReasonArm64Reset: + switch (vcpu->exit_ctx.Arm64Reset.ResetType) { + case WHvArm64ResetTypePowerOff: + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN= ); + break; + case WHvArm64ResetTypeReboot: + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + break; + default: + g_assert_not_reached(); + } + bql_lock(); + if (arm_cpu->power_state !=3D PSCI_OFF) { + whpx_psci_cpu_off(arm_cpu); + } + bql_unlock(); + break; + case WHvRunVpExitReasonNone: + case WHvRunVpExitReasonUnrecoverableException: + case WHvRunVpExitReasonInvalidVpRegisterValue: + case WHvRunVpExitReasonUnsupportedFeature: + default: + error_report("WHPX: Unexpected VP exit code 0x%08x", + vcpu->exit_ctx.ExitReason); + whpx_get_registers(cpu); + bql_lock(); + qemu_system_guest_panicked(cpu_get_crash_info(cpu)); + bql_unlock(); + break; + } + if (advance_pc) { + WHV_REGISTER_VALUE pc; + + flush_cpu_state(cpu); + pc.Reg64 =3D vcpu->exit_ctx.MemoryAccess.Header.Pc + 4; + whpx_set_reg(cpu, WHvArm64RegisterPc, pc); + } + } while (!ret); + + cpu_exec_end(cpu); + + bql_lock(); + current_cpu =3D cpu; + + if (--whpx->running_cpus =3D=3D 0) { + whpx_last_vcpu_stopping(cpu); + } + + qatomic_set(&cpu->exit_request, false); + + return ret < 0; +} + +static void clean_whv_register_value(WHV_REGISTER_VALUE *val) +{ + memset(val, 0, sizeof(WHV_REGISTER_VALUE)); +} + +void whpx_get_registers(CPUState *cpu) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + WHV_REGISTER_VALUE val; + int i; + + for (i =3D 0; i < ARRAY_SIZE(whpx_reg_match); i++) { + whpx_get_reg(cpu, whpx_reg_match[i].reg, &val); + *(uint64_t *)((void *)env + whpx_reg_match[i].offset) =3D val.Reg6= 4; + } + + for (i =3D 0; i < ARRAY_SIZE(whpx_fpreg_match); i++) { + whpx_get_reg(cpu, whpx_reg_match[i].reg, &val); + memcpy((void *)env + whpx_fpreg_match[i].offset, &val, sizeof(val.= Reg128)); + } + + whpx_get_reg(cpu, WHvArm64RegisterPc, &val); + env->pc =3D val.Reg64; + + whpx_get_reg(cpu, WHvArm64RegisterFpcr, &val); + vfp_set_fpcr(env, val.Reg32); + + whpx_get_reg(cpu, WHvArm64RegisterFpsr, &val); + vfp_set_fpsr(env, val.Reg32); + + whpx_get_reg(cpu, WHvArm64RegisterPstate, &val); + pstate_write(env, val.Reg32); + + for (i =3D 0; i < ARRAY_SIZE(whpx_sreg_match); i++) { + if (whpx_sreg_match[i].global =3D=3D true) { + continue; + } + if (whpx_sreg_match[i].cp_idx =3D=3D -1) { + continue; + } + + whpx_get_reg(cpu, whpx_sreg_match[i].reg, &val); + + arm_cpu->cpreg_values[whpx_sreg_match[i].cp_idx] =3D val.Reg64; + } + + /* WHP disallows us from reading global regs as a vCPU */ + for (i =3D 0; i < ARRAY_SIZE(whpx_sreg_match); i++) { + if (whpx_sreg_match[i].global =3D=3D false) { + continue; + } + if (whpx_sreg_match[i].cp_idx =3D=3D -1) { + continue; + } + + whpx_get_global_reg(whpx_sreg_match[i].reg, &val); + + arm_cpu->cpreg_values[whpx_sreg_match[i].cp_idx] =3D val.Reg64; + } + assert(write_list_to_cpustate(arm_cpu)); + + aarch64_restore_sp(env, arm_current_el(env)); +} + +void whpx_set_registers(CPUState *cpu, int level) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + WHV_REGISTER_VALUE val; + clean_whv_register_value(&val); + int i; + + assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); + + for (i =3D 0; i < ARRAY_SIZE(whpx_reg_match); i++) { + val.Reg64 =3D *(uint64_t *)((void *)env + whpx_reg_match[i].offset= ); + whpx_set_reg(cpu, whpx_reg_match[i].reg, val); + } + + for (i =3D 0; i < ARRAY_SIZE(whpx_fpreg_match); i++) { + memcpy(&val.Reg128, (void *)env + whpx_fpreg_match[i].offset, size= of(val.Reg128)); + whpx_set_reg(cpu, whpx_reg_match[i].reg, val); + } + + clean_whv_register_value(&val); + val.Reg64 =3D env->pc; + whpx_set_reg(cpu, WHvArm64RegisterPc, val); + + clean_whv_register_value(&val); + val.Reg32 =3D vfp_get_fpcr(env); + whpx_set_reg(cpu, WHvArm64RegisterFpcr, val); + val.Reg32 =3D vfp_get_fpsr(env); + whpx_set_reg(cpu, WHvArm64RegisterFpsr, val); + val.Reg32 =3D pstate_read(env); + whpx_set_reg(cpu, WHvArm64RegisterPstate, val); + + aarch64_save_sp(env, arm_current_el(env)); + + assert(write_cpustate_to_list(arm_cpu, false)); + for (i =3D 0; i < ARRAY_SIZE(whpx_sreg_match); i++) { + if (whpx_sreg_match[i].global =3D=3D true) { + continue; + } + + if (whpx_sreg_match[i].cp_idx =3D=3D -1) { + continue; + } + clean_whv_register_value(&val); + val.Reg64 =3D arm_cpu->cpreg_values[whpx_sreg_match[i].cp_idx]; + whpx_set_reg(cpu, whpx_sreg_match[i].reg, val); + } + + /* Currently set global regs every time. */ + for (i =3D 0; i < ARRAY_SIZE(whpx_sreg_match); i++) { + if (whpx_sreg_match[i].global =3D=3D false) { + continue; + } + + if (whpx_sreg_match[i].cp_idx =3D=3D -1) { + continue; + } + clean_whv_register_value(&val); + val.Reg64 =3D arm_cpu->cpreg_values[whpx_sreg_match[i].cp_idx]; + whpx_set_global_reg(whpx_sreg_match[i].reg, val); + } +} + +static uint32_t max_vcpu_index; + +static void whpx_cpu_update_state(void *opaque, bool running, RunState sta= te) +{ +} + +int whpx_init_vcpu(CPUState *cpu) +{ + HRESULT hr; + struct whpx_state *whpx =3D &whpx_global; + AccelCPUState *vcpu =3D NULL; + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + int ret; + + uint32_t sregs_match_len =3D ARRAY_SIZE(whpx_sreg_match); + uint32_t sregs_cnt =3D 0; + WHV_REGISTER_VALUE val; + int i; + + vcpu =3D g_new0(AccelCPUState, 1); + + hr =3D whp_dispatch.WHvCreateVirtualProcessor( + whpx->partition, cpu->cpu_index, 0); + if (FAILED(hr)) { + error_report("WHPX: Failed to create a virtual processor," + " hr=3D%08lx", hr); + ret =3D -EINVAL; + goto error; + } + + /* Assumption that CNTFRQ_EL0 is the same between the VMM and the part= ition. */ + asm volatile("mrs %0, cntfrq_el0" : "=3Dr"(arm_cpu->gt_cntfrq_hz)); + + cpu->vcpu_dirty =3D true; + cpu->accel =3D vcpu; + max_vcpu_index =3D max(max_vcpu_index, cpu->cpu_index); + qemu_add_vm_change_state_handler(whpx_cpu_update_state, env); + + env->aarch64 =3D true; + + /* Allocate enough space for our sysreg sync */ + arm_cpu->cpreg_indexes =3D g_renew(uint64_t, arm_cpu->cpreg_indexes, + sregs_match_len); + arm_cpu->cpreg_values =3D g_renew(uint64_t, arm_cpu->cpreg_values, + sregs_match_len); + arm_cpu->cpreg_vmstate_indexes =3D g_renew(uint64_t, + arm_cpu->cpreg_vmstate_indexe= s, + sregs_match_len); + arm_cpu->cpreg_vmstate_values =3D g_renew(uint64_t, + arm_cpu->cpreg_vmstate_values, + sregs_match_len); + + memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); + + /* Populate cp list for all known sysregs */ + for (i =3D 0; i < sregs_match_len; i++) { + const ARMCPRegInfo *ri; + uint32_t key =3D whpx_sreg_match[i].key; + + ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, key); + if (ri) { + assert(!(ri->type & ARM_CP_NO_RAW)); + whpx_sreg_match[i].cp_idx =3D sregs_cnt; + arm_cpu->cpreg_indexes[sregs_cnt++] =3D cpreg_to_kvm_id(key); + } else { + whpx_sreg_match[i].cp_idx =3D -1; + } + } + arm_cpu->cpreg_array_len =3D sregs_cnt; + arm_cpu->cpreg_vmstate_array_len =3D sregs_cnt; + + assert(write_cpustate_to_list(arm_cpu, false)); + + /* Set CP_NO_RAW system registers on init */ + val.Reg64 =3D arm_cpu->midr; + whpx_set_reg(cpu, WHvArm64RegisterMidrEl1, + val); + + clean_whv_register_value(&val); + + val.Reg64 =3D deposit64(arm_cpu->mp_affinity, 31, 1, 1 /* RES1 */); + whpx_set_reg(cpu, WHvArm64RegisterMpidrEl1, val); + + return 0; + +error: + g_free(vcpu); + + return ret; + +} + +void whpx_cpu_instance_init(CPUState *cs) +{ +} + +int whpx_accel_init(AccelState *as, MachineState *ms) +{ + struct whpx_state *whpx; + int ret; + HRESULT hr; + WHV_CAPABILITY whpx_cap; + UINT32 whpx_cap_size; + WHV_PARTITION_PROPERTY prop; + WHV_CAPABILITY_FEATURES features =3D {0}; + + whpx =3D &whpx_global; + /* on arm64 Windows Hypervisor Platform, vGICv3 always used */ + whpx->kernel_irqchip =3D true; + + if (!init_whp_dispatch()) { + ret =3D -ENOSYS; + goto error; + } + + whpx->mem_quota =3D ms->ram_size; + + hr =3D whp_dispatch.WHvGetCapability( + WHvCapabilityCodeHypervisorPresent, &whpx_cap, + sizeof(whpx_cap), &whpx_cap_size); + if (FAILED(hr) || !whpx_cap.HypervisorPresent) { + error_report("WHPX: No accelerator found, hr=3D%08lx", hr); + ret =3D -ENOSPC; + goto error; + } + + hr =3D whp_dispatch.WHvGetCapability( + WHvCapabilityCodeFeatures, &features, sizeof(features), NULL); + if (FAILED(hr)) { + error_report("WHPX: Failed to query capabilities, hr=3D%08lx", hr); + ret =3D -EINVAL; + goto error; + } + + if (!features.Arm64Support) { + error_report("WHPX: host OS exposing pre-release WHPX implementati= on. " + "Please update your operating system to at least build 26100.3= 915"); + ret =3D -EINVAL; + goto error; + } + + hr =3D whp_dispatch.WHvCreatePartition(&whpx->partition); + if (FAILED(hr)) { + error_report("WHPX: Failed to create partition, hr=3D%08lx", hr); + ret =3D -EINVAL; + goto error; + } + + memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY)); + prop.ProcessorCount =3D ms->smp.cpus; + hr =3D whp_dispatch.WHvSetPartitionProperty( + whpx->partition, + WHvPartitionPropertyCodeProcessorCount, + &prop, + sizeof(WHV_PARTITION_PROPERTY)); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set partition processor count to %u," + " hr=3D%08lx", prop.ProcessorCount, hr); + ret =3D -EINVAL; + goto error; + } + + if (!whpx->kernel_irqchip_allowed) { + error_report("WHPX: on Arm, only kernel-irqchip=3Don is currently = supported"); + ret =3D -EINVAL; + goto error; + } + + memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY)); + + hr =3D whp_dispatch.WHvSetupPartition(whpx->partition); + if (FAILED(hr)) { + error_report("WHPX: Failed to setup partition, hr=3D%08lx", hr); + ret =3D -EINVAL; + goto error; + } + + whpx_memory_init(); + + return 0; + +error: + + if (NULL !=3D whpx->partition) { + whp_dispatch.WHvDeletePartition(whpx->partition); + whpx->partition =3D NULL; + } + + return ret; +} --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1760634041; cv=none; d=zohomail.com; s=zohoarc; b=aXKLOu9Qe6UP3bC2LP/VF7M9fv8offEmaRvu6yZ/OcIm70HGXomHkbREabRlkglIYn+Hot/Nj+Clt3Skr473E8QZBExrcKho6cNziot/HdTrxfptutIAWoyIOgjLA4jPFN54uRBDTsoRF/bgXuBr8aLp86ql+jtkoJPtJs6Xp0Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760634041; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=X4HLxeIyHK0KKw8PIa5chPyq98xB5PG+vYgn4ck2iWM=; b=H8UNru8MisqBS/jalP8hhI13fLUm71fBlf6XpHepa1pZUZHAJDIlVLF5wPu1SC6Z6FSRVATsywMSaf6/pJ8EaOr/+yaCQH0zXEW0UyDskfvVWqL56RjrETTkvZ6Jt3eysXBmiXManizyuYabqvwqpQTaKPLFe4saUlxCWd36/YM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760634041008520.1033693981375; Thu, 16 Oct 2025 10:00:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v9RIh-0001An-U1; Thu, 16 Oct 2025 12:58:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RId-00018w-2w for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:58:00 -0400 Received: from p-east2-cluster1-host8-snip4-1.eps.apple.com ([57.103.76.74] helo=outbound.st.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RIB-0001cW-VI for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:57:58 -0400 Received: from outbound.st.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPS id C2BB918015F8; Thu, 16 Oct 2025 16:57:16 +0000 (UTC) Received: from localhost.localdomain (unknown [17.42.251.67]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPSA id 8A89F1800317; Thu, 16 Oct 2025 16:56:07 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=X4HLxeIyHK0KKw8PIa5chPyq98xB5PG+vYgn4ck2iWM=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=WaUUM4rOXYwsLYRKRibENDznsdNteeNfjjfJr37poxWVT25X9OB6YBGHMhRdQE5pVGYJsrN4J1RhjbcrEgoRnD3jr9swjwIhXdRvFQqd0JB00a2hrrdH2NOJjjDEGMIFld33WTMRb5X7ZHqhyOe2ZEQf/JrZmq/EIPpBj46plMEUkWJsEsS4voHvjhJEl773PiMmI8FAnry/nonkQoTUYMVMQ9cadfm7KKZwwSwxeEPghGUjjOj+buwn+ZzawFDqtTXnHoSFYzM2tkRBOuSAOBW1JONW+psouKErIsClMgw9wXUDp93ADFfezZJCp9fNPJcVuydI3FmCJCMK7uixBA== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. Tsirkin" , Igor Mammedov , Paolo Bonzini , Yanan Wang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Shannon Zhao , kvm@vger.kernel.org, Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pedro Barbuda , Zhao Liu , Roman Bolshakov , Pierrick Bouvier Subject: [PATCH v7 13/24] whpx: copy over memory management logic from hvf Date: Thu, 16 Oct 2025 18:55:09 +0200 Message-ID: <20251016165520.62532-14-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251016165520.62532-1-mohamed@unpredictable.fr> References: <20251016165520.62532-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: RW90amPd7TnaVi7O2M9X-eJZ3T1_GCLi X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE2MDEyMiBTYWx0ZWRfX+eHzf3Mr8o8d 1Mt6HZTElluV+7BDfo3l7pJqg0SVJtAElcIr050CGPLayKXXeZVgMpSWNky0/YoQXquKRPbXA/5 p842yni4mkVJdEXfwUkIhtimezDYDdjc5ocQuGnuIMRRfdNYkCT6lWkFjNnjPWEydqGABS1k95W qJdRLOISEG75LDL9JRP+Osj+85LvekJ23J1VVfbiKmflubIrXBk8P2p1bPwx/fts+PyqMMzz9bn 0K6imtqHiVPmWZRW8DPMvvNMkMMlXP933v/Qv1RU/NMZbD718uDu4cTEbMw7chuU7aNISD6Yw= X-Proofpoint-GUID: RW90amPd7TnaVi7O2M9X-eJZ3T1_GCLi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 mlxscore=0 spamscore=0 suspectscore=0 clxscore=1030 bulkscore=0 malwarescore=0 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510160122 X-JNJ: AAAAAAABfrdvjvZJJ5ozzleXQcFPKI8f/YqTj0Civ6EZ1+mHY1v7KuYOAbxkMsu6uRNUBxrADLDH20vpgjY/S/aaynNAD7GotOADl21uStPLJN1U9sEcWVmjXr+sqPSrxsYREWtXLh/B0V48CdIYTSAGDMQ9RvpDGRMzgSq8IT1e2oKw+LRiAZThQN7H//P15DNyTw4dzCqtKa2GzrrdvmmfKp4+9Sct+gQpTRgC7qzGmRIVlkuKblD+3vjpzgyq/a84AuHhx7S4uAz6ADFxBpo5ct1zGNTtg7npZdFYSmBZlBK4sYJjoDhgMkw3Ij9ui7ix/J5sX474iVleB7LaderN1RF/1M+Ckkit9JjuRm+A53I5KWikhoUmh/ls+sVXPPPGVXJHQ5CMpcrQ6SHwx+6jXA7AxWslgKlg2vLBBx6Va+U0+jA+SDNToR3dn6RKla91gLV2bx1JTcvxyH9krOVrvaEtOSS6h+yZ9c246FXaU0R6J5v0GXjXt/1C8sWZrVdr3OEGVldkMcH+cX3hT8rG0ku6wwZ6tqJkSb0qip9KZMAOyXN/1KMXB4o/8/kncZF+ca/oOmNSpoX+eIRePJnp5fERmMtqpziexO94N/aVdZrLEXnML66/jhxeZZBfrjLkTUXpUbOHbyiVRAo16K/BiM3GRw3CR07nuq6S8CuQ7DESt8Jw+NC2NHGModI+3ly2iH4AFCIAgID/7wYKO35XIKcAdHSnKKys+28fK1PB9jynp2BtY+JIqsN5HQ7FPbTsvWtEP8Ry7Uk5u4rKMZ+EtifmnoTIP2h2h/F6AdNUVLUn/p4+K82mZWQExEyw60avK+hn5phn2DMK64xUC9/QTulM7igtC00HCN0tXCaDC5CAHjz5YzxUVYw6EWXfEFG72UFum7L21shwsgwPW4nwdXJs9WOVQvG4GcxkKLDQvMJtL8mQNg== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.76.74; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760634044882154100 Content-Type: text/plain; charset="utf-8" This allows edk2 to work, although u-boot is still not functional. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- accel/whpx/whpx-common.c | 201 ++++++++++++++++++++++++++++----------- 1 file changed, 147 insertions(+), 54 deletions(-) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index c69792e638..f324f5c146 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -258,89 +258,174 @@ void whpx_vcpu_kick(CPUState *cpu) * Memory support. */ =20 -static void whpx_update_mapping(hwaddr start_pa, ram_addr_t size, - void *host_va, int add, int rom, - const char *name) + /* whpx_slot flags */ +#define WHPX_SLOT_LOG (1 << 0) +typedef struct whpx_slot { + uint64_t start; + uint64_t size; + uint8_t *mem; + int slot_id; + uint32_t flags; + MemoryRegion *region; +} whpx_slot; + +typedef struct WHPXState { + whpx_slot slots[32]; + int num_slots; +} WHPXState; + + WHPXState *whpx_state; + + struct mac_slot { + int present; + uint64_t size; + uint64_t gpa_start; + uint64_t gva; +}; + +struct mac_slot mac_slots[32]; + +static int do_whpx_set_memory(whpx_slot *slot, WHV_MAP_GPA_RANGE_FLAGS fla= gs) { struct whpx_state *whpx =3D &whpx_global; + struct mac_slot *macslot; HRESULT hr; =20 - /* - if (add) { - printf("WHPX: ADD PA:%p Size:%p, Host:%p, %s, '%s'\n", - (void*)start_pa, (void*)size, host_va, - (rom ? "ROM" : "RAM"), name); - } else { - printf("WHPX: DEL PA:%p Size:%p, Host:%p, '%s'\n", - (void*)start_pa, (void*)size, host_va, name); + macslot =3D &mac_slots[slot->slot_id]; + + if (macslot->present) { + if (macslot->size !=3D slot->size) { + macslot->present =3D 0; + hr =3D whp_dispatch.WHvUnmapGpaRange(whpx->partition, + macslot->gpa_start, macslot->size); + if (FAILED(hr)) { + abort(); + } + } } - */ - - if (add) { - hr =3D whp_dispatch.WHvMapGpaRange(whpx->partition, - host_va, - start_pa, - size, - (WHvMapGpaRangeFlagRead | - WHvMapGpaRangeFlagExecute | - (rom ? 0 : WHvMapGpaRangeFlagWri= te))); - } else { - hr =3D whp_dispatch.WHvUnmapGpaRange(whpx->partition, - start_pa, - size); + + if (!slot->size) { + return 0; } =20 - if (FAILED(hr)) { - error_report("WHPX: Failed to %s GPA range '%s' PA:%p, Size:%p byt= es," - " Host:%p, hr=3D%08lx", - (add ? "MAP" : "UNMAP"), name, - (void *)(uintptr_t)start_pa, (void *)size, host_va, h= r); + macslot->present =3D 1; + macslot->gpa_start =3D slot->start; + macslot->size =3D slot->size; + hr =3D whp_dispatch.WHvMapGpaRange(whpx->partition, + slot->mem, slot->start, slot->size, flags); + return 0; +} + +static whpx_slot *whpx_find_overlap_slot(uint64_t start, uint64_t size) +{ + whpx_slot *slot; + int x; + for (x =3D 0; x < whpx_state->num_slots; ++x) { + slot =3D &whpx_state->slots[x]; + if (slot->size && start < (slot->start + slot->size) && + (start + size) > slot->start) { + return slot; + } } + return NULL; } =20 -static void whpx_process_section(MemoryRegionSection *section, int add) +static void whpx_set_phys_mem(MemoryRegionSection *section, bool add) { - MemoryRegion *mr =3D section->mr; - hwaddr start_pa =3D section->offset_within_address_space; - ram_addr_t size =3D int128_get64(section->size); - unsigned int delta; - uint64_t host_va; + whpx_slot *mem; + MemoryRegion *area =3D section->mr; + bool writable =3D !area->readonly && !area->rom_device; + WHV_MAP_GPA_RANGE_FLAGS flags; + uint64_t page_size =3D qemu_real_host_page_size(); + + if (!memory_region_is_ram(area)) { + if (writable) { + return; + } else if (!memory_region_is_romd(area)) { + /* + * If the memory device is not in romd_mode, then we actually = want + * to remove the whpx memory slot so all accesses will trap. + */ + add =3D false; + } + } =20 - if (!memory_region_is_ram(mr)) { - return; + if (!QEMU_IS_ALIGNED(int128_get64(section->size), page_size) || + !QEMU_IS_ALIGNED(section->offset_within_address_space, page_size))= { + /* Not page aligned, so we can not map as RAM */ + add =3D false; } =20 - delta =3D qemu_real_host_page_size() - (start_pa & ~qemu_real_host_pag= e_mask()); - delta &=3D ~qemu_real_host_page_mask(); - if (delta > size) { - return; + mem =3D whpx_find_overlap_slot( + section->offset_within_address_space, + int128_get64(section->size)); + + if (mem && add) { + if (mem->size =3D=3D int128_get64(section->size) && + mem->start =3D=3D section->offset_within_address_space && + mem->mem =3D=3D (memory_region_get_ram_ptr(area) + + section->offset_within_region)) { + return; /* Same region was attempted to register, go away. */ + } + } + + /* Region needs to be reset. set the size to 0 and remap it. */ + if (mem) { + mem->size =3D 0; + if (do_whpx_set_memory(mem, 0)) { + error_report("Failed to reset overlapping slot"); + abort(); + } } - start_pa +=3D delta; - size -=3D delta; - size &=3D qemu_real_host_page_mask(); - if (!size || (start_pa & ~qemu_real_host_page_mask())) { + + if (!add) { return; } =20 - host_va =3D (uintptr_t)memory_region_get_ram_ptr(mr) - + section->offset_within_region + delta; + if (area->readonly || + (!memory_region_is_ram(area) && memory_region_is_romd(area))) { + flags =3D WHvMapGpaRangeFlagRead | WHvMapGpaRangeFlagExecute; + } else { + flags =3D WHvMapGpaRangeFlagRead | WHvMapGpaRangeFlagWrite + | WHvMapGpaRangeFlagExecute; + } + + /* Now make a new slot. */ + int x; + + for (x =3D 0; x < whpx_state->num_slots; ++x) { + mem =3D &whpx_state->slots[x]; + if (!mem->size) { + break; + } + } + + if (x =3D=3D whpx_state->num_slots) { + error_report("No free slots"); + abort(); + } =20 - whpx_update_mapping(start_pa, size, (void *)(uintptr_t)host_va, add, - memory_region_is_rom(mr), mr->name); + mem->size =3D int128_get64(section->size); + mem->mem =3D memory_region_get_ram_ptr(area) + section->offset_within_= region; + mem->start =3D section->offset_within_address_space; + mem->region =3D area; + + if (do_whpx_set_memory(mem, flags)) { + error_report("Error registering new memory slot"); + abort(); + } } =20 static void whpx_region_add(MemoryListener *listener, MemoryRegionSection *section) { - memory_region_ref(section->mr); - whpx_process_section(section, 1); + whpx_set_phys_mem(section, true); } =20 static void whpx_region_del(MemoryListener *listener, MemoryRegionSection *section) { - whpx_process_section(section, 0); - memory_region_unref(section->mr); + whpx_set_phys_mem(section, false); } =20 static void whpx_transaction_begin(MemoryListener *listener) @@ -524,6 +609,14 @@ static void whpx_accel_instance_init(Object *obj) memset(whpx, 0, sizeof(struct whpx_state)); /* Turn on kernel-irqchip, by default */ whpx->kernel_irqchip_allowed =3D true; + + int x; + whpx_state =3D malloc(sizeof(WHPXState)); + whpx_state->num_slots =3D ARRAY_SIZE(whpx_state->slots); + for (x =3D 0; x < whpx_state->num_slots; ++x) { + whpx_state->slots[x].size =3D 0; + whpx_state->slots[x].slot_id =3D x; + } } =20 static const TypeInfo whpx_accel_type =3D { --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1760634243; cv=none; d=zohomail.com; s=zohoarc; b=DC5JeUo31ntkZiZ5LTXVgUT14vOhmIFcZAuiwr8Fial7hkIWH7ldyPmkxveV8IjQJ1IdsGWKOE1tBtqBHP2A0lEaIwFb8hsiNtAuqqM2Va7RzVGjrfX5G/Q/FeTV8rmJphiFrYgs2CmEWbN61AGyriHooRLzSiMuJgG1LgZ9d+A= ARC-Message-Signature: i=1; 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bh=AZVyyBW9yXgsaeulA1YXhH/G5izca99gWRDYt1AsjCw=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=LJxk1oU/PhdViyEgTOpI+H6Q6yhgQvte58YjngC0iV9JGb3b9f3KoBf4UtITIn8kJIkqoT7r3M2HKfq6qLHty8OvyG4eofaTnUY/4FXQx+vb8LsCZ4Rdm0c9Bq6WTtgDjTTng+hYzd3Wfah4NdlQX9Un5yKD0ja5loqkaUbGg0v7USVGg4CuR8PkiLiDCvjHhexhWOGqzDLmhSaZjZdNts2ftXs52q4ZnqBVMWnjh1KVWIBB/u+65qwXShfeWE5qDlmJJ08rF/VvoJPh43AwLiRnL5VqpprOdXXowQZyxxdiApIRLs1iVca81VpScTfneF1a2y1c/Z2kcSAtf18ymQ== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. Tsirkin" , Igor Mammedov , Paolo Bonzini , Yanan Wang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Shannon Zhao , kvm@vger.kernel.org, Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pedro Barbuda , Zhao Liu , Roman Bolshakov , Pierrick Bouvier Subject: [PATCH v7 14/24] target/arm: cpu: mark WHPX as supporting PSCI 1.3 Date: Thu, 16 Oct 2025 18:55:10 +0200 Message-ID: <20251016165520.62532-15-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251016165520.62532-1-mohamed@unpredictable.fr> References: <20251016165520.62532-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: JsCEOPQOJ2dsSIDOxlHrsbL5OsLuv_dQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE2MDEyMiBTYWx0ZWRfX92gxmSv9O7po C31ioFjC667O407rDAP+I7esduqWKOQeqt4r/HF1vflt5nnHtAha1jNxXz8zux2fqzkt3Ns338Z Ij3oZV1di3pfaBXOqCLreV/sTAsK/ft4QW+HBg4Thzo5iDP7Gu5nZ3n+kaOe520JwiYhf42SA+9 9Ipr5n48NSu5gESRATmkDFudtl6ToFJ0afQhHMrgNZ30j2931jzSg1LU7sfDjbetvrZxT7Jr46C wCzmig9EXFd7sA2y1ufVLu3IxbTpMPLydSBDADnWX+z4vFZzKHdmo4rlh9DeVsRW6Cour6n1g= X-Proofpoint-GUID: JsCEOPQOJ2dsSIDOxlHrsbL5OsLuv_dQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1030 phishscore=0 suspectscore=0 adultscore=0 mlxlogscore=906 bulkscore=0 malwarescore=0 spamscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510160122 X-JNJ: AAAAAAABiyYFN1ylLz9x2kQJNEPRbUP3xlqwEVogXRXR2ZOOevjA+VJdwIaZ9iGcCDVM5Vc2oHYBKP+ZFCLIEMpbmtDSPhtW5ml/A/715zWSn1yLhgvg2vWw67NhoDXOuWeHdSd8CzSyqearBtLfqxeX/VpHSQwQI8CvTT4/sSAtcZZCyUARmProdzfBj5iq51c8uVCz7ugM/nzlLNNPORH6CH/TBwI06KA+syC0D6D9phEsVNpH8uV9acqg+FOQYrNewslELwyprxF+370b4odbLc1To8piL9ppJS7fHBBccT7mxpj2+qNFyCRpoudFaMtOQ9jRfMgLRbzgeivuotc7kvVnerjgd/D8J7B8TLMx5RAmQAUqOvQZkCKXjSpMHZrm0PU3H91/jf5ek7uSgOZVAujRQ2lAieMh6TULbwZrG1KguYI2l0KcpVaKwJuNNwFSsPZHomXub2R8yu2Pe7ambQ+zkOf86f/c6vHGwnNMqZwPlYsZ7suy0NWJh2sF2Y+e19CyK0vXzgMojU7xN5Mwj38ZLbgOsFOGstZaozB9qyc7j2epK6ijJwL7qunQWjR6LIhhwfrgu95lFoR+/aJjolZSkr3QHHlxU4YLx8NxQhOAr/NwnO0Bft4dXic1MQ7H8CnduPme1FFXlGR7TRKfTbGK6LjFahqZCZsCko7Ib5XdcR+3wzXfKm4ikUJw3c8Az2v+dBa4CDY+TPpQB4VC5E1dZDDl5uQKPZ5IS5ndv2kqCGgMmKLk4z1eW4syWB9S52H9kJlxJbD48HDYux31b8QA+T7tprYxmeRnA6d8mxeHFWKETH01icXv6hNeE+yFfwl85K5BhBavLa/kpLw8SRAyAGyjpC9U4OjDqOqb04k9RmeuXIpoeseRDaxvMAlNp25psLqXjXcdnXTArcARzPR0ud6rsLB/EXMdkA3VYsXGHinUaZW9gRY/8Vc= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.76.30; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760634245287154100 Content-Type: text/plain; charset="utf-8" Hyper-V supports PSCI 1.3, and that implementation is exposed through WHPX. Signed-off-by: Mohamed Mediouni Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/arm/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3b556f1404..bf25b3580e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -23,6 +23,7 @@ #include "qemu/timer.h" #include "qemu/log.h" #include "exec/page-vary.h" +#include "system/whpx.h" #include "target/arm/idau.h" #include "qemu/module.h" #include "qapi/error.h" @@ -1140,6 +1141,8 @@ static void arm_cpu_initfn(Object *obj) if (tcg_enabled() || hvf_enabled()) { /* TCG and HVF implement PSCI 1.1 */ cpu->psci_version =3D QEMU_PSCI_VERSION_1_1; + } else if (whpx_enabled()) { + cpu->psci_version =3D QEMU_PSCI_VERSION_1_3; } } =20 --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1760634096; cv=none; d=zohomail.com; s=zohoarc; b=J/jAekNMfP0lbm3w6sI3zKbD+nK+6vrX8Jlb/zT7F7S6D6vbL+Bsg9bbqxYFadtz30qoS98X/IzTZajeT4qeePkkAzL5GTf3XoZXs0PC9o8YpVauqdgfwbBITfR0N8fSNeHG601Ib2KEachKQnD4IftqCdtZVS2mAYnIzJed20w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760634096; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=l22ICiGLwj6aXpGxuf8i6PtVOTlAq5b5eC2p9+pf+tY=; b=IB+2tgE/d0xfS9RwVdOxIPIS3tmjJpI/P+Zsg7iuqWtJ1aYEuPStRJneuy1riqP8/H5GsiGF3G6LE6diZFfQ5tCtqkUKgN8fFDQntLq2KUc4CdKFYbBpew2MqYcSrfrDwqpXdgflQYI9zkuFWjEgk21A5e7/G4lcnK1G6W0i154= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760634096950957.1168529189885; Thu, 16 Oct 2025 10:01:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v9RIS-00014A-Ck; Thu, 16 Oct 2025 12:57:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RIR-00013a-1A for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:57:47 -0400 Received: from p-east2-cluster1-host11-snip4-10.eps.apple.com ([57.103.76.53] helo=outbound.st.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RI2-0001c5-9B for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:57:43 -0400 Received: from outbound.st.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPS id 109A51800332; Thu, 16 Oct 2025 16:57:18 +0000 (UTC) Received: from localhost.localdomain (unknown [17.42.251.67]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPSA id 6E0311800322; Thu, 16 Oct 2025 16:56:14 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=l22ICiGLwj6aXpGxuf8i6PtVOTlAq5b5eC2p9+pf+tY=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=AqMfNsEmKzxAytJaGwKkikXzZrDPBGbU9bLkc7RYI0LeNipd/Ve4/YlzCRvQynML/I49avjPK2Cq+CAaGnqZoBXD5jpzRir1IWd9QJ4w0tpXJMp+pt0txZeUmjmaw57Ew2qgFT7u9M54aq8F7hXJzyFnxAhQhgC92a2O4jJu1rSVgbmvD635MYZfeHDTu0SIoDBKMZJ2Cl+0NZCmgdQOVEzhsHNVRTIuiKDQiDzAzVYosMZdkmLSm2kvXH/ExRMJzuFpMp8/NhLR4+TMBazhMo2YXou0amos0fQ62Abm17nCka4zyb1epmndTvF+sHy4R16v3SSF5HVOU4Kn4huA+A== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. Tsirkin" , Igor Mammedov , Paolo Bonzini , Yanan Wang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Shannon Zhao , kvm@vger.kernel.org, Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pedro Barbuda , Zhao Liu , Roman Bolshakov Subject: [PATCH v7 15/24] hw/arm: virt: cleanly fail on attempt to use the platform vGIC together with ITS Date: Thu, 16 Oct 2025 18:55:11 +0200 Message-ID: <20251016165520.62532-16-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251016165520.62532-1-mohamed@unpredictable.fr> References: <20251016165520.62532-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: f0tLGjiMLByt0CRyjAwB_UP6ISX8K_7y X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE2MDEyMiBTYWx0ZWRfX3j7ynFxbvj4u 1gsBAA9KBG7QCLGTotpcJZuYjtZNpODS0ngM6wQeaGBVJPehWyFCB/NWX1st5XthuMvZyp/iHOe j5hzCBMeA/kyf9L7y1/CDAy7SqWhFppXYzNglBQQi6dLy1euU4MwDdyVqQgDLDnvFxUKkOOFKQn l1WO52CiSfayf41mEwZgtD+ZuE7iV6wpJxbwqSVU3zQPfrQXj6Vc+3fhBxwQY7hucLcoqVBGgfJ S3naUG4gZDfgOka8FTQN98kOJS8u+bV6AW1pO+U1HnYWDpKplcPH2kSUqUElXFdR8TYTTpunY= X-Proofpoint-ORIG-GUID: f0tLGjiMLByt0CRyjAwB_UP6ISX8K_7y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 malwarescore=0 mlxscore=0 spamscore=0 mlxlogscore=999 clxscore=1030 bulkscore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510160122 X-JNJ: AAAAAAABsgs2SEdDWHGDOJEpMvZuESfQeN8HtvUY5nHib09Eh7Q0J4ZxhKePxnvcoSfoHFK0WrmyetLqwiDhX0UqAOvoqbMRCqeqwagL7mqaa/swqaE7I5XHqu1fTf14tMBhkXIdq46PMNpCbYKtsTvq4ItX6q7X4B+oK9JUqZ6yxHnUj353q/ydhkZ8klt2JPto142eC8rUrpNsBGL2S7poCcSTsQS8xPl3EPnBmxI8ebUv6s9rkZT238Ovy8qtBpmFHyO19AJOC6WaCKUmm9mOKxuy7RYA7cGZbzMzofJkHoQkZOsWcIJQ52pxehX+0DDdn03ckwsPM+sN0vSgezMvBrRfdQwfk0cdM1O0Dgu7mfgSza62itXZqwWehhGBD2y7sYVDN9cg3+/UV+kdJPkJjCwrc1ijExgHWmlfr2rMI6DdhC27u8iSXPNcMc5dresfOcHWlSeTZ3oP/qK2EsQTkZMmhtCk/qbJo1Fq/9HcArPjBHdkhpSAguVOvEEoYiuaRA5ehV10JO1ryuQD864XLsJwKSaqUv0Sw4vaa4L5D3HchYTVhDnBiMfR9ZwiuNwHflAfW87TZ3DfM2lkiEAgq+JXKBykVNuNy+NBzym1POz8KXvcATjzEFT1IhpdMU8XSy4VjJhYoczzpirITrMTj6hFoUxvbiL94hIFKEKyVcc6WMuEbHDsSJGj+24t5JRjayL22294X9t2EIInxBgXePbmmkUlLmNODE3AmFdIC2CdLkZEdYej5aPG24EMxvkjDQbCWYR2GtA1X8OCE52QeUO3PWzcSBve0b3Rr/pjs47QAbZ7rTrxy5aQTaUKPIbqDzBTMW2JZiWE1vbNXLFOwkjkFx4AVXYIYa80o8VsCmFZh7NmDExjmZ9Trdyy6/9BFFnZOIaGqYKh/Lr7rQ8ZR48= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.76.53; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760634099325154100 Content-Type: text/plain; charset="utf-8" Switch its to a tristate. Windows Hypervisor Platform's vGIC doesn't support ITS. Deal with this by reporting to the user and exiting. Regular configuration: GICv3 + ITS New default configuration with WHPX: GICv3 with GICv2m And its=3Doff explicitly for the newest machine version: GICv3 + GICv2m Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- hw/arm/virt-acpi-build.c | 14 +++++------ hw/arm/virt.c | 50 ++++++++++++++++++++++++++++++++-------- include/hw/arm/virt.h | 4 +++- 3 files changed, 50 insertions(+), 18 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 0a6ec74aa0..c716130206 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -472,7 +472,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) nb_nodes =3D num_smmus + 1; /* RC and SMMUv3 */ rc_mapping_count =3D rc_smmu_idmaps_len; =20 - if (vms->its) { + if (virt_is_its_enabled(vms)) { /* * Knowing the ID ranges from the RC to the SMMU, it's possibl= e to * determine the ID ranges from RC that go directly to ITS. @@ -483,7 +483,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) rc_mapping_count +=3D rc_its_idmaps->len; } } else { - if (vms->its) { + if (virt_is_its_enabled(vms)) { nb_nodes =3D 2; /* RC and ITS */ rc_mapping_count =3D 1; /* Direct map to ITS */ } else { @@ -498,7 +498,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ =20 - if (vms->its) { + if (virt_is_its_enabled(vms)) { /* Table 12 ITS Group Format */ build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Ty= pe */ node_size =3D 20 /* fixed header size */ + 4 /* 1 GIC ITS Identif= ier */; @@ -517,7 +517,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) int smmu_mapping_count, offset_to_id_array; int irq =3D sdev->irq; =20 - if (vms->its) { + if (virt_is_its_enabled(vms)) { smmu_mapping_count =3D 1; /* ITS Group node */ offset_to_id_array =3D SMMU_V3_ENTRY_SIZE; /* Just after the h= eader */ } else { @@ -610,7 +610,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } } =20 - if (vms->its) { + if (virt_is_its_enabled(vms)) { /* * Map bypassed (don't go through the SMMU) RIDs (input) to * ITS Group node directly: RC -> ITS. @@ -945,7 +945,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) memmap[VIRT_HIGH_GIC_REDIST2].si= ze); } =20 - if (vms->its) { + if (virt_is_its_enabled(vms)) { /* * ACPI spec, Revision 6.0 Errata A * (original 6.0 definition has invalid Length) @@ -961,7 +961,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } } =20 - if (!(vms->gic_version !=3D VIRT_GIC_VERSION_2 && vms->its) && !vms->n= o_gicv3_with_gicv2m) { + if (virt_is_its_enabled(vms) && !vms->no_gicv3_with_gicv2m) { const uint16_t spi_base =3D vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BA= SE; =20 /* 5.2.12.16 GIC MSI Frame Structure */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9121eb37eb..1bebbc265d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -735,7 +735,7 @@ static void create_its(VirtMachineState *vms) { DeviceState *dev; =20 - assert(vms->its); + assert(virt_is_its_enabled(vms)); if (!kvm_irqchip_in_kernel() && !vms->tcg_its) { /* * Do nothing if ITS is neither supported by the host nor emulated= by @@ -744,6 +744,15 @@ static void create_its(VirtMachineState *vms) return; } =20 + if (whpx_enabled() && vms->tcg_its) { + /* + * Signal to the user when ITS is neither supported by the host + * nor emulated by the machine. + */ + info_report("ITS not supported on WHPX."); + exit(1); + } + dev =3D qdev_new(its_class_name()); =20 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), @@ -955,7 +964,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) =20 fdt_add_gic_node(vms); =20 - if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && vms->its) { + if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && virt_is_its_enabled(vm= s)) { create_its(vms); } else if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && !vms->no_gicv3_= with_gicv2m) { create_v2m(vms); @@ -2705,18 +2714,38 @@ static void virt_set_highmem_mmio_size(Object *obj,= Visitor *v, extended_memmap[VIRT_HIGH_PCIE_MMIO].size =3D size; } =20 -static bool virt_get_its(Object *obj, Error **errp) +bool virt_is_its_enabled(VirtMachineState *vms) +{ + if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { + return false; + } + + if (vms->its =3D=3D ON_OFF_AUTO_OFF) { + return false; + } + if (vms->its =3D=3D ON_OFF_AUTO_AUTO) { + if (whpx_enabled()) { + return false; + } + } + return true; +} + +static void virt_get_its(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); + OnOffAuto its =3D vms->its; =20 - return vms->its; + visit_type_OnOffAuto(v, name, &its, errp); } =20 -static void virt_set_its(Object *obj, bool value, Error **errp) +static void virt_set_its(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); =20 - vms->its =3D value; + visit_type_OnOffAuto(v, name, &vms->its, errp); } =20 static bool virt_get_dtb_randomness(Object *obj, Error **errp) @@ -3426,8 +3455,9 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) "guest CPU which implements the = ARM " "Memory Tagging Extension"); =20 - object_class_property_add_bool(oc, "its", virt_get_its, - virt_set_its); + object_class_property_add(oc, "its", "OnOffAuto", + virt_get_its, virt_set_its, + NULL, NULL); object_class_property_set_description(oc, "its", "Set on/off to enable/disable " "ITS instantiation"); @@ -3487,8 +3517,8 @@ static void virt_instance_init(Object *obj) vms->highmem_mmio =3D true; vms->highmem_redists =3D true; =20 - /* Default allows ITS instantiation */ - vms->its =3D true; + /* Default allows ITS instantiation if available */ + vms->its =3D ON_OFF_AUTO_AUTO; /* Allow ITS emulation if the machine version supports it */ vms->tcg_its =3D !vmc->no_tcg_its; vms->no_gicv3_with_gicv2m =3D false; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index d31348dd61..997dd51678 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -149,7 +149,7 @@ struct VirtMachineState { bool highmem_ecam; bool highmem_mmio; bool highmem_redists; - bool its; + OnOffAuto its; bool tcg_its; bool virt; bool ras; @@ -218,4 +218,6 @@ static inline int virt_gicv3_redist_region_count(VirtMa= chineState *vms) vms->highmem_redists) ? 2 : 1; } =20 +bool virt_is_its_enabled(VirtMachineState *vms); + #endif /* QEMU_ARM_VIRT_H */ --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Remove the mention of pre-2.7 machine models as those aren't provided anymore. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- docs/system/arm/virt.rst | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 10cbffc8a7..fe95be991e 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -40,9 +40,10 @@ The virt board supports: - An optional SMMUv3 IOMMU - hotpluggable DIMMs - hotpluggable NVDIMMs -- An MSI controller (GICv2M or ITS). GICv2M is selected by default along - with GICv2. ITS is selected by default with GICv3 (>=3D virt-2.7). Note - that ITS is not modeled in TCG mode. +- An MSI controller (GICv2m or ITS). + - When using a GICv3, ITS is selected by default when available on the p= latform. + - If using a GICv2 or when ITS is not available, a GICv2m is provided by= default instead. + - Before virt-10.2, a GICv2m is not provided when the ITS is disabled. - 32 virtio-mmio transport devices - running guests using the KVM accelerator on aarch64 hardware - large amounts of RAM (at least 255GB, and more if using highmem) @@ -167,8 +168,7 @@ gic-version ``4`` if ``virtualization`` is ``on``, but this may change in future) =20 its - Set ``on``/``off`` to enable/disable ITS instantiation. The default is `= `on`` - for machine types later than ``virt-2.7``. + Set ``on``/``off``/``auto`` to control ITS instantiation. The default is= ``auto``. =20 iommu Set the IOMMU type to create for the guest. Valid values are: --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1760634059; cv=none; d=zohomail.com; s=zohoarc; b=nBKewMvr6DUSkgsdaHt5zPEjRhlbIjbZV2wbBvWoHwcuz9Q/aa8RJ40uk4hb+qh+2HNdtmVTILmwNj7fKIQ8qRzSvqI7AhfLkY8c7fs05ZMuAUpulfAZ5pmPheTXXJYzARM+OASGXhK2yH674d56omfhwJfAO+MSMaoB4k40UPg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760634059; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CvVKf9o8IK7zHuuMrO5kQA3WrF0ISdlWVQATSzelsq0=; b=ZSqAYK8lgdTSMeRJcp2r5Fl3yuKJj0upPXiNelttoDE3FbTIc/whBE1w2Hk6HJ1UoO/C2Jm2ATrFRu3XO4q44xb2k6er0rTAIKo8bxCb07rd2nftXam4SVg6bMxx/86Qk/KIGkkGwUnb5c2B0i3zmQQPw9qHMBm8MLhjBbLoha4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760634059142949.4074826867259; Thu, 16 Oct 2025 10:00:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v9RIa-00016z-6g; Thu, 16 Oct 2025 12:57:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RIX-00015o-Pr for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:57:53 -0400 Received: from p-east2-cluster1-host11-snip4-10.eps.apple.com ([57.103.76.53] helo=outbound.st.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RI8-0001d2-LB for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:57:53 -0400 Received: from outbound.st.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPS id 26E1818015D5; Thu, 16 Oct 2025 16:57:25 +0000 (UTC) Received: from localhost.localdomain (unknown [17.42.251.67]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPSA id 1DA191800319; Thu, 16 Oct 2025 16:56:21 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=CvVKf9o8IK7zHuuMrO5kQA3WrF0ISdlWVQATSzelsq0=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=YApFOkb/I6SDPvuDKTmlcMoC68Ds9G+M0RjQSfk4Eu4HBkuwu2o+JITvA1ebIHZjaqeZ0BN1C2ESG4HJKcRJdbQiwReL/qpbzUYfJ/zimbWpillVTaKkhtuJvu+t6qqhi3Eu+cc9OPgAdL6WseEYvZBEiDsKxR5tiYZs1ktmvZkyF74MxxsmP8EXdeOrAppFwavL2DFbjns+puQy+hyzzx9Jbts+UZqcxXNym/j4JqZUfIbGy9KU7jj9DakVYvbSxJh9zgEvdiF5x37iXWs4B+IIy+SHGV9BtE1Y0r1DEwdMYwb1H8YJC0O2fE3PJ/uygZRnfjdCCmX4F6A8yFTQJg== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. Tsirkin" , Igor Mammedov , Paolo Bonzini , Yanan Wang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Shannon Zhao , kvm@vger.kernel.org, Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pedro Barbuda , Zhao Liu , Roman Bolshakov , Pierrick Bouvier Subject: [PATCH v7 17/24] whpx: arm64: clamp down IPA size Date: Thu, 16 Oct 2025 18:55:13 +0200 Message-ID: <20251016165520.62532-18-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251016165520.62532-1-mohamed@unpredictable.fr> References: <20251016165520.62532-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: P079GoPLlC8LrjWGWw2DAGl_WZd91Hnw X-Proofpoint-ORIG-GUID: P079GoPLlC8LrjWGWw2DAGl_WZd91Hnw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE2MDEyMiBTYWx0ZWRfX77qbDpla/Sih tmNGdGcfhmS0amFRgUVbf8QaxeyescnsalNNX40KefDIdCt8ri2IzIP/985gPV5NU9EduIhP+bu vu2JD7IAXIHwApbm2vBv0JwA0nVajlhaJ8RA1bObapwpkmMUvC8lTcvfp7ps1HZwk1PF73Sst4R E2iFeO4rOUDYrHxR3NjlfkeLu9RjPx3A/KQWTLU36U4XM3/9kuNIVWZ1BxaLitw006wlb8aVTra bVypZkAk4sIfIoohl2e9Y7ysxo8shHgNe66UiCu8PrlXKOaoc+i7SdQQoJSXEX4PdkQQzTCA8= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 bulkscore=0 malwarescore=0 adultscore=0 spamscore=0 clxscore=1030 suspectscore=0 mlxscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510160122 X-JNJ: AAAAAAABq0aPi+nDqZ2z3o/R2sT/wIGSdUF2ct3bxqZHSn9hYI+4tg5d0Hp03AiylOIlF0mswhfqFg7nk7FFttba9Z2GeoDch8gotRu8oXB9A7o1e9c8GOBg9PBCBIpw8XAMmqZH/iBT89W3W0QZWHT1Fhkaof/T8s1zCGMP91upziOIN9y9qgioMe8AG3u5gpzJi0NGO6IojGc1zY+lraWltrMSpgIIYfRe45jItPS4POB0FVt8IOn6WbMfC3WodKXD7d6RJ41qk0k65FSdKAWjromCMzRaf85qpRDMKGOmXWGc2ddRcQHRzV+pobn8AHa/zjAqpmKFJZQmOdV2c2xx/F9pKqDRJd3ChH84PctjE9Jlj5lVNNmGEEykZfkACoeFlhjGQxXAoDVi52v2230TyBbfBU7FBY2NZ7bU1Qd9vS7y6Iyl95MyPlLjbFa2f3XGi+IwZeZPsRDsJ9iM5KwmDV3TEAf+OUV7sFCZfK1ku8NEqRLiT3mkt72HHZAgZo7OxJ1hcclgk2ToQ/bJ4bw3ni1P4Xr9PQK1KYktYsVPhWDnxddU84SIQxBijZ7zD9Pol2JppSiybCO9WbUT14t/AfkjifzUPJcpQp0fdZIZ02fcKqAXMCrErjWOgNFphTZrWoaY3nfmIbBYab5EOmok5t6AU/Bu9j+Wac7RO0jw6VmMYWaggeY+fjvXkFdUcJ/YQRLLhLjjXRFBsHjGK3TIN45T48bB/oy4b49TvMw3LFV//ve1PzLPKshAUkOUv/L8KeOfrYjCpQ3bbS+lPSyS1mbBsd65Sv88YjOB3BJ+iOzKe0UaOug9e2qdqcIa7o5BR9DnXYTtHoBooTF1yLTKYVpqYLliD2Cz02NP4xitLgRV33LrK0p0V/QXX/WgdvSDMhjzH6UhC0jnbw== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.76.53; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760634060879154100 Content-Type: text/plain; charset="utf-8" Code taken from HVF and adapted for WHPX use. Note that WHPX doesn't have a default vs maximum IPA distinction. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- hw/arm/virt.c | 32 ++++++++++++++++++++++++++ include/hw/boards.h | 1 + target/arm/whpx/meson.build | 2 ++ target/arm/whpx/whpx-all.c | 45 +++++++++++++++++++++++++++++++++++++ target/arm/whpx/whpx-stub.c | 15 +++++++++++++ target/arm/whpx_arm.h | 16 +++++++++++++ 6 files changed, 111 insertions(+) create mode 100644 target/arm/whpx/whpx-stub.c create mode 100644 target/arm/whpx_arm.h diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 1bebbc265d..b6b3e37f33 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -70,6 +70,7 @@ #include "hw/irq.h" #include "kvm_arm.h" #include "hvf_arm.h" +#include "whpx_arm.h" #include "hw/firmware/smbios.h" #include "qapi/visitor.h" #include "qapi/qapi-visit-common.h" @@ -3257,6 +3258,36 @@ static int virt_kvm_type(MachineState *ms, const cha= r *type_str) return fixed_ipa ? 0 : requested_pa_size; } =20 +static int virt_whpx_get_physical_address_range(MachineState *ms) +{ + VirtMachineState *vms =3D VIRT_MACHINE(ms); + + int max_ipa_size =3D whpx_arm_get_ipa_bit_size(); + + /* We freeze the memory map to compute the highest gpa */ + virt_set_memmap(vms, max_ipa_size); + + int requested_ipa_size =3D 64 - clz64(vms->highest_gpa); + + /* + * If we're <=3D the default IPA size just use the default. + * If we're above the default but below the maximum, round up to + * the maximum. hvf_arm_get_max_ipa_bit_size() conveniently only + * returns values that are valid ARM PARange values. + */ + if (requested_ipa_size <=3D max_ipa_size) { + requested_ipa_size =3D max_ipa_size; + } else { + error_report("-m and ,maxmem option values " + "require an IPA range (%d bits) larger than " + "the one supported by the host (%d bits)", + requested_ipa_size, max_ipa_size); + return -1; + } + + return requested_ipa_size; +} + static int virt_hvf_get_physical_address_range(MachineState *ms) { VirtMachineState *vms =3D VIRT_MACHINE(ms); @@ -3349,6 +3380,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) mc->get_default_cpu_node_id =3D virt_get_default_cpu_node_id; mc->kvm_type =3D virt_kvm_type; mc->hvf_get_physical_address_range =3D virt_hvf_get_physical_address_r= ange; + mc->whpx_get_physical_address_range =3D virt_whpx_get_physical_address= _range; assert(!mc->get_hotplug_handler); mc->get_hotplug_handler =3D virt_machine_get_hotplug_handler; hc->pre_plug =3D virt_machine_device_pre_plug_cb; diff --git a/include/hw/boards.h b/include/hw/boards.h index 665b620121..3d01fb8cc9 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -276,6 +276,7 @@ struct MachineClass { void (*wakeup)(MachineState *state); int (*kvm_type)(MachineState *machine, const char *arg); int (*hvf_get_physical_address_range)(MachineState *machine); + int (*whpx_get_physical_address_range)(MachineState *machine); =20 BlockInterfaceType block_default_type; int units_per_default_bus; diff --git a/target/arm/whpx/meson.build b/target/arm/whpx/meson.build index 1de2ef0283..3df632c9d3 100644 --- a/target/arm/whpx/meson.build +++ b/target/arm/whpx/meson.build @@ -1,3 +1,5 @@ arm_system_ss.add(when: 'CONFIG_WHPX', if_true: files( 'whpx-all.c', )) + +arm_common_system_ss.add(when: 'CONFIG_WHPX', if_false: files('whpx-stub.c= ')) diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 7ef900a5ca..62fd6c230a 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -35,6 +35,7 @@ #include "system/whpx-accel-ops.h" #include "system/whpx-all.h" #include "system/whpx-common.h" +#include "whpx_arm.h" #include "hw/arm/bsa.h" #include "arm-powerctl.h" =20 @@ -660,6 +661,40 @@ static void whpx_cpu_update_state(void *opaque, bool r= unning, RunState state) { } =20 +uint32_t whpx_arm_get_ipa_bit_size(void) +{ + WHV_CAPABILITY whpx_cap; + UINT32 whpx_cap_size; + HRESULT hr; + hr =3D whp_dispatch.WHvGetCapability( + WHvCapabilityCodePhysicalAddressWidth, &whpx_cap, + sizeof(whpx_cap), &whpx_cap_size); + if (FAILED(hr)) { + error_report("WHPX: failed to get supported" + "physical address width, hr=3D%08lx", hr); + } + + /* + * We clamp any IPA size we want to back the VM with to a valid PARange + * value so the guest doesn't try and map memory outside of the valid = range. + * This logic just clamps the passed in IPA bit size to the first valid + * PARange value <=3D to it. + */ + return round_down_to_parange_bit_size(whpx_cap.PhysicalAddressWidth); +} + +static void clamp_id_aa64mmfr0_parange_to_ipa_size(ARMISARegisters *isar) +{ + uint32_t ipa_size =3D whpx_arm_get_ipa_bit_size(); + uint64_t id_aa64mmfr0; + + /* Clamp down the PARange to the IPA size the kernel supports. */ + uint8_t index =3D round_down_to_parange_index(ipa_size); + id_aa64mmfr0 =3D GET_IDREG(isar, ID_AA64MMFR0); + id_aa64mmfr0 =3D (id_aa64mmfr0 & ~R_ID_AA64MMFR0_PARANGE_MASK) | index; + SET_IDREG(isar, ID_AA64MMFR0, id_aa64mmfr0); +} + int whpx_init_vcpu(CPUState *cpu) { HRESULT hr; @@ -738,6 +773,7 @@ int whpx_init_vcpu(CPUState *cpu) val.Reg64 =3D deposit64(arm_cpu->mp_affinity, 31, 1, 1 /* RES1 */); whpx_set_reg(cpu, WHvArm64RegisterMpidrEl1, val); =20 + clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar); return 0; =20 error: @@ -760,6 +796,8 @@ int whpx_accel_init(AccelState *as, MachineState *ms) UINT32 whpx_cap_size; WHV_PARTITION_PROPERTY prop; WHV_CAPABILITY_FEATURES features =3D {0}; + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + int pa_range =3D 0; =20 whpx =3D &whpx_global; /* on arm64 Windows Hypervisor Platform, vGICv3 always used */ @@ -770,6 +808,13 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } =20 + if (mc->whpx_get_physical_address_range) { + pa_range =3D mc->whpx_get_physical_address_range(ms); + if (pa_range < 0) { + return -EINVAL; + } + } + whpx->mem_quota =3D ms->ram_size; =20 hr =3D whp_dispatch.WHvGetCapability( diff --git a/target/arm/whpx/whpx-stub.c b/target/arm/whpx/whpx-stub.c new file mode 100644 index 0000000000..32e434a5f6 --- /dev/null +++ b/target/arm/whpx/whpx-stub.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * WHPX stubs for ARM + * + * Copyright (c) 2025 Mohamed Mediouni + * + */ + +#include "qemu/osdep.h" +#include "whpx_arm.h" + +uint32_t whpx_arm_get_ipa_bit_size(void) +{ + g_assert_not_reached(); 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bh=EvfkgLBMZk75kDKUNUYe7ztU0SJwfZDhSVhp7kNA1Bg=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=OM2iAAHrLEBAt45EDSq04oVDlYFgKUYM/Z5LeWEKZqi4qpu7ACUgn0BMOOWzdBr2NN70zoz4uvKG/Y4xhJL/a6EqffyDnAtItD1ijg/RQK7s0O2SuL5EEZslqQpHLsW5X5tVMuPzlH7flqRRW5ErL1xokhsK77tcgKX0rI9i45xEKdfDzz5nFMESXPpuftDm6FXc5dGqZsytalUD9+dRm2FFZ+tRC/g68x6bnQGv8n+aUPO4GJHlPfw7g8RbjHTieUnoT79RRxpHz0wjY+Ddr4JRb7WVX0Yb6+bCk8NNpFGO4+RxxOWcSZPrhg9xPfVJzG9CVkzVio2MP06NaiuqYw== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. Tsirkin" , Igor Mammedov , Paolo Bonzini , Yanan Wang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Shannon Zhao , kvm@vger.kernel.org, Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pedro Barbuda , Zhao Liu , Roman Bolshakov , Pierrick Bouvier Subject: [PATCH v7 18/24] hw/arm, accel/hvf, whpx: unify get_physical_address_range between WHPX and HVF Date: Thu, 16 Oct 2025 18:55:14 +0200 Message-ID: <20251016165520.62532-19-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251016165520.62532-1-mohamed@unpredictable.fr> References: <20251016165520.62532-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE2MDEyMiBTYWx0ZWRfX9BnjlnrG2SXB 4vXvD3tljoB/8EPjb2NDsKFZg+umAmJ3bu6XagXv3LZsewJgqQ7tIbaGxElbgpwruC/hyANOiEG mC2LadszqwTm8N0jccasU8RzYznmZrktS2dZIZ+p4iGTldEJ+s7rNho2hDv45qiFD2WpbeNNlph hC/i+Yc8UUIMa14UwxOWXCq50R5GUdL+vcW5Dh67UWwGgaWkPQzcLlFNGlSuwLv2pTjdzzzHp5R rBnfbIaEVOqMYWdRxYyGGUqjWDen2bYI46PNPGKpaN7lvP2gMrOki5+30ClM7P5r/xft4xcSU= X-Proofpoint-ORIG-GUID: OW7G9dVrtnx1hovaxOM4K6hwZdjwEm0N X-Proofpoint-GUID: OW7G9dVrtnx1hovaxOM4K6hwZdjwEm0N X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 bulkscore=0 mlxlogscore=999 malwarescore=0 mlxscore=0 clxscore=1030 spamscore=0 suspectscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510160122 X-JNJ: AAAAAAABVC1/mVdf9ypQyBeCA5NOMJuKQQY1lK7CuJuXYq1jmmcoLL4lBmdyCHeeSTTCvlJ0TMxAy8rI883dDIEXl27yHhmt5Wn+Ro9v++DD3nsJCI6mQvS47hgIsOOMia9J/LKtpgChVuwXudmWPwROD83hDqnzyARe7lXhP1JTG2ToTqdR2o8gout+8wSTZw2Tl7nvan6+wDEnm+JjmhEOsiV7EC0RF/QbGQG6bBpMoJe+5hvrLpGme9/H0iFkyxVbxMimVzN11tpHoQozrLoYX1s4CPDBeJRN1nIUEK53tLBxjYiKqzNUu4x4qJX5qCVArjE+2b0dAjUrepTkrYMoLfewTqZXB8ghJtZIn77i421K48O45RIhz/Sg6njK001mfBHGnqPpSnPik/2TTus3AUS97wbtXoUW46ZD96QDKI1Bl59E+4I+qbSfcUK1fTaA+bBQzGgBrrrjAR6wObjeAZ28dr/lMrSO551FcAcGv5ai6rcgxDeh2DcrokAvuZvzsnsu/iP0FPcHRt7b2nyd1Gmu/GSdBhpfh+L9bYY1KWh6j8zFaaBzhjl0Ef8Jm0TB94ysHOzsTNwCnJbM/HMXenQ0vIYwF8fBs7HfN8qZjwi6ch9ZMdl7JBW7A1TyDfGbPzyVsS5wLiVZb5eMQOUfiaJ8EfIvwHG6Oy8Zs93CL6WYrcJ4+Kx9jZhMsRByX1YyeeFeF+dlLQrayfNCA5YSYY/Ht9mYsV8cg406Wfm7LuInPjZJ9JCRy2Gk01EQ256YonSunkR9y68+mn9GNuRR00e+jKC80JM6DY9+QkJnOFwlvjel5UckgNpuBcmJtHNl4h7bIpCPVms7piRrWUEBMLL20UzYM7pMrb1czevbvTenznYfKn61I1ge2e0jAz3wQsQueHYexMi3CSeOfrWlTXiBaOPHLVnv5NSD/rJT2d1jD4fJFDdWfuMyguQ= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.76.64; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760634342261158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- accel/hvf/hvf-all.c | 7 +++++-- hw/arm/virt.c | 41 ++++---------------------------------- include/hw/boards.h | 4 ++-- include/system/hvf_int.h | 2 ++ target/arm/hvf-stub.c | 20 ------------------- target/arm/hvf/hvf.c | 6 +++--- target/arm/hvf_arm.h | 3 --- target/arm/whpx/whpx-all.c | 5 +++-- target/i386/hvf/hvf.c | 11 ++++++++++ 9 files changed, 30 insertions(+), 69 deletions(-) delete mode 100644 target/arm/hvf-stub.c diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c index 0a4b498e83..8229ad8640 100644 --- a/accel/hvf/hvf-all.c +++ b/accel/hvf/hvf-all.c @@ -17,6 +17,7 @@ #include "system/hvf_int.h" #include "hw/core/cpu.h" #include "hw/boards.h" +#include "target/arm/hvf_arm.h" #include "trace.h" =20 bool hvf_allowed; @@ -256,8 +257,10 @@ static int hvf_accel_init(AccelState *as, MachineState= *ms) int pa_range =3D 36; MachineClass *mc =3D MACHINE_GET_CLASS(ms); =20 - if (mc->hvf_get_physical_address_range) { - pa_range =3D mc->hvf_get_physical_address_range(ms); + + if (mc->get_physical_address_range) { + pa_range =3D mc->get_physical_address_range(ms, + hvf_arch_get_default_ipa_bit_size(), hvf_arch_get_max_ipa_bit_= size()); if (pa_range < 0) { return -EINVAL; } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b6b3e37f33..d3dd36908a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3258,43 +3258,11 @@ static int virt_kvm_type(MachineState *ms, const ch= ar *type_str) return fixed_ipa ? 0 : requested_pa_size; } =20 -static int virt_whpx_get_physical_address_range(MachineState *ms) +static int virt_get_physical_address_range(MachineState *ms, + int default_ipa_size, int max_ipa_size) { VirtMachineState *vms =3D VIRT_MACHINE(ms); =20 - int max_ipa_size =3D whpx_arm_get_ipa_bit_size(); - - /* We freeze the memory map to compute the highest gpa */ - virt_set_memmap(vms, max_ipa_size); - - int requested_ipa_size =3D 64 - clz64(vms->highest_gpa); - - /* - * If we're <=3D the default IPA size just use the default. - * If we're above the default but below the maximum, round up to - * the maximum. hvf_arm_get_max_ipa_bit_size() conveniently only - * returns values that are valid ARM PARange values. - */ - if (requested_ipa_size <=3D max_ipa_size) { - requested_ipa_size =3D max_ipa_size; - } else { - error_report("-m and ,maxmem option values " - "require an IPA range (%d bits) larger than " - "the one supported by the host (%d bits)", - requested_ipa_size, max_ipa_size); - return -1; - } - - return requested_ipa_size; -} - -static int virt_hvf_get_physical_address_range(MachineState *ms) -{ - VirtMachineState *vms =3D VIRT_MACHINE(ms); - - int default_ipa_size =3D hvf_arm_get_default_ipa_bit_size(); - int max_ipa_size =3D hvf_arm_get_max_ipa_bit_size(); - /* We freeze the memory map to compute the highest gpa */ virt_set_memmap(vms, max_ipa_size); =20 @@ -3303,7 +3271,7 @@ static int virt_hvf_get_physical_address_range(Machin= eState *ms) /* * If we're <=3D the default IPA size just use the default. * If we're above the default but below the maximum, round up to - * the maximum. hvf_arm_get_max_ipa_bit_size() conveniently only + * the maximum. hvf_arch_get_max_ipa_bit_size() conveniently only * returns values that are valid ARM PARange values. */ if (requested_ipa_size <=3D default_ipa_size) { @@ -3379,8 +3347,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) mc->valid_cpu_types =3D valid_cpu_types; mc->get_default_cpu_node_id =3D virt_get_default_cpu_node_id; mc->kvm_type =3D virt_kvm_type; - mc->hvf_get_physical_address_range =3D virt_hvf_get_physical_address_r= ange; - mc->whpx_get_physical_address_range =3D virt_whpx_get_physical_address= _range; + mc->get_physical_address_range =3D virt_get_physical_address_range; assert(!mc->get_hotplug_handler); mc->get_hotplug_handler =3D virt_machine_get_hotplug_handler; hc->pre_plug =3D virt_machine_device_pre_plug_cb; diff --git a/include/hw/boards.h b/include/hw/boards.h index 3d01fb8cc9..aecf5ca92e 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -275,8 +275,8 @@ struct MachineClass { void (*reset)(MachineState *state, ResetType type); void (*wakeup)(MachineState *state); int (*kvm_type)(MachineState *machine, const char *arg); - int (*hvf_get_physical_address_range)(MachineState *machine); - int (*whpx_get_physical_address_range)(MachineState *machine); + int (*get_physical_address_range)(MachineState *machine, + int default_ipa_size, int max_ipa_size); =20 BlockInterfaceType block_default_type; int units_per_default_bus; diff --git a/include/system/hvf_int.h b/include/system/hvf_int.h index a3b06a3e75..8b6447c238 100644 --- a/include/system/hvf_int.h +++ b/include/system/hvf_int.h @@ -71,6 +71,8 @@ void assert_hvf_ok_impl(hv_return_t ret, const char *file= , unsigned int line, const char *hvf_return_string(hv_return_t ret); int hvf_arch_init(void); hv_return_t hvf_arch_vm_create(MachineState *ms, uint32_t pa_range); +uint32_t hvf_arch_get_default_ipa_bit_size(void); +uint32_t hvf_arch_get_max_ipa_bit_size(void); int hvf_arch_init_vcpu(CPUState *cpu); void hvf_arch_vcpu_destroy(CPUState *cpu); int hvf_vcpu_exec(CPUState *); diff --git a/target/arm/hvf-stub.c b/target/arm/hvf-stub.c deleted file mode 100644 index ff137267a0..0000000000 --- a/target/arm/hvf-stub.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * QEMU Hypervisor.framework (HVF) stubs for ARM - * - * Copyright (c) Linaro - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#include "qemu/osdep.h" -#include "hvf_arm.h" - -uint32_t hvf_arm_get_default_ipa_bit_size(void) -{ - g_assert_not_reached(); -} - -uint32_t hvf_arm_get_max_ipa_bit_size(void) -{ - g_assert_not_reached(); -} diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 0658a99a2d..ecca1a63ec 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -725,7 +725,7 @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt) static void clamp_id_aa64mmfr0_parange_to_ipa_size(ARMISARegisters *isar) { uint32_t ipa_size =3D chosen_ipa_bit_size ? - chosen_ipa_bit_size : hvf_arm_get_max_ipa_bit_size(); + chosen_ipa_bit_size : hvf_arch_get_max_ipa_bit_size(); uint64_t id_aa64mmfr0; =20 /* Clamp down the PARange to the IPA size the kernel supports. */ @@ -816,7 +816,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) return r =3D=3D HV_SUCCESS; } =20 -uint32_t hvf_arm_get_default_ipa_bit_size(void) +uint32_t hvf_arch_get_default_ipa_bit_size(void) { uint32_t default_ipa_size; hv_return_t ret =3D hv_vm_config_get_default_ipa_size(&default_ipa_siz= e); @@ -825,7 +825,7 @@ uint32_t hvf_arm_get_default_ipa_bit_size(void) return default_ipa_size; } =20 -uint32_t hvf_arm_get_max_ipa_bit_size(void) +uint32_t hvf_arch_get_max_ipa_bit_size(void) { uint32_t max_ipa_size; hv_return_t ret =3D hv_vm_config_get_max_ipa_size(&max_ipa_size); diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h index ea82f2691d..5d19d82e5d 100644 --- a/target/arm/hvf_arm.h +++ b/target/arm/hvf_arm.h @@ -22,7 +22,4 @@ void hvf_arm_init_debug(void); =20 void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu); =20 -uint32_t hvf_arm_get_default_ipa_bit_size(void); -uint32_t hvf_arm_get_max_ipa_bit_size(void); - #endif diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 62fd6c230a..19513b50a3 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -808,8 +808,9 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } =20 - if (mc->whpx_get_physical_address_range) { - pa_range =3D mc->whpx_get_physical_address_range(ms); + if (mc->get_physical_address_range) { + pa_range =3D mc->get_physical_address_range(ms, + whpx_arm_get_ipa_bit_size(), whpx_arm_get_ipa_bit_size()); if (pa_range < 0) { return -EINVAL; } diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 8445cadece..0994b8643d 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -225,6 +225,17 @@ int hvf_arch_init(void) return 0; } =20 +/* 48-bit on all Intel Macs. Function currently unused. */ +uint32_t hvf_arch_get_default_ipa_bit_size(void) +{ + g_assert_not_reached(); +} + +uint32_t hvf_arch_get_max_ipa_bit_size(void) +{ + g_assert_not_reached(); +} + hv_return_t hvf_arch_vm_create(MachineState *ms, uint32_t pa_range) { return hv_vm_create(HV_VM_DEFAULT); --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1760633951; cv=none; d=zohomail.com; s=zohoarc; b=ZW29sqkW28d7X7FcmIm1srR8Ez4jH3Hr8lcaYYaJOREM40rQ5GyaqeZ8VBXZBhRpNyEBAzk/1kktyoztLQ8BEzR8fGCXymobvEvOvB8RTuJ8v36dT+g/RUh4ZueD3amFRs83jJjIijaQeKvu7CilbfGlSroyWjSgxCa52a/dFFE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760633951; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PPb8dlcuMo+VEVLq+WaUpAP0KWKymP1yw5xY57lCVP0=; b=hUrJkfCts2t8lTutJ/QhVt5na6G84swJtN+bzFoFhyhSIb+E+ZaPP7yhHZpr5A6TwUZk7dAxyWfMUrt9CZfjtkm1Mq/Pc5xGi6TYb4eSl7ppbFM1Lps0PVbnAQmpms++prGvjXnsd6RodpZm9anb7Z6GDBBRB3ntz6yJ6TinbP4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760633951421585.6874508898079; Thu, 16 Oct 2025 09:59:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v9RIr-0001EO-GV; Thu, 16 Oct 2025 12:58:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RIk-0001CW-9O for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:58:06 -0400 Received: from p-east2-cluster1-host7-snip4-4.eps.apple.com ([57.103.76.67] helo=outbound.st.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RII-0001eV-Gf for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:58:04 -0400 Received: from outbound.st.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPS id 3C32B18001DF; Thu, 16 Oct 2025 16:57:30 +0000 (UTC) Received: from localhost.localdomain (unknown [17.42.251.67]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPSA id 00B2018001F5; Thu, 16 Oct 2025 16:56:27 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=PPb8dlcuMo+VEVLq+WaUpAP0KWKymP1yw5xY57lCVP0=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=B5ga6ScjYDJcp4chLCCMzwZXM5HFmxqDWr0WDic7bbMnIShjbiBha5isz2AY8vXKSnpYm2ZvZkQI0D6NqTi1C3oitgRCQv+X3vqVNPvvEz/PbOFeNyHWkaiK6pLfoCi+mQu3VN1+VwJiLTFbEsJCIp9O8ZC7DUNPz6rc0N4KfNyWnzG9NZBlXOBivv4z1e5/aENMbRDQRb8LHM3THzgbgLxaH8kBgMsNp10qyqqhUz5HK+NvreuToTcxds90AafOnUDTsAdSzc8a0M466qY0Aqa/STti0aAtdQ6Q0HlWuFSqqzxgEIj4c3pks1HmlN7kWBycB+LkkxgM4O1qkNph1w== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.76.67; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760633953628158500 Content-Type: text/plain; charset="utf-8" Logic to fetch MIDR_EL1 for cpu 0 adapted from: https://github.com/FEX-Emu/FEX/blob/e6de17e72ef03aa88ba14fa0ec13163061608c7= 4/Source/Windows/Common/CPUFeatures.cpp#L62 Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- hw/arm/virt.c | 2 +- target/arm/cpu64.c | 19 ++++--- target/arm/whpx/whpx-all.c | 104 +++++++++++++++++++++++++++++++++++++ target/arm/whpx_arm.h | 1 + 4 files changed, 119 insertions(+), 7 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d3dd36908a..1904765db3 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3312,7 +3312,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) #ifdef TARGET_AARCH64 ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) || defined(CONFIG_WHPX) ARM_CPU_TYPE_NAME("host"), #endif /* CONFIG_KVM || CONFIG_HVF */ #endif /* TARGET_AARCH64 */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 26cf7e6dfa..3f00071081 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -26,10 +26,13 @@ #include "qemu/units.h" #include "system/kvm.h" #include "system/hvf.h" +#include "system/whpx.h" +#include "system/hw_accel.h" #include "system/qtest.h" #include "system/tcg.h" #include "kvm_arm.h" #include "hvf_arm.h" +#include "whpx_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" #include "internals.h" @@ -522,7 +525,7 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) isar2 =3D FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0); isar2 =3D FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0); =20 - if (kvm_enabled() || hvf_enabled()) { + if (hwaccel_enabled()) { /* * Exit early if PAuth is enabled and fall through to disable it. * The algorithm selection properties are not present. @@ -599,10 +602,10 @@ void aarch64_add_pauth_properties(Object *obj) =20 /* Default to PAUTH on, with the architected algorithm on TCG. */ qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); - if (kvm_enabled() || hvf_enabled()) { + if (hwaccel_enabled()) { /* * Mirror PAuth support from the probed sysregs back into the - * property for KVM or hvf. Is it just a bit backward? Yes it is! + * property for HW accel. Is it just a bit backward? Yes it is! * Note that prop_pauth is true whether the host CPU supports the * architected QARMA5 algorithm or the IMPDEF one. We don't * provide the separate pauth-impdef property for KVM or hvf, @@ -773,6 +776,10 @@ static void aarch64_host_initfn(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); hvf_arm_set_cpu_features_from_host(cpu); aarch64_add_pauth_properties(obj); +#elif defined(CONFIG_WHPX) + ARMCPU *cpu =3D ARM_CPU(obj); + whpx_arm_set_cpu_features_from_host(cpu); + aarch64_add_pauth_properties(obj); #else g_assert_not_reached(); #endif @@ -780,8 +787,8 @@ static void aarch64_host_initfn(Object *obj) =20 static void aarch64_max_initfn(Object *obj) { - if (kvm_enabled() || hvf_enabled()) { - /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ + if (hwaccel_enabled()) { + /* When hardware acceleration enabled, '-cpu max' is identical to = '-cpu host' */ aarch64_host_initfn(obj); return; } @@ -800,7 +807,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) || defined(CONFIG_WHPX) { .name =3D "host", .initfn =3D aarch64_host_initfn }, #endif }; diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 19513b50a3..680954f4b5 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -41,6 +41,17 @@ =20 #include #include +#include + +typedef struct ARMHostCPUFeatures { + ARMISARegisters isar; + uint64_t features; + uint64_t midr; + uint32_t reset_sctlr; + const char *dtb_compatible; +} ARMHostCPUFeatures; + +static ARMHostCPUFeatures arm_host_cpu_features; =20 struct whpx_reg_match { WHV_REGISTER_NAME reg; @@ -695,6 +706,99 @@ static void clamp_id_aa64mmfr0_parange_to_ipa_size(ARM= ISARegisters *isar) SET_IDREG(isar, ID_AA64MMFR0, id_aa64mmfr0); } =20 +static uint64_t whpx_read_midr(void) +{ + HKEY key; + uint64_t midr_el1; + DWORD size =3D sizeof(midr_el1); + const char *path =3D "Hardware\\Description\\System\\CentralProcessor\= \0\\"; + assert(!RegOpenKeyExA(HKEY_LOCAL_MACHINE, path, 0, KEY_READ, &key)); + assert(!RegGetValueA(key, NULL, "CP 4000", RRF_RT_REG_QWORD, NULL, &mi= dr_el1, &size)); + RegCloseKey(key); + return midr_el1; +} + +static bool whpx_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) +{ + const struct isar_regs { + WHV_REGISTER_NAME reg; + uint64_t *val; + } regs[] =3D { + { WHvArm64RegisterIdAa64Pfr0El1, &ahcf->isar.idregs[ID_AA64PFR0_EL= 1_IDX] }, + { WHvArm64RegisterIdAa64Pfr1El1, &ahcf->isar.idregs[ID_AA64PFR1_EL= 1_IDX] }, + { WHvArm64RegisterIdAa64Dfr0El1, &ahcf->isar.idregs[ID_AA64DFR0_EL= 1_IDX] }, + { WHvArm64RegisterIdAa64Dfr1El1 , &ahcf->isar.idregs[ID_AA64DFR1_E= L1_IDX] }, + { WHvArm64RegisterIdAa64Isar0El1, &ahcf->isar.idregs[ID_AA64ISAR0_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Isar1El1, &ahcf->isar.idregs[ID_AA64ISAR1_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Isar2El1, &ahcf->isar.idregs[ID_AA64ISAR2_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Mmfr0El1, &ahcf->isar.idregs[ID_AA64MMFR0_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Mmfr1El1, &ahcf->isar.idregs[ID_AA64MMFR1_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Mmfr2El1, &ahcf->isar.idregs[ID_AA64MMFR2_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Mmfr3El1, &ahcf->isar.idregs[ID_AA64MMFR2_= EL1_IDX] } + }; + + int i; + WHV_REGISTER_VALUE val; + + ahcf->dtb_compatible =3D "arm,armv8"; + ahcf->features =3D (1ULL << ARM_FEATURE_V8) | + (1ULL << ARM_FEATURE_NEON) | + (1ULL << ARM_FEATURE_AARCH64) | + (1ULL << ARM_FEATURE_PMU) | + (1ULL << ARM_FEATURE_GENERIC_TIMER); + + for (i =3D 0; i < ARRAY_SIZE(regs); i++) { + clean_whv_register_value(&val); + whpx_get_global_reg(regs[i].reg, &val); + *regs[i].val =3D val.Reg64; + } + + /* + * MIDR_EL1 is not a global register on WHPX + * As such, read the CPU0 from the registry to get a consistent value. + * Otherwise, on heterogenous systems, you'll get variance between CPU= s. + */ + ahcf->midr =3D whpx_read_midr(); + + clamp_id_aa64mmfr0_parange_to_ipa_size(&ahcf->isar); + + /* + * Disable SVE, which is not supported by QEMU whpx yet. + * Work needed for SVE support: + * - SVE state save/restore + * - any potentially needed VL management + * Also disable SME at the same time. (not currently supported by Hype= r-V) + */ + SET_IDREG(&ahcf->isar, ID_AA64PFR0, + GET_IDREG(&ahcf->isar, ID_AA64PFR0) & ~R_ID_AA64PFR0_SVE_MAS= K); + + SET_IDREG(&ahcf->isar, ID_AA64PFR1, + GET_IDREG(&ahcf->isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MAS= K); + + return true; +} + +void whpx_arm_set_cpu_features_from_host(ARMCPU *cpu) +{ + if (!arm_host_cpu_features.dtb_compatible) { + if (!whpx_enabled() || + !whpx_arm_get_host_cpu_features(&arm_host_cpu_features)) { + /* + * We can't report this error yet, so flag that we need to + * in arm_cpu_realizefn(). + */ + cpu->host_cpu_probe_failed =3D true; + return; + } + } + + cpu->dtb_compatible =3D arm_host_cpu_features.dtb_compatible; + cpu->isar =3D arm_host_cpu_features.isar; + cpu->env.features =3D arm_host_cpu_features.features; + cpu->midr =3D arm_host_cpu_features.midr; + cpu->reset_sctlr =3D arm_host_cpu_features.reset_sctlr; +} + int whpx_init_vcpu(CPUState *cpu) { HRESULT hr; diff --git a/target/arm/whpx_arm.h b/target/arm/whpx_arm.h index de7406b66f..df65fd753c 100644 --- a/target/arm/whpx_arm.h +++ b/target/arm/whpx_arm.h @@ -12,5 +12,6 @@ #include "target/arm/cpu-qom.h" =20 uint32_t whpx_arm_get_ipa_bit_size(void); +void whpx_arm_set_cpu_features_from_host(ARMCPU *cpu); =20 #endif --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1760634041; cv=none; d=zohomail.com; s=zohoarc; b=Mav2ke278Oj7GFF4xs3MxCiN7NJjDuqLw2Cnl6+Iy0VnaEWB06axvbmL6iLrVhTtiHncFGrSnqvb8tVQIk8Q7+Er8sccccA4Hu5pFmIANGZKScUhY2xe6pm4/6cjoAOsOjuscHcSayUOgYMJmk8JSQW5pFXv/7G5Og/Dx4NCC60= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760634041; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=XY0aRLNzrnTUVd3ei9jMIMiM8ijXecVFkp2kgf3sj3c=; b=WnwQG+5rYXPFo4yUPGL5CC25nGFA6gAacgT5u7iwpUGmo/mtztJjtUWZToKNYEy1vkWWGPiSH1q6eC/PviQSH2qVEi60Imxo20IdOI2dgwZntEqecMxvWQ0vBR0gDl6caFUpBI3mqCwz0gVDVqxo3Stq1Ys2MXOr5c0oub/59Bs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760634041454713.5557948565126; Thu, 16 Oct 2025 10:00:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v9RJB-0001ee-UB; Thu, 16 Oct 2025 12:58:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RJ5-0001X1-4W for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:58:28 -0400 Received: from p-east2-cluster1-host11-snip4-5.eps.apple.com ([57.103.76.48] helo=outbound.st.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RIS-0001gI-WF for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:58:14 -0400 Received: from outbound.st.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPS id 31CF318004AF; Thu, 16 Oct 2025 16:57:32 +0000 (UTC) Received: from localhost.localdomain (unknown [17.42.251.67]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPSA id 4E7CC18015F9; Thu, 16 Oct 2025 16:56:31 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=XY0aRLNzrnTUVd3ei9jMIMiM8ijXecVFkp2kgf3sj3c=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=G5fbOyvHJVvgmn47PEMp7WVDlwecLoNfGzreo6Ra1tG5G9dXBpnH+HBzlIIoE2Q3h4mlwGsBzbCs+TJ28RVpf/wtI1FxhP6nWXJehu897bNb8rQPJfVEFZm/aILvM47OQWa9XGV1dBoHZhj1vHEmsrDPj/wzcNu9E4uEkjZh5WJt6GhgwV0kz3wtut+BdvMpulXBO4fW2cj+qn/Ew96tJtb8mnboZiUyJpo3RaEbXNa+Jl9JKFpQz9I8QLk2GjkWpQiHlOHVhxwKZkw4k92+bxjAJbYeXgN/Lh2KCs367PvXaBEfBTrETXLJEt+8y0LIbfeq5vqbRzey+m5WqssPsg== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. Tsirkin" , Igor Mammedov , Paolo Bonzini , Yanan Wang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Shannon Zhao , kvm@vger.kernel.org, Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pedro Barbuda , Zhao Liu , Roman Bolshakov , Pierrick Bouvier Subject: [PATCH v7 20/24] target/arm: whpx: instantiate GIC early Date: Thu, 16 Oct 2025 18:55:16 +0200 Message-ID: <20251016165520.62532-21-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251016165520.62532-1-mohamed@unpredictable.fr> References: <20251016165520.62532-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE2MDEyMyBTYWx0ZWRfX5RPg22SuOdaV ZtTU4QVzU7686asx7bCXjsWGnA7izvNqLIwCdj/7CqqAxyL7JE/2PatujnSg5x5YMQBNLmddTzf 54acd03G9sAO6QwtiYwOR9GBwBN3vHaOZzJdefLudxb9q4ISDOXv4pTVvAbZWSVZh4enlOEewOl l3ooDrDSb+RPU06eAkd/JeHEvFGQoth1+YTpdKa7qb/C1X6ulBgilRLxsbzq+Iu4atTFG4yO0Jc Utr/y6SQr+iLLmX9JymHamL2+4b11WRnsl1vNwc8MAtsgKDZEEpC3JRaqdTFSC42YLXt1Wj7A= X-Proofpoint-GUID: lPwsSiVTqUh4yKtd54TOrkzbe0fpD3CF X-Proofpoint-ORIG-GUID: lPwsSiVTqUh4yKtd54TOrkzbe0fpD3CF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=700 clxscore=1030 phishscore=0 malwarescore=0 spamscore=0 mlxscore=0 adultscore=0 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510160123 X-JNJ: AAAAAAABRqlvR0HOYZmVSAMe64xMp24ydQMh0BLfmwizl1Z6qWJPTXy29Ke4PBngEdTirCepez5QG64/oUzy3Up3ADBkfnYlOWIZwadRqErq76oeLLIXYjKCCH4OXqgGH2Ve5QLQuwUCBtRro6Gxji6lEdiDFjxM19uNyrro7K8AgTvYIjSB18dIJhqRcSbohJIsKf3jZDsDsdSPr6Qo4NMwxSbsusL3B8rlEbia8dqWBoiURngsrBrLfbe6QCmMbP7mWboKRiMwJ+LqwkDDSTAMqgSJWbeFpOfqjxY6Vt8tUg1781WPVLgwSZkxrYGdkugkeAbKLUE25cfLXI7Rooizu7Pcl2pgHuYmP9S0R5vN2y1tmUG92gZbVSEX3JcQpUzltRDX/BBqB8TyvaxFN5w96FXuC6ddtHHYdbDKCXo+zmpAQYkjrfbqJnM6wjFc3Y+ChUsBQA6tTYp/xQDtRrfCDbhVFUsUxi4YZgLL29GoAa0Pt2dAWJe1krh0XqPnmc1bdhBUHvjd4hjuNCO0lagp6GjKgj6432zRJOUqV/kaQGeCAQyHwrJBvGlkccIw/l/5jr5xL6ZzVAciJPdu+XJoO+afX5VvtkHx/CSxgl9pP3nK2LCKyJtUawjWGaCSy8H22FqT59vb4RNvwNAii8sIVqEmWeBenlWqVxBVO1bbBhvy5aCehHqxMlDmnLbVrnaQXEPZi4OwaFYH15P1kvQr/BDpoiyiC7uloHUJPOF9DzQn5QxEBI/Zi1oVkjADUxCtiJmVTmZ/q1xT/nV99IMvWiTQNzYcPr2iyXWOGjSxss2a1LcgrwnKQLfUIXMIXe2+b39jFlrByb07NRDNNxCYPuo/4J2WPVgATItp9K+TaeRwjyIcdC8RrKGxDS+o/KXMhQdiB/KP3AsxxtUDs2Y= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.76.48; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760634042576154100 Content-Type: text/plain; charset="utf-8" While figuring out a better spot for it, put it in whpx_accel_init. Needs to be done before WHvSetupPartition. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- target/arm/whpx/whpx-all.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 680954f4b5..12d397f35e 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -976,6 +976,29 @@ int whpx_accel_init(AccelState *as, MachineState *ms) =20 memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY)); =20 + WHV_ARM64_IC_PARAMETERS ic_params =3D { + .EmulationMode =3D WHvArm64IcEmulationModeGicV3, + .GicV3Parameters =3D { + .GicdBaseAddress =3D 0x08000000, + .GitsTranslaterBaseAddress =3D 0x08080000, + .GicLpiIntIdBits =3D 0, + .GicPpiPerformanceMonitorsInterrupt =3D VIRTUAL_PMU_IRQ, + .GicPpiOverflowInterruptFromCntv =3D ARCH_TIMER_VIRT_IRQ + } + }; + prop.Arm64IcParameters =3D ic_params; + + hr =3D whp_dispatch.WHvSetPartitionProperty( + whpx->partition, + WHvPartitionPropertyCodeArm64IcParameters, + &prop, + sizeof(WHV_PARTITION_PROPERTY)); + if (FAILED(hr)) { + error_report("WHPX: Failed to enable GICv3 interrupt controller, h= r=3D%08lx", hr); + ret =3D -EINVAL; + goto error; + } + hr =3D whp_dispatch.WHvSetupPartition(whpx->partition); if (FAILED(hr)) { error_report("WHPX: Failed to setup partition, hr=3D%08lx", hr); --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1760633956; cv=none; d=zohomail.com; s=zohoarc; b=jmUM3OiJjSaQdArUzqFmGjnGvrmT1CMvSD2l0R0aamQGjzZ7GcEDMC1mqGrIjLRuE6S4bJ1/10Wuj+y4xKBxjq9i5XDRmfxKkWFSDgO1W4RRr3kFvQgivfPheqt8TTvg1aZ7ERzSy5uMQKn84t6VZ2vyxeK7R3jMUosrGu31hwo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760633956; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nzWfz+yWdE38Km+dQsZKqvSOWpOIi0Tms+2rrM0SehM=; b=HmNrocAcOxBj/SIvSchzd6/P8ByYDQwbxLFzVhnP13RWNyuSu46DaPdBZ/LF63hLcXcJiwiYBjYwOXhV4GD42qWq0A2oE2D61kuMskKK4bGesv3ROTdgni3iIo7rFAuRTKUt2+12z9pgJjRZUQia5VmvBXc3lnXy5afKcqbFrI0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760633956379525.6852188222377; Thu, 16 Oct 2025 09:59:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v9RJ1-0001OQ-F8; Thu, 16 Oct 2025 12:58:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RIp-0001Eq-RY for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:58:12 -0400 Received: from p-east2-cluster1-host12-snip4-10.eps.apple.com ([57.103.76.63] helo=outbound.st.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RIR-0001g3-Ri for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:58:10 -0400 Received: from outbound.st.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPS id 3066918015FE; Thu, 16 Oct 2025 16:57:39 +0000 (UTC) Received: from localhost.localdomain (unknown [17.42.251.67]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPSA id B98511800760; Thu, 16 Oct 2025 16:56:34 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=nzWfz+yWdE38Km+dQsZKqvSOWpOIi0Tms+2rrM0SehM=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=KGg3sgIOKcnQqiLDH2kAbjPth2rJxYcfhocZDr/O2uJWt+38QFuRoJ2Z97btAPo29Q+zzxC7eBMkT+EAi1g4K1JZgb2Xlv2g7huRMRbE4VxYJf/t7LCaYyL+bMR+HQ4TA/4Xsox2Cc5iCt6+x4SwE/d4Ro5bPvUWq5O4OXhJVt4+mXQHtEMlO/bnd+3uaQqcLjVMfut/He67wfEs+V8pRQMSuyXWzFiw3krcABCk6ACFyb7cluLQ065wADNZtBGXMm5Xf4Gqj7HWdoWYK8PPMJP5O/mdcZUOElt94TwJR+pffVXFLMh6a05z/oZJxLRsbav8IIn6IlGW1EyGmcH0yA== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. Tsirkin" , Igor Mammedov , Paolo Bonzini , Yanan Wang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Shannon Zhao , kvm@vger.kernel.org, Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pedro Barbuda , Zhao Liu , Roman Bolshakov Subject: [PATCH v7 21/24] whpx: arm64: gicv3: add migration blocker Date: Thu, 16 Oct 2025 18:55:17 +0200 Message-ID: <20251016165520.62532-22-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251016165520.62532-1-mohamed@unpredictable.fr> References: <20251016165520.62532-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: t8Aq89xlJQFujfMgbbyJbEK71dJavbvS X-Proofpoint-GUID: t8Aq89xlJQFujfMgbbyJbEK71dJavbvS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE2MDEyMiBTYWx0ZWRfX9bS4A67yelyI RPZX5eVoHpWWSdYypK3vWXGTViKzcX2/4idbfxJDkfAdGArRs6vyiQpr36nEs4CG2JSrlRe7Q6D YumVBJGNknG2eCK4aO+TI86SV85hJnGakdBTkt1Eu+EeSirI2mj3QaM6f1S7Vh4WIg8S4eGCKGI NWsoOhS3iq8tdrO1BEzyv3dOdiSfgoGk4aUx3evNaAVaGFX+UfhoBjBtE7I6eIlIxz5OWZg/ejV 4T1IljcI877fYcQDHlgN6iZgnAufUReVSO5ZVUdNgEQqu7RGe+fvKmSkOc618w3KoZ8SjLa60= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 mlxlogscore=970 malwarescore=0 spamscore=0 mlxscore=0 bulkscore=0 clxscore=1030 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510160122 X-JNJ: AAAAAAAB3vmBivw56P7Bq+mQdi6xqqxbZvPE6oYdlUtVh1HgBTGJ57lyY0GfbMa3g1KH7pCQ2RRoGbFUgraxGJxWjqRjDdkRourh9MFoo1iClsIFC3g6DAfGUrYhWW1RCp3X1bHeoqSqD0ORZYRTYXDqDoXk98EO13O4tOsSRlVH3zKwk3ISzBmwqT3IaFSDMaC+1f6kc4ja3lmqIKvZtDWk/RBu6M+QCshJswkctHBL3cBDl89scKxPkqoHSioxUy48MTwgW4KPjsSJ25hR/RyL4ipa7iREgyoyJ+cBWsopHllvMMZgdR4FWLB76U5fzZ83PzvHDOAzH+ttL0JxyRi3zfMWXCJTJSHSuumiNxHTr/kK7bOlQ3U4GikwDBSye5bGUAc0KrtPVNc/05sy6e0BSi9ocE61a65CivNSE5Th340ovOI9lcobB4lYNVHj6NE4XshUlQOKzT0x7apL6WoDB+e+cr+CtGKax/RkES1ORM01jrE4SSbvv73UwgvhBbdOwBAp9jv2ZF0O2Jraefj25y6kbCO1/nXSd8xIJLXd5eXXpIgfH4439cLk6GPy1OEoe8nfF42J3pjTDifzZQMivtkRy3j6wcaed8xDWMnykA8w3qC0H3MOMgowshEtYmR9gUae2kDEhk+BHhGUC392eph+rhTilAYmWeT1DDzlw8Ys71mcQpr2EQ12R4i1VE/7OHCTRnebf5//MtgFkpkUDozFwEW8eGOyGeQFGEH+mIbm0lDgOFHe06xXCeqoZJKDGixjd249y0X6GmVB/wqTzPeo3lEFRsscqsWfbEowzfP6HJr8oEh5O0rTBd0zHU/r0uufw62XbMCs/KTqhy3FJ/Uyic8rIbDWVPgY65hEcf45JLd4qIJR4F1mgK/qL/X4t4VmsJqNib+DDECcj+mJqKK7 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.76.63; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760633957526154100 Content-Type: text/plain; charset="utf-8" GICv3 state save-restore is currently not implemented yet. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- hw/intc/arm_gicv3_whpx.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/intc/arm_gicv3_whpx.c b/hw/intc/arm_gicv3_whpx.c index 88a05e5901..6ceae78483 100644 --- a/hw/intc/arm_gicv3_whpx.c +++ b/hw/intc/arm_gicv3_whpx.c @@ -17,6 +17,7 @@ #include "system/whpx-internal.h" #include "gicv3_internal.h" #include "vgic_common.h" +#include "migration/blocker.h" #include "qom/object.h" #include "target/arm/cpregs.h" =20 @@ -205,6 +206,15 @@ static void whpx_gicv3_realize(DeviceState *dev, Error= **errp) error_setg(errp, "Nested virtualisation not currently supported by= WHPX."); return; } + + Error *whpx_migration_blocker =3D NULL; + + error_setg(&whpx_migration_blocker, + "Live migration disabled because GIC state save/restore not suppor= ted on WHPX"); + if (migrate_add_blocker(&whpx_migration_blocker, errp)) { + error_free(whpx_migration_blocker); + return; + } } =20 static void whpx_gicv3_class_init(ObjectClass *klass, const void *data) --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1760634104; cv=none; d=zohomail.com; s=zohoarc; b=KfwBFxWWdlAT60/XfZfipjTBWAqrMT1tsI/6KRpNzVxfBaWQ9/ZChWKsWat0jbLot69Exp+/OH2m3TfD79pqbnjtsH1NWItsn/g7typn0qeiiQftwAYF5PHWVnLQs2CVJ5zCCcDvf2jhjTVaChSzxc30CPYLku+Cn4bxR4QothI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760634104; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/emOJC8MVUV/uiHpi2m5tS4QeiaPLM29PVhym/FdJcU=; b=iLol+ruUf4x0Xn6SPnwfpVmbb2csdHpg7w11ON7swwKLevZuo0ZYs1+pJz2bunR1yph8G3UJy/pxOdV3l+zrHPWuOmsmMfCf2qdSYBwpW8g7STUOSenVDrWp11YZgM9lc7V5PFTrzKJLn9houbNO9ljqojcBybzyIsnwuXris+Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176063410413094.9040357795036; Thu, 16 Oct 2025 10:01:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v9RJ5-0001Xz-II; Thu, 16 Oct 2025 12:58:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RIn-0001Dv-Oo for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:58:10 -0400 Received: from p-east2-cluster1-host6-snip4-10.eps.apple.com ([57.103.76.103] helo=outbound.st.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RIR-0001fh-QG for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:58:09 -0400 Received: from outbound.st.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPS id 99880180031E; Thu, 16 Oct 2025 16:57:38 +0000 (UTC) Received: from localhost.localdomain (unknown [17.42.251.67]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPSA id 131AB18015E4; Thu, 16 Oct 2025 16:56:37 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=/emOJC8MVUV/uiHpi2m5tS4QeiaPLM29PVhym/FdJcU=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=bGK6tL68CZkL65E06+61khANtcYjpq3PARdtmvowceiOa5ZPv6jgqDjp8bwc0PrldqVk0byHCWeOsPxqa2eyFj1G0AkYid5/xFxbRF/PixLXeyevvtKCMY+Hb/hlFcV/1Eg4OYvPkGeKTVP+6G14ZDp45Fe9j6Fl2H5bi/S3xt39vMM8XHjk+JA7u7hZoMexUonEUey0gXMpACgCU9JalYLDLC4jIzY3lnRB5BhFVU6V0D1TQnN0uDiYV7QRWNItizzEnL6kXPtwX0G8VaVhLqZN43jTDYxe6600lKcwsAzaBY0ARgeERQ4DUXWQCAmbOYhdV4KP/CdSTXg0Dy92IQ== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. 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charset="utf-8" Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- meson.build | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/meson.build b/meson.build index afaefa0172..51561ce020 100644 --- a/meson.build +++ b/meson.build @@ -327,7 +327,8 @@ accelerator_targets +=3D { 'CONFIG_XEN': xen_targets } =20 if cpu =3D=3D 'aarch64' accelerator_targets +=3D { - 'CONFIG_HVF': ['aarch64-softmmu'] + 'CONFIG_HVF': ['aarch64-softmmu'], + 'CONFIG_WHPX': ['aarch64-softmmu'] } elif cpu =3D=3D 'x86_64' accelerator_targets +=3D { @@ -893,13 +894,18 @@ if get_option('mshv').allowed() and host_os =3D=3D 'l= inux' endif =20 if get_option('whpx').allowed() and host_os =3D=3D 'windows' - if get_option('whpx').enabled() and host_machine.cpu() !=3D 'x86_64' - error('WHPX requires 64-bit host') - elif cc.has_header('winhvplatform.h', required: get_option('whpx')) and \ - cc.has_header('winhvemulation.h', required: get_option('whpx')) - accelerators +=3D 'CONFIG_WHPX' + if cpu =3D=3D 'i386' + if get_option('whpx').enabled() + error('WHPX requires 64-bit host') + endif + # Leave CONFIG_WHPX disabled + else + if cc.has_header('winhvplatform.h', required: get_option('whpx')) and \ + cc.has_header('winhvemulation.h', required: get_option('whpx')) + accelerators +=3D 'CONFIG_WHPX' + endif endif -endif + endif =20 hvf =3D not_found if get_option('hvf').allowed() --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Igor Mammedov , Paolo Bonzini , Yanan Wang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Shannon Zhao , kvm@vger.kernel.org, Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pedro Barbuda , Zhao Liu , Roman Bolshakov Subject: [PATCH v7 23/24] MAINTAINERS: update maintainers for WHPX Date: Thu, 16 Oct 2025 18:55:19 +0200 Message-ID: <20251016165520.62532-24-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251016165520.62532-1-mohamed@unpredictable.fr> References: <20251016165520.62532-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE2MDEyMiBTYWx0ZWRfXxVvW6wWaENS+ 2A3l3E2Virp5V14DLevwsSjjyHn9uN/EQ+TIcgB0XjAxrHwAFDpd0PtM82CkbmUiPq6oMTy1gvg f7CAAXDCGZLPGVBcaVd1q3gGJbJrkfJlA22/CA+I2toVIsLT2XSE1Wo09tl9yd5q7SYLkDGuxcH JH4M49aC7Wcz05r5QpfZeNK+wtSwPyva+5cjp11OKQA5twzd9n7D08qCx2MdcQzt0WLPJGlNzR9 QzxgiuVfopKi3rfugfwqiX9EY8mO3CtJw52S8dlh5LK0dZIg5PpxpecUVnCjl9xmg4qx+5JLg= X-Proofpoint-GUID: wJNaRMLLJzLK6FHYFfpP3tbniwg0bIlp X-Proofpoint-ORIG-GUID: wJNaRMLLJzLK6FHYFfpP3tbniwg0bIlp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 mlxlogscore=900 bulkscore=0 phishscore=0 adultscore=0 mlxscore=0 clxscore=1030 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510160122 X-JNJ: AAAAAAABBFeBE2oOJopGBuIMoX+iRngQjjVB2BEL7RjgOojp2rWGSIeRpyN2yUjJSd+DxsgU52nfeb6448yILSWcKR4KSpvpqsNw99oj04kXpWolG6nAtVMu8KYjRv9KcybJkRJq7cGo6y1vliJcw+v5p2qKpZ4VXAq3MOJmDetcMES1EBWaKAFkC1FE0VgF+eyZM6tUeiNApCB3FopG5sYyYlgh/fwiLeUec0QeNb+hp9A8UnpSsRPgtLPsEgZzNDV1xl4qNnl/t+Q5pu1qLpxgWqc6JxkBvPFyApOezVoLQ+371QheCsDoE+f7A/gffS1QY98PB5/jOAZ4yubOIUC4rzZNP9qbDpyTRZ2vod5DGk6qdyL+/S0s2pjdDwO+SfhKJ2JgONXiydGzITXktbiyQqPdForCQIOqd6nAIeTbCxUhiBLeCKTxw28UCezhvOzpFGxLAOrMZOdcIlfuJ8n+HboH2OYWiGr7a8rLi6kg9+hLVKISyoA7QI6HKHoR/PInOSRaPq7eRQP6NiKPGwgdUeJTpg0PoOMd9t1LA5AG62viX4nb+vp27lP/wEHR89frPHNKOM2IEWbdbapbCNxzjWvRTrs8gtYAs4QAKdse8oevZVKxWCplIVKjApvcjWt5oXRhnf8HJ5yA5w/FPjzm7NoJJqYNrSGOdVPrDdBKKLef+1nQKoa+zyVOOkwoJjSOp8879AJEQxIPkFBQ4qh36xINAE+a5sMS9WJ5Llo066+MCyP4M+/nnUAIEeUIk+Q3BYD6Uuvihc5F3L6/PwB5poNZbls3pA0mGcTU3CmXl44v7VGsQrQKjdUWWu+pwv+N6lfs8OIkRQ9sFPoU4NF0bx/8A1Kr6G4TfOX9En9UnwwBDMawj59/iXn6+v4R7IM9Zk+qetevD6T9WEa6SkUp Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.76.110; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760634074950158500 Content-Type: text/plain; charset="utf-8" And add arm64 files. From Pedro Barbuda (on Teams): > we meant to have that switched a while back. you can add me as the mainta= iner. Pedro Barbuda (pbarbuda@microsoft.com) Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier --- MAINTAINERS | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index a516e66642..5faa4a2fb6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -544,11 +544,14 @@ F: accel/stubs/hvf-stub.c F: include/system/hvf.h F: include/system/hvf_int.h =20 -WHPX CPUs -M: Sunil Muthuswamy +WHPX +M: Pedro Barbuda +M: Mohamed Mediouni S: Supported F: accel/whpx/ F: target/i386/whpx/ +F: target/arm/whpx_arm.h +F: target/arm/whpx/ F: accel/stubs/whpx-stub.c F: include/system/whpx.h F: include/system/whpx-accel-ops.h --=20 2.50.1 (Apple Git-155) From nobody Fri Nov 14 16:52:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1760634179; cv=none; d=zohomail.com; s=zohoarc; b=mKGGkcmLwjot0wCZ350I4aLfNke4NDv4fJsiulke2MohfwT193mJVw0zvvzsU38+MqJ1YgzNzmSb9hkiqYcHZtODPkCBQwGGnrpVf8w3aXGQBtJ4LT10R2Oax0NgAkS7SDxKayj0JcT/X/76xZpkzpWWRHFuTOAnkFjjICq186w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760634179; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=c/5rsUrStdeRorYSqBu3+Q8xyENsD0DokCuHFqMkrGk=; b=EcuNXEhMlDlimNNnLmlSMIvD7rJuqU+CFV/XcCgz3KwCiJUYkeeqAsYSokR4sB0zJgXaXEcdpoTJP9ieDZpu7E6drPv4DK2upWTrkDOWxigQKkRiuJtlrmPMpWjcOxoejwfUvaAPAdEjHk+T4ra0Rqnmj7Fj+gresGRdiqUlU5M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760634179104719.2855017391366; Thu, 16 Oct 2025 10:02:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v9RJ4-0001Rq-Eh; Thu, 16 Oct 2025 12:58:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RIn-0001Du-Ee for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:58:10 -0400 Received: from p-east2-cluster1-host5-snip4-2.eps.apple.com ([57.103.76.85] helo=outbound.st.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v9RIV-0001hQ-6V for qemu-devel@nongnu.org; Thu, 16 Oct 2025 12:58:09 -0400 Received: from outbound.st.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPS id A6A4D180017F; Thu, 16 Oct 2025 16:57:45 +0000 (UTC) Received: from localhost.localdomain (unknown [17.42.251.67]) by p00-icloudmta-asmtp-us-east-1a-100-percent-2 (Postfix) with ESMTPSA id B3362180074D; Thu, 16 Oct 2025 16:56:44 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; bh=c/5rsUrStdeRorYSqBu3+Q8xyENsD0DokCuHFqMkrGk=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=Qx2WAH2lDvnTPqu2Ezpway7CAh7U/kHiAa0myPfLiHvnT5JzbCU/Ozxql8vTWLU1uHZXDPFNovGSgfPLdh3FjMS1Q6Mcv/yB9RX3Uq8bh8UaqlD0dLmcpukI09uy68zUG/VFSkEdmzU341tNoAzhlHfucpE913sENz34yvIMi+OtNTa3mZFm9Wk0L7WdTsx0YP5uY/4aYWK6DysBMOuf9CAm+NW8qwxmViwYmLZgye7QsB0WXzEqHP3WV2Ku8DoWyW6+l875mrE64TMz7BsD+qu0i0b+59sT0UO6T4ngowZ4wHldGKPUlPtRLxh1WPYjvribVZr6jfudXpWDMxDSlg== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Alexander Graf , Richard Henderson , Cameron Esfahani , Mads Ynddal , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ani Sinha , Phil Dennis-Jordan , Mohamed Mediouni , Eduardo Habkost , Sunil Muthuswamy , "Michael S. Tsirkin" , Igor Mammedov , Paolo Bonzini , Yanan Wang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Shannon Zhao , kvm@vger.kernel.org, Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pedro Barbuda , Zhao Liu , Roman Bolshakov Subject: [PATCH v7 24/24] whpx: apic: use non-deprecated APIs to control interrupt controller state Date: Thu, 16 Oct 2025 18:55:20 +0200 Message-ID: <20251016165520.62532-25-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251016165520.62532-1-mohamed@unpredictable.fr> References: <20251016165520.62532-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE2MDEyMiBTYWx0ZWRfX3i591J451V0o sUr0Fl3iXpQwy/Fl4zdiWLFiMpXCSfVPkj64i2rGs4UIzKhvNch4ARxEuJ7d3V9UM+LlzeWvYiP CwiG54MjcbPEiIH9JB05aIfno0GN3YhuvFQT6jmSNZanRe0M3bYaDtlmhT2ptdLSU/QIjB14sEv Vw+njagl+uYv4sVOoEPu76T34W2l7r7fHWpXMjGViTX6wRD0Nj50QwooFH0g9aDqKVY8VLImich O5ekCNCxPInhMy6eMRcvIGRoGtM8Et4yD5CPzHTDVYxlKCZswSRI9MtGKRrlm9f7ebn+Vt80A= X-Proofpoint-ORIG-GUID: LFF1_aj_2RXFysquanP2u9LYbbvtgC-y X-Proofpoint-GUID: LFF1_aj_2RXFysquanP2u9LYbbvtgC-y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 malwarescore=0 spamscore=0 mlxlogscore=824 mlxscore=0 bulkscore=0 phishscore=0 suspectscore=0 adultscore=0 clxscore=1030 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.22.0-2506270000 definitions=main-2510160122 X-JNJ: AAAAAAABCDIHi3Oq+7eUfU6kQVtln5bsGab5D20obzhGx/RBwT3+UnCVMabBxb0dMK01J2HgwJ46Ww/4ugDyIy4pWrM9aJgR5Ic5avONZXpjWKzw4dSjkzeg9pKKVeoeiXLXV47Q5fv+c9MMPP+ltky/OJ81LqzITocrn4Ssnk47d66KC/iBUaAsW+73JI/Rd/EdvFNanjHdRj/uT3rr/lYsshaeLsvzBS5aUWYDcwH6Gg6GrbuFGuKrKA4XEpOiDJ1qnjKnYDxZUuzLjc8WoYIqdwyGF9P0FsWjCHN7gvSveEv69ZDybTPlmE7O6121UR6WS7+DpeOAOHrScyG1WAyH50iEbVhXlthWY66jLDUAfgwtG62RZEJKPJFP30MANYW3ZNqIDsxKdX/0K+9jv75271g/chZmpeQuZGH5qn4waXrO2U3GAj32rXkT60JGX9T+vPspdNHQUMbs0wLBzTIz00jGmj2fvovUvGnqUwE9RSzAlhN5e01hlqV3g8n8Yxc0SAu71D/StJlQgVSxiUKBfjORcInbFBDloXgvSKtT0rn+3pyCFt8IeUWUiZO4BNv0tvztVQgumWlsplFgLR3ypIqBqzEGR21HBRbXyCPIisP88hl6qRVYjC5yrn6n3u0MPVIHHL9uHph36Icm8UeQc6fYpEriWwKE6S5nRMFvMm9845X73TpiM/Zuhj6hCUtgXkSOYV61ryHBwTRomlO9ALuAw5R7yAw7DiWZXmkempImhGf0OaVtbSG7GVPkpsjKQzz4sKNWn/iB22pXaj+l2M3fmz0tWzbJyEswFSUHLNa8suzsktqNQHoUklpSE69DblaHahW/XxLGE5QRpXJp0oC1GB+29vqp+O1z8WgPxh7TTCCcEAw/xXFxnzQ2kVr2N24Eo4xTnZu13Pb7/AevUVx1hJFABKfq Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.76.85; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1760634182393154100 Content-Type: text/plain; charset="utf-8" WHvGetVirtualProcessorInterruptControllerState2 and WHvSetVirtualProcessorInterruptControllerState2 are deprecated since Windows 10 version 2004. Use the non-deprecated WHvGetVirtualProcessorState and WHvSetVirtualProcessorState when available. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier Tested-by: Pierrick Bouvier --- include/system/whpx-internal.h | 9 +++++++ target/i386/whpx/whpx-apic.c | 46 +++++++++++++++++++++++++--------- 2 files changed, 43 insertions(+), 12 deletions(-) diff --git a/include/system/whpx-internal.h b/include/system/whpx-internal.h index 366bc525a3..b87d35cf1b 100644 --- a/include/system/whpx-internal.h +++ b/include/system/whpx-internal.h @@ -84,6 +84,15 @@ void whpx_apic_get(DeviceState *s); X(HRESULT, WHvSetVirtualProcessorInterruptControllerState2, \ (WHV_PARTITION_HANDLE Partition, UINT32 VpIndex, PVOID State, \ UINT32 StateSize)) \ + X(HRESULT, WHvGetVirtualProcessorState, \ + (WHV_PARTITION_HANDLE Partition, UINT32 VpIndex, \ + WHV_VIRTUAL_PROCESSOR_STATE_TYPE StateType, PVOID Buffer, \ + UINT32 BufferSizeInBytes, UINT32 *BytesWritten)) \ + X(HRESULT, WHvSetVirtualProcessorState, \ + (WHV_PARTITION_HANDLE Partition, UINT32 VpIndex, \ + WHV_VIRTUAL_PROCESSOR_STATE_TYPE StateType, PVOID Buffer, \ + UINT32 BufferSizeInBytes)) \ + =20 #define LIST_WINHVEMULATION_FUNCTIONS(X) \ X(HRESULT, WHvEmulatorCreateEmulator, (const WHV_EMULATOR_CALLBACKS* Cal= lbacks, WHV_EMULATOR_HANDLE* Emulator)) \ diff --git a/target/i386/whpx/whpx-apic.c b/target/i386/whpx/whpx-apic.c index badb404b63..285ca28ba2 100644 --- a/target/i386/whpx/whpx-apic.c +++ b/target/i386/whpx/whpx-apic.c @@ -137,11 +137,21 @@ static void whpx_apic_put(CPUState *cs, run_on_cpu_da= ta data) whpx_put_apic_base(CPU(s->cpu), s->apicbase); whpx_put_apic_state(s, &kapic); =20 - hr =3D whp_dispatch.WHvSetVirtualProcessorInterruptControllerState2( - whpx_global.partition, - cs->cpu_index, - &kapic, - sizeof(kapic)); + if (whp_dispatch.WHvSetVirtualProcessorState) { + hr =3D whp_dispatch.WHvSetVirtualProcessorState( + whpx_global.partition, + cs->cpu_index, + WHvVirtualProcessorStateTypeInterruptControllerState2, + &kapic, + sizeof(kapic)); + } else { + hr =3D whp_dispatch.WHvSetVirtualProcessorInterruptControllerState= 2( + whpx_global.partition, + cs->cpu_index, + &kapic, + sizeof(kapic)); + } + if (FAILED(hr)) { fprintf(stderr, "WHvSetVirtualProcessorInterruptControllerState failed: %08lx\= n", @@ -156,16 +166,28 @@ void whpx_apic_get(DeviceState *dev) APICCommonState *s =3D APIC_COMMON(dev); CPUState *cpu =3D CPU(s->cpu); struct whpx_lapic_state kapic; + HRESULT hr; + + if (whp_dispatch.WHvGetVirtualProcessorState) { + hr =3D whp_dispatch.WHvGetVirtualProcessorState( + whpx_global.partition, + cpu->cpu_index, + WHvVirtualProcessorStateTypeInterruptControllerState2, + &kapic, + sizeof(kapic), + NULL); + } else { + hr =3D whp_dispatch.WHvGetVirtualProcessorInterruptControllerState= 2( + whpx_global.partition, + cpu->cpu_index, + &kapic, + sizeof(kapic), + NULL); + } =20 - HRESULT hr =3D whp_dispatch.WHvGetVirtualProcessorInterruptControllerS= tate2( - whpx_global.partition, - cpu->cpu_index, - &kapic, - sizeof(kapic), - NULL); if (FAILED(hr)) { fprintf(stderr, - "WHvSetVirtualProcessorInterruptControllerState failed: %08lx\= n", + "WHvGetVirtualProcessorInterruptControllerState failed: %08lx\= n", hr); =20 abort(); --=20 2.50.1 (Apple Git-155)