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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Message-Id: <20251008064814.90520-3-philmd@linaro.org> --- target/sh4/cpu.h | 2 +- target/sh4/helper.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index db27a693f12..b0759010c47 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -277,7 +277,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwa= ddr addr, uint32_t mem_value); #endif =20 -int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr); +int cpu_sh4_is_cached(CPUSH4State *env, uint32_t addr); =20 void cpu_load_tlb(CPUSH4State * env); =20 diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 1744ef0e6d8..4f1e2072296 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -47,7 +47,7 @@ =20 #if defined(CONFIG_USER_ONLY) =20 -int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr) +int cpu_sh4_is_cached(CPUSH4State *env, uint32_t addr) { /* For user mode, only U0 area is cacheable. */ return !(addr & 0x80000000); @@ -735,7 +735,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwa= ddr addr, } } =20 -int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) +int cpu_sh4_is_cached(CPUSH4State *env, uint32_t addr) { int n; int use_asid =3D !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD)= ); --=20 2.51.0