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Next commits will remove support for 32-bit MIPS hosts. Stop cross-building QEMU on our CI. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Signed-off-by: Richard Henderson Message-ID: <20251009195210.33161-3-philmd@linaro.org> --- .gitlab-ci.d/container-cross.yml | 6 ------ .gitlab-ci.d/crossbuilds.yml | 14 -------------- 2 files changed, 20 deletions(-) diff --git a/.gitlab-ci.d/container-cross.yml b/.gitlab-ci.d/container-cros= s.yml index 8d3be53b75..0fd7341afa 100644 --- a/.gitlab-ci.d/container-cross.yml +++ b/.gitlab-ci.d/container-cross.yml @@ -52,12 +52,6 @@ mips64el-debian-cross-container: variables: NAME: debian-mips64el-cross =20 -mipsel-debian-cross-container: - extends: .container_job_template - stage: containers - variables: - NAME: debian-mipsel-cross - ppc64el-debian-cross-container: extends: .container_job_template stage: containers diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index 8ff0c27f74..99dfa7eea6 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -68,20 +68,6 @@ cross-i686-tci: # would otherwise be using a parallelism of 9. MAKE_CHECK_ARGS: check check-tcg -j2 =20 -cross-mipsel-system: - extends: .cross_system_build_job - needs: - - job: mipsel-debian-cross-container - variables: - IMAGE: debian-mipsel-cross - -cross-mipsel-user: - extends: .cross_user_build_job - needs: - - job: mipsel-debian-cross-container - variables: - IMAGE: debian-mipsel-cross - cross-mips64el-system: extends: .cross_system_build_job needs: --=20 2.43.0 From nobody Fri Nov 14 18:19:12 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760564396; cv=none; d=zohomail.com; s=zohoarc; b=XZ7fsdU+Xg/8OAln/VtfYDnoOD636RmeGCjaeOuL8brf+0mES4cuWjN5R+sp/LdtzddlTkJZPF5LI3mYSABQAZ+Eoeo4RtZHZcUvP2j67z5hs+LYQ9mU5WSf344HJ5eJgvyRsZMsyAYD7vkwZ4BegNRtwwXuEojOn1hfRak6bww= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760564396; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EAYhbIEVnqIpv3UM3lZTlnJP6T433ZQvfgE/KFwrBAE=; b=HrTLfptXmr+2xrd1FD9qy2Ze/Y7d/Cb1FpF6yY9MmPZAmG56SWG6imTjPg9Y8HQlEVfEMYB1JetduqHao8BX6a7nd3DlbnwrMZwy/G/4JY58SKjZMDQT/+DPAcuvGt9qMwAK6NrM18qMgdiRjBzKzH8FzSNlv7oD8PpoHw/DyNY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760564396018680.9998653451993; Wed, 15 Oct 2025 14:39:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v99D9-0003d6-O2; Wed, 15 Oct 2025 17:39:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v99Cu-0003ZX-H9 for qemu-devel@nongnu.org; Wed, 15 Oct 2025 17:38:54 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v99Cr-0004zN-Lm for qemu-devel@nongnu.org; Wed, 15 Oct 2025 17:38:52 -0400 Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-b556284db11so9387a12.0 for ; Wed, 15 Oct 2025 14:38:48 -0700 (PDT) Received: from stoup.. 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See previous commit for rationale. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Signed-off-by: Richard Henderson Message-ID: <20251009195210.33161-8-philmd@linaro.org> --- configure | 7 ------- docs/about/deprecated.rst | 13 +++++-------- docs/about/removed-features.rst | 6 ++++++ 3 files changed, 11 insertions(+), 15 deletions(-) diff --git a/configure b/configure index 461b53dd60..8263f81370 100755 --- a/configure +++ b/configure @@ -404,8 +404,6 @@ elif check_define _ARCH_PPC ; then elif check_define __mips__ ; then if check_define __mips64 ; then cpu=3D"mips64" - else - cpu=3D"mips" fi elif check_define __s390__ ; then if check_define __s390x__ ; then @@ -473,11 +471,6 @@ case "$cpu" in host_arch=3Dmips linux_arch=3Dmips ;; - mips*) - cpu=3Dmips - host_arch=3Dmips - linux_arch=3Dmips - ;; =20 ppc) host_arch=3Dppc diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 98361f5832..dacf2882e4 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -172,17 +172,14 @@ This argument has always been ignored. Host Architectures ------------------ =20 -Big endian MIPS since 7.2; 32-bit little endian MIPS since 9.2, MIPS since= 11.0 -''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''= ''''' +MIPS (since 11.0) +''''''''''''''''' =20 -As Debian 10 ("Buster") moved into LTS the big endian 32 bit version of -MIPS moved out of support making it hard to maintain our -cross-compilation CI tests of the architecture. As we no longer have -CI coverage support may bitrot away before the deprecation process +MIPS is not supported by Debian 13 ("Trixie") and newer, making it hard to +maintain our cross-compilation CI tests of the architecture. As we no long= er +have CI coverage support may bitrot away before the deprecation process completes. =20 -Likewise, MIPS is not supported by Debian 13 ("Trixie") and newer. - System emulation on 32-bit x86 hosts (since 8.0) '''''''''''''''''''''''''''''''''''''''''''''''' =20 diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.= rst index a5338e44c2..53829f59e6 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -896,6 +896,12 @@ work around the atomicity issues in system mode by run= ning all vCPUs in a single thread context; in user mode atomicity was simply broken. From 10.0, QEMU has disabled configuration of 64-bit guests on 32-bit host= s. =20 +32-bit MIPS (since 11.0) +'''''''''''''''''''''''' + +Debian 12 "Bookworm" removed support for 32-bit MIPS, making it hard to +maintain our cross-compilation CI tests of the architecture. + Guest Emulator ISAs ------------------- =20 --=20 2.43.0 From nobody Fri Nov 14 18:19:12 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760564391; cv=none; d=zohomail.com; s=zohoarc; b=B6uh/VRKRNZhwJN8L+CvULA+uYqr1cavh+w2FvSaZb0VaO3aGKxqNgPDmt5TYgcxTKn++6qcZW3vNLqeulAVsAvMx4mgKu5eHmzCg49cIVdsZTTPtzHglE+LWDpECC0fvEBZAgWavkIEsOlzBmg1QBOcHbTEUw96Rbww9tQeQhk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760564391; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+w5No0Ep1LX3XR7FDPjD+GZNr16ogOShPRDBWgvVMw0=; b=SOnTcDVHLKplC7vW1hcb1w+aLFDDiC9fucC1hVNS3uSaBIg9XQxHcqrwlgrls1HQmu9xZGRFVetkxLr/2qHKJMOjRaHczZ19qLQWZbBMxrEPT+jceDXZmr+mTeC+CYOkdNGH1rqACmX/Ry/uZy3v14vBiOIl3pP1N50QHo46sDU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760564391266463.0764639716791; Wed, 15 Oct 2025 14:39:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v99DA-0003e1-S3; Wed, 15 Oct 2025 17:39:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v99Cx-0003Zj-0s for qemu-devel@nongnu.org; Wed, 15 Oct 2025 17:38:57 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v99Cr-0004zQ-LU for qemu-devel@nongnu.org; Wed, 15 Oct 2025 17:38:54 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-789fb76b466so84584b3a.0 for ; Wed, 15 Oct 2025 14:38:48 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Signed-off-by: Richard Henderson Message-ID: <20251009195210.33161-7-philmd@linaro.org> --- meson.build | 2 -- 1 file changed, 2 deletions(-) diff --git a/meson.build b/meson.build index afaefa0172..c5710a6a47 100644 --- a/meson.build +++ b/meson.build @@ -295,8 +295,6 @@ elif cpu =3D=3D 'ppc' kvm_targets =3D ['ppc-softmmu'] elif cpu =3D=3D 'ppc64' kvm_targets =3D ['ppc-softmmu', 'ppc64-softmmu'] -elif cpu =3D=3D 'mips' - kvm_targets =3D ['mips-softmmu', 'mipsel-softmmu'] elif cpu =3D=3D 'mips64' kvm_targets =3D ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mi= ps64el-softmmu'] elif cpu =3D=3D 'riscv32' --=20 2.43.0 From nobody Fri Nov 14 18:19:12 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760564483; cv=none; d=zohomail.com; s=zohoarc; b=kkTpXb+0tXMkrXbjxYG/osmkcD3Ng8+EamQqGNxVedr+Hqd3MYMd27+QoQwmk46/85fmOcsqA4YW6MEUIRQ6mAujwbLYHC7+Jp/quuZwegoVlCYgv527ZU+gBYznToK+zf8I5tpzw5USzksg3QjLtkxSMzEEqcfJGfFqUqI6020= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760564483; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=oZnK3yCNaUwo8Kqz/STDxY+wFQGjUJ7jcrykCbsgxto=; b=fqmdvegQ0w5i5rt7jJd/z8jXs4+L6e8LCAliKh0kr0MFyGMo01owH3Rz+UCcW+0D87KyszP5wHZ99LQOtEHFsQTilCuiT9XmvSamnx2WwYwCX6jOWqN8j8CkZw7aEOs+poUF7mLJ3ypjKCrpZHj6QmfP0NSac4AZTBtVDISlqxk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17605644835561010.4163615799623; Wed, 15 Oct 2025 14:41:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v99D7-0003cA-Cg; Wed, 15 Oct 2025 17:39:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v99Cx-0003Zk-2N for qemu-devel@nongnu.org; Wed, 15 Oct 2025 17:38:57 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v99Cr-0004zV-MF for qemu-devel@nongnu.org; Wed, 15 Oct 2025 17:38:54 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-27eec33b737so895615ad.1 for ; Wed, 15 Oct 2025 14:38:48 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Signed-off-by: Richard Henderson Message-ID: <20251009195210.33161-5-philmd@linaro.org> --- tcg/mips/tcg-target-reg-bits.h | 8 ++---- common-user/host/mips/safe-syscall.inc.S | 35 ------------------------ tcg/mips/tcg-target.c.inc | 14 ++-------- 3 files changed, 6 insertions(+), 51 deletions(-) diff --git a/tcg/mips/tcg-target-reg-bits.h b/tcg/mips/tcg-target-reg-bits.h index 56fe0a725e..ee346a3f25 100644 --- a/tcg/mips/tcg-target-reg-bits.h +++ b/tcg/mips/tcg-target-reg-bits.h @@ -7,12 +7,10 @@ #ifndef TCG_TARGET_REG_BITS_H #define TCG_TARGET_REG_BITS_H =20 -#if _MIPS_SIM =3D=3D _ABIO32 -# define TCG_TARGET_REG_BITS 32 -#elif _MIPS_SIM =3D=3D _ABIN32 || _MIPS_SIM =3D=3D _ABI64 -# define TCG_TARGET_REG_BITS 64 -#else +#if !defined(_MIPS_SIM) || _MIPS_SIM !=3D _ABI64 # error "Unknown ABI" #endif =20 +#define TCG_TARGET_REG_BITS 64 + #endif diff --git a/common-user/host/mips/safe-syscall.inc.S b/common-user/host/mi= ps/safe-syscall.inc.S index 6a44614970..3b196cc634 100644 --- a/common-user/host/mips/safe-syscall.inc.S +++ b/common-user/host/mips/safe-syscall.inc.S @@ -30,15 +30,9 @@ * arguments being syscall arguments (also 'long'). */ =20 -#if _MIPS_SIM =3D=3D _ABIO32 -/* 8 * 4 =3D 32 for outgoing parameters; 1 * 4 for s0 save; 1 * 4 for alig= n. */ -#define FRAME 40 -#define OFS_S0 32 -#else /* 1 * 8 for s0 save; 1 * 8 for align. */ #define FRAME 16 #define OFS_S0 0 -#endif =20 =20 NESTED(safe_syscall_base, FRAME, ra) @@ -47,34 +41,6 @@ NESTED(safe_syscall_base, FRAME, ra) .cfi_adjust_cfa_offset FRAME REG_S s0, OFS_S0(sp) .cfi_rel_offset s0, OFS_S0 -#if _MIPS_SIM =3D=3D _ABIO32 - /* - * The syscall calling convention is nearly the same as C: - * we enter with a0 =3D=3D &signal_pending - * a1 =3D=3D syscall number - * a2, a3, stack =3D=3D syscall arguments - * and return the result in a0 - * and the syscall instruction needs - * v0 =3D=3D syscall number - * a0 ... a3, stack =3D=3D syscall arguments - * and returns the result in v0 - * Shuffle everything around appropriately. - */ - move s0, a0 /* signal_pending pointer */ - move v0, a1 /* syscall number */ - move a0, a2 /* syscall arguments */ - move a1, a3 - lw a2, FRAME+16(sp) - lw a3, FRAME+20(sp) - lw t4, FRAME+24(sp) - lw t5, FRAME+28(sp) - lw t6, FRAME+32(sp) - lw t7, FRAME+40(sp) - sw t4, 16(sp) - sw t5, 20(sp) - sw t6, 24(sp) - sw t7, 28(sp) -#else /* * The syscall calling convention is nearly the same as C: * we enter with a0 =3D=3D &signal_pending @@ -95,7 +61,6 @@ NESTED(safe_syscall_base, FRAME, ra) move a3, a5 move a4, a6 move a5, a7 -#endif =20 /* * This next sequence of code works in conjunction with the diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 400eafbab4..2ca5aaf3a6 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -26,16 +26,10 @@ =20 /* used for function call generation */ #define TCG_TARGET_STACK_ALIGN 16 -#if _MIPS_SIM =3D=3D _ABIO32 -# define TCG_TARGET_CALL_STACK_OFFSET 16 -# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN -# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF -#else -# define TCG_TARGET_CALL_STACK_OFFSET 0 -# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL -# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL -#endif +#define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN =20 #if TCG_TARGET_REG_BITS =3D=3D 32 @@ -135,12 +129,10 @@ static const TCGReg tcg_target_call_iarg_regs[] =3D { TCG_REG_A1, TCG_REG_A2, TCG_REG_A3, -#if _MIPS_SIM =3D=3D _ABIN32 || _MIPS_SIM =3D=3D _ABI64 TCG_REG_T0, TCG_REG_T1, TCG_REG_T2, TCG_REG_T3, -#endif }; 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The next release being v10.2, we can remove the TCG backend for 32-bit MIPS hosts. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Signed-off-by: Richard Henderson Message-ID: <20251009195210.33161-6-philmd@linaro.org> --- tcg/mips/tcg-target-has.h | 2 - tcg/mips/tcg-target.c.inc | 285 +++++--------------------------------- 2 files changed, 38 insertions(+), 249 deletions(-) diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h index b9eb338528..88f0145efb 100644 --- a/tcg/mips/tcg-target-has.h +++ b/tcg/mips/tcg-target-has.h @@ -39,11 +39,9 @@ extern bool use_mips32r2_instructions; #endif =20 /* optional instructions */ -#if TCG_TARGET_REG_BITS =3D=3D 64 #define TCG_TARGET_HAS_extr_i64_i32 1 #define TCG_TARGET_HAS_ext32s_i64 1 #define TCG_TARGET_HAS_ext32u_i64 1 -#endif =20 /* optional instructions detected at runtime */ #define TCG_TARGET_HAS_qemu_ldst_i128 0 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 2ca5aaf3a6..8e7c0ea33f 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -32,15 +32,6 @@ #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 -# define LO_OFF (HOST_BIG_ENDIAN * 4) -# define HI_OFF (4 - LO_OFF) -#else -/* Assert at compile-time that these values are never used for 64-bit. */ -# define LO_OFF ({ qemu_build_not_reached(); 0; }) -# define HI_OFF ({ qemu_build_not_reached(); 0; }) -#endif - #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { "zero", @@ -84,11 +75,7 @@ static const char * const tcg_target_reg_names[TCG_TARGE= T_NB_REGS] =3D { #define TCG_TMP3 TCG_REG_T7 =20 #define TCG_GUEST_BASE_REG TCG_REG_S7 -#if TCG_TARGET_REG_BITS =3D=3D 64 #define TCG_REG_TB TCG_REG_S6 -#else -#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; }) -#endif =20 /* check if we really need so many registers :P */ static const int tcg_target_reg_alloc_order[] =3D { @@ -559,7 +546,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, tcg_target_long tmp; int sh, lo; =20 - if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I32) { + if (type =3D=3D TCG_TYPE_I32) { arg =3D (int32_t)arg; } =20 @@ -567,7 +554,6 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, if (tcg_out_movi_two(s, ret, arg)) { return; } - assert(TCG_TARGET_REG_BITS =3D=3D 64); =20 /* Load addresses within 2GB of TB with 1 or 3 insns. */ tmp =3D tcg_tbrel_diff(s, (void *)arg); @@ -630,8 +616,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg) { - TCGReg tbreg =3D TCG_TARGET_REG_BITS =3D=3D 64 ? TCG_REG_TB : 0; - tcg_out_movi_int(s, type, ret, arg, tbreg); + tcg_out_movi_int(s, type, ret, arg, TCG_REG_TB); } =20 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg r= s) @@ -658,7 +643,6 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TC= GReg rs) =20 static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); } =20 @@ -701,7 +685,6 @@ static void tcg_out_bswap_subr(TCGContext *s, const tcg= _insn_unit *sub) =20 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); if (use_mips32r2_instructions) { tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); } else { @@ -727,20 +710,14 @@ static void tcg_out_ldst(TCGContext *s, MIPSInsn opc,= TCGReg data, static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { - MIPSInsn opc =3D OPC_LD; - if (TCG_TARGET_REG_BITS =3D=3D 32 || type =3D=3D TCG_TYPE_I32) { - opc =3D OPC_LW; - } + MIPSInsn opc =3D type =3D=3D TCG_TYPE_I32 ? OPC_LW : OPC_LD; tcg_out_ldst(s, opc, arg, arg1, arg2); } =20 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { - MIPSInsn opc =3D OPC_SD; - if (TCG_TARGET_REG_BITS =3D=3D 32 || type =3D=3D TCG_TYPE_I32) { - opc =3D OPC_SW; - } + MIPSInsn opc =3D type =3D=3D TCG_TYPE_I32 ? OPC_SW : OPC_SD; tcg_out_ldst(s, opc, arg, arg1, arg2); } =20 @@ -918,72 +895,6 @@ void tcg_out_br(TCGContext *s, TCGLabel *l) tgen_brcond(s, TCG_TYPE_I32, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, = l); } =20 -static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) -{ - int flags =3D 0; - - switch (cond) { - case TCG_COND_EQ: - flags |=3D SETCOND_INV; - /* fall through */ - case TCG_COND_NE: - flags |=3D SETCOND_NEZ; - tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl); - tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh); - tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); - break; - - default: - tgen_setcond(s, TCG_TYPE_I32, TCG_COND_EQ, TCG_TMP0, ah, bh); - tgen_setcond(s, TCG_TYPE_I32, tcg_unsigned_cond(cond), - TCG_TMP1, al, bl); - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0); - tgen_setcond(s, TCG_TYPE_I32, tcg_high_cond(cond), TCG_TMP0, ah, b= h); - tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); - break; - } - return ret | flags; -} - -static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, - TCGArg bh, bool const_bh) -{ - int tmpflags =3D tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh); - tcg_out_setcond_end(s, ret, tmpflags); -} - -#if TCG_TARGET_REG_BITS !=3D 32 -__attribute__((unused)) -#endif -static const TCGOutOpSetcond2 outop_setcond2 =3D { - .base.static_constraint =3D C_O1_I4(r, r, r, rz, rz), - .out =3D tgen_setcond2, -}; - -static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, - TCGArg bh, bool const_bh, TCGLabel *l) -{ - int tmpflags =3D tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, b= h); - TCGReg tmp =3D tmpflags & ~SETCOND_FLAGS; - MIPSInsn b_opc =3D tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; - - tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); - tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO); - tcg_out_nop(s); -} - -#if TCG_TARGET_REG_BITS !=3D 32 -__attribute__((unused)) -#endif -static const TCGOutOpBrcond2 outop_brcond2 =3D { - .base.static_constraint =3D C_O0_I4(r, r, rz, rz), - .out =3D tgen_brcond2, -}; - static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, TCGArg v1, bool const_v1, TCGArg v2, bool const_v= 2) @@ -1189,7 +1100,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); =20 /* Extract the TLB index from the address into TMP3. */ - if (TCG_TARGET_REG_BITS =3D=3D 32 || addr_type =3D=3D TCG_TYPE_I32= ) { + if (addr_type =3D=3D TCG_TYPE_I32) { tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); } else { @@ -1201,7 +1112,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); =20 /* Load the tlb comparator. */ - if (TCG_TARGET_REG_BITS =3D=3D 64 && addr_type =3D=3D TCG_TYPE_I32= ) { + if (addr_type =3D=3D TCG_TYPE_I32) { tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HOST_BIG_ENDIAN * 4); } else { @@ -1218,8 +1129,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, */ tcg_out_movi(s, addr_type, TCG_TMP1, TARGET_PAGE_MASK | a_mask); if (a_mask < s_mask) { - tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS =3D=3D 32 - || addr_type =3D=3D TCG_TYPE_I32 + tcg_out_opc_imm(s, (addr_type =3D=3D TCG_TYPE_I32 ? OPC_ADDIU : OPC_DADDIU), TCG_TMP2, addr, s_mask - a_mask); tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); @@ -1228,7 +1138,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, } =20 /* Zero extend a 32-bit guest address for a 64-bit host. */ - if (TCG_TARGET_REG_BITS =3D=3D 64 && addr_type =3D=3D TCG_TYPE_I32= ) { + if (addr_type =3D=3D TCG_TYPE_I32) { tcg_out_ext32u(s, TCG_TMP2, addr); addr =3D TCG_TMP2; } @@ -1261,7 +1171,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, } =20 base =3D addr; - if (TCG_TARGET_REG_BITS =3D=3D 64 && addr_type =3D=3D TCG_TYPE_I32= ) { + if (addr_type =3D=3D TCG_TYPE_I32) { tcg_out_ext32u(s, TCG_REG_A0, base); base =3D TCG_REG_A0; } @@ -1297,7 +1207,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, tcg_out_opc_imm(s, OPC_LH, lo, base, 0); break; case MO_UL: - if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64) { + if (type =3D=3D TCG_TYPE_I64) { tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); break; } @@ -1306,16 +1216,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TC= GReg lo, TCGReg hi, tcg_out_opc_imm(s, OPC_LW, lo, base, 0); break; case MO_UQ: - /* Prefer to load from offset 0 first, but allow for overlap. */ - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_opc_imm(s, OPC_LD, lo, base, 0); - } else if (HOST_BIG_ENDIAN ? hi !=3D base : lo =3D=3D base) { - tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); - tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); - } else { - tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); - tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); - } + tcg_out_opc_imm(s, OPC_LD, lo, base, 0); break; default: g_assert_not_reached(); @@ -1357,21 +1258,14 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, = TCGReg lo, TCGReg hi, case MO_32: tcg_out_opc_imm(s, lw1, lo, base, 0); tcg_out_opc_imm(s, lw2, lo, base, 3); - if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64 && != sgn) { + if (type =3D=3D TCG_TYPE_I64 && !sgn) { tcg_out_ext32u(s, lo, lo); } break; =20 case MO_64: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_opc_imm(s, ld1, lo, base, 0); - tcg_out_opc_imm(s, ld2, lo, base, 7); - } else { - tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0= ); - tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3= ); - tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0= ); - tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3= ); - } + tcg_out_opc_imm(s, ld1, lo, base, 0); + tcg_out_opc_imm(s, ld2, lo, base, 7); break; =20 default: @@ -1407,36 +1301,8 @@ static const TCGOutOpQemuLdSt outop_qemu_ld =3D { .out =3D tgen_qemu_ld, }; =20 -static void tgen_qemu_ld2(TCGContext *s, TCGType type, TCGReg datalo, - TCGReg datahi, TCGReg addr, MemOpIdx oi) -{ - MemOp opc =3D get_memop(oi); - TCGLabelQemuLdst *ldst; - HostAddress h; - - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); - ldst =3D prepare_host_addr(s, &h, addr, oi, true); - - if (use_mips32r6_instructions || h.aa.align >=3D (opc & MO_SIZE)) { - tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, type); - } else { - tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, type); - } - - if (ldst) { - ldst->type =3D type; - ldst->datalo_reg =3D datalo; - ldst->datahi_reg =3D datahi; - ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); - } -} - static const TCGOutOpQemuLdSt2 outop_qemu_ld2 =3D { - /* Ensure that the mips32 code is compiled but discarded for mips64. */ - .base.static_constraint =3D - TCG_TARGET_REG_BITS =3D=3D 32 ? C_O2_I1(r, r, r) : C_NotImplemente= d, - .out =3D - TCG_TARGET_REG_BITS =3D=3D 32 ? tgen_qemu_ld2 : NULL, + .base.static_constraint =3D C_NotImplemented, }; =20 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, @@ -1453,12 +1319,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TC= GReg lo, TCGReg hi, tcg_out_opc_imm(s, OPC_SW, lo, base, 0); break; case MO_64: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_opc_imm(s, OPC_SD, lo, base, 0); - } else { - tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0); - tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4); - } + tcg_out_opc_imm(s, OPC_SD, lo, base, 0); break; default: g_assert_not_reached(); @@ -1486,15 +1347,8 @@ static void tcg_out_qemu_st_unalign(TCGContext *s, T= CGReg lo, TCGReg hi, break; =20 case MO_64: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_opc_imm(s, sd1, lo, base, 0); - tcg_out_opc_imm(s, sd2, lo, base, 7); - } else { - tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0= ); - tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3= ); - tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0= ); - tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3= ); - } + tcg_out_opc_imm(s, sd1, lo, base, 0); + tcg_out_opc_imm(s, sd2, lo, base, 7); break; =20 default: @@ -1530,36 +1384,8 @@ static const TCGOutOpQemuLdSt outop_qemu_st =3D { .out =3D tgen_qemu_st, }; =20 -static void tgen_qemu_st2(TCGContext *s, TCGType type, TCGReg datalo, - TCGReg datahi, TCGReg addr, MemOpIdx oi) -{ - MemOp opc =3D get_memop(oi); - TCGLabelQemuLdst *ldst; - HostAddress h; - - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); - ldst =3D prepare_host_addr(s, &h, addr, oi, false); - - if (use_mips32r6_instructions || h.aa.align >=3D (opc & MO_SIZE)) { - tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); - } else { - tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); - } - - if (ldst) { - ldst->type =3D type; - ldst->datalo_reg =3D datalo; - ldst->datahi_reg =3D datahi; - ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); - } -} - static const TCGOutOpQemuLdSt2 outop_qemu_st2 =3D { - /* Ensure that the mips32 code is compiled but discarded for mips64. */ - .base.static_constraint =3D - TCG_TARGET_REG_BITS =3D=3D 32 ? C_O0_I3(rz, rz, r) : C_NotImplemen= ted, - .out =3D - TCG_TARGET_REG_BITS =3D=3D 32 ? tgen_qemu_st2 : NULL, + .base.static_constraint =3D C_NotImplemented, }; =20 static void tcg_out_mb(TCGContext *s, unsigned a0) @@ -1584,22 +1410,14 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_= t a0) int16_t lo =3D 0; =20 if (a0) { - intptr_t ofs; - if (TCG_TARGET_REG_BITS =3D=3D 64) { - ofs =3D tcg_tbrel_diff(s, (void *)a0); - lo =3D ofs; - if (ofs =3D=3D lo) { - base =3D TCG_REG_TB; - } else { - base =3D TCG_REG_V0; - tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); - tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); - } + intptr_t ofs =3D tcg_tbrel_diff(s, (void *)a0); + lo =3D ofs; + if (ofs =3D=3D lo) { + base =3D TCG_REG_TB; } else { - ofs =3D a0; - lo =3D ofs; base =3D TCG_REG_V0; tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); + tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); } } if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { @@ -1616,35 +1434,24 @@ static void tcg_out_goto_tb(TCGContext *s, int whic= h) TCGReg base, dest; =20 /* indirect jump method */ - if (TCG_TARGET_REG_BITS =3D=3D 64) { - dest =3D TCG_REG_TB; - base =3D TCG_REG_TB; - ofs =3D tcg_tbrel_diff(s, (void *)ofs); - } else { - dest =3D TCG_TMP0; - base =3D TCG_REG_ZERO; - } + dest =3D TCG_REG_TB; + base =3D TCG_REG_TB; + ofs =3D tcg_tbrel_diff(s, (void *)ofs); tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); /* delay slot */ tcg_out_nop(s); =20 set_jmp_reset_offset(s, which); - if (TCG_TARGET_REG_BITS =3D=3D 64) { - /* For the unlinked case, need to reset TCG_REG_TB. */ - tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, - -tcg_current_code_size(s)); - } + /* For the unlinked case, need to reset TCG_REG_TB. */ + tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, + -tcg_current_code_size(s)); } =20 static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) { tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); - } else { - tcg_out_nop(s); - } + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); } =20 void tb_target_set_jmp_target(const TranslationBlock *tb, int n, @@ -1839,7 +1646,6 @@ static const TCGOutOpBinary outop_eqv =3D { .base.static_constraint =3D C_NotImplemented, }; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg= a1) { tcg_out_dsra(s, a0, a1, 32); @@ -1849,7 +1655,6 @@ static const TCGOutOpUnary outop_extrh_i64_i32 =3D { .base.static_constraint =3D C_O1_I1(r, r), .out_rr =3D tgen_extrh_i64_i32, }; -#endif =20 static void tgen_mul(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) @@ -2238,7 +2043,6 @@ static const TCGOutOpBswap outop_bswap32 =3D { .out_rr =3D tgen_bswap32, }; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg ret, TCGReg a= rg) { if (use_mips32r2_instructions) { @@ -2256,7 +2060,6 @@ static const TCGOutOpUnary outop_bswap64 =3D { .base.static_constraint =3D C_O1_I1(r, r), .out_rr =3D tgen_bswap64, }; -#endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ =20 static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) { @@ -2384,7 +2187,6 @@ static const TCGOutOpLoad outop_ld16s =3D { .out =3D tgen_ld16s, }; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 static void tgen_ld32u(TCGContext *s, TCGType type, TCGReg dest, TCGReg base, ptrdiff_t offset) { @@ -2406,7 +2208,6 @@ static const TCGOutOpLoad outop_ld32s =3D { .base.static_constraint =3D C_O1_I1(r, r), .out =3D tgen_ld32s, }; -#endif =20 static void tgen_st8_r(TCGContext *s, TCGType type, TCGReg data, TCGReg base, ptrdiff_t offset) @@ -2545,7 +2346,7 @@ static tcg_insn_unit *align_code_ptr(TCGContext *s) } =20 /* Stack frame parameters. */ -#define REG_SIZE (TCG_TARGET_REG_BITS / 8) +#define REG_SIZE 8 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZ= E) #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) =20 @@ -2577,17 +2378,15 @@ static void tcg_target_qemu_prologue(TCGContext *s) * with the address of the prologue, so we can use that instead * of TCG_REG_TB. */ -#if TCG_TARGET_REG_BITS =3D=3D 64 && !defined(__mips_abicalls) +#if !defined(__mips_abicalls) # error "Unknown mips abi" #endif tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, - TCG_TARGET_REG_BITS =3D=3D 64 ? TCG_REG_T9 : 0); + TCG_REG_T9); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } =20 - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs= [1]); - } + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); =20 /* Call generated code */ tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); @@ -2643,10 +2442,6 @@ static void tcg_target_qemu_prologue(TCGContext *s) /* t3 =3D dcba -- delay slot */ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - return; - } - /* * bswap32u -- unsigned 32-bit swap. a0 =3D ....abcd. */ @@ -2741,9 +2536,7 @@ static void tcg_target_init(TCGContext *s) { tcg_target_detect_isa(); tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffff; - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffff; - } + tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffff; =20 tcg_target_call_clobber_regs =3D 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); @@ -2774,9 +2567,7 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address = */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer = */ - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ - } + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ } =20 typedef struct { @@ -2794,7 +2585,7 @@ static const DebugFrame debug_frame =3D { .h.cie.id =3D -1, .h.cie.version =3D 1, .h.cie.code_align =3D 1, - .h.cie.data_align =3D -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ + .h.cie.data_align =3D -REG_SIZE & 0x7f, /* sleb128 */ .h.cie.return_column =3D TCG_REG_RA, =20 /* Total FDE size does not include the "len" member. */ --=20 2.43.0 From nobody Fri Nov 14 18:19:12 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760564383; cv=none; d=zohomail.com; s=zohoarc; b=QNaLDa+qInPh9p5KXJ0waDZEQE281aKktI7hNhxQor34NoehwxnpjFZNC92pKXhxuC+kemXrvgG15hlQcZUhwnXRkYV2b/SS2OE2eXkgbYwsIcf/1sQ1/hkTup818OrVc0HhVGjw4LujJaKczmZa8mkZMaET1pAIB4CVC+F1tqs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760564383; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=SqCRsRggw+NmDtKLMVf8Mr9OjYm8BzUFUWvu2nTrVOA=; b=JPDnO5OlCwN/izgl+z/Sz4S6cP2jHk1+UYWcuCfG7hv6B+F0lGoBWrmo5ZZcH1sQlCvE8pksX1joTERizfqlwW6DuOGL0+ZEz0hFZeYEhXmMWjR1vADCTU68AJtOKXtyqwrMnNwYcGhMKGGSGAjVo/tBXr79BGMOHZA3htrGwcA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760564383928311.86458235077396; Wed, 15 Oct 2025 14:39:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v99D6-0003c0-8r; Wed, 15 Oct 2025 17:39:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v99Cx-0003Zq-Ve for qemu-devel@nongnu.org; Wed, 15 Oct 2025 17:39:00 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v99Cu-0004zm-7w for qemu-devel@nongnu.org; Wed, 15 Oct 2025 17:38:55 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-2698384978dso503965ad.0 for ; Wed, 15 Oct 2025 14:38:50 -0700 (PDT) Received: from stoup.. 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Now that the 64-bit abi is the only one supported, we can use the DADD* instructions directly. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth --- tcg/mips/tcg-target.c.inc | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 8e7c0ea33f..83bf65d5ca 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -340,10 +340,6 @@ typedef enum { OPC_SYNC_ACQUIRE =3D OPC_SYNC | 0x11 << 6, OPC_SYNC_RELEASE =3D OPC_SYNC | 0x12 << 6, OPC_SYNC_RMB =3D OPC_SYNC | 0x13 << 6, - - /* Aliases for convenience. */ - ALIAS_PADD =3D sizeof(void *) =3D=3D 4 ? OPC_ADDU : OPC_DADDU, - ALIAS_PADDI =3D sizeof(void *) =3D=3D 4 ? OPC_ADDIU : OPC_DADDIU, } MIPSInsn; =20 /* @@ -700,7 +696,7 @@ static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, T= CGReg data, if (ofs !=3D lo) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); if (addr !=3D TCG_REG_ZERO) { - tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); + tcg_out_opc_reg(s, OPC_DADDU, TCG_TMP0, TCG_TMP0, addr); } addr =3D TCG_TMP0; } @@ -1109,7 +1105,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); =20 /* Add the tlb_table pointer, creating the CPUTLBEntry address. */ - tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); + tcg_out_opc_reg(s, OPC_DADDU, TCG_TMP3, TCG_TMP3, TCG_TMP1); =20 /* Load the tlb comparator. */ if (addr_type =3D=3D TCG_TYPE_I32) { @@ -1148,7 +1144,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, =20 /* delay slot */ base =3D TCG_TMP3; - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addr); + tcg_out_opc_reg(s, OPC_DADDU, base, TCG_TMP3, addr); } else { if (a_mask && (use_mips32r6_instructions || a_bits !=3D s_bits)) { ldst =3D new_ldst_label(s); @@ -1177,9 +1173,9 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, } if (guest_base) { if (guest_base =3D=3D (int16_t)guest_base) { - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_ba= se); + tcg_out_opc_imm(s, OPC_DADDIU, TCG_REG_A0, base, guest_bas= e); } else { - tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, + tcg_out_opc_reg(s, OPC_DADDU, TCG_REG_A0, base, TCG_GUEST_BASE_REG); } base =3D TCG_REG_A0; @@ -1417,7 +1413,7 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t = a0) } else { base =3D TCG_REG_V0; tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); - tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); + tcg_out_opc_reg(s, OPC_DADDU, base, base, TCG_REG_TB); } } if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { @@ -1425,7 +1421,7 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t = a0) tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); } /* delay slot */ - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo); + tcg_out_opc_imm(s, OPC_DADDIU, TCG_REG_V0, base, lo); } =20 static void tcg_out_goto_tb(TCGContext *s, int which) @@ -1444,7 +1440,7 @@ static void tcg_out_goto_tb(TCGContext *s, int which) =20 set_jmp_reset_offset(s, which); /* For the unlinked case, need to reset TCG_REG_TB. */ - tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, + tcg_out_ldst(s, OPC_DADDIU, TCG_REG_TB, TCG_REG_TB, -tcg_current_code_size(s)); } =20 @@ -2366,7 +2362,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); =20 /* TB prologue */ - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); + tcg_out_opc_imm(s, OPC_DADDIU, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); for (i =3D 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], TCG_REG_SP, SAVE_OFS + i * REG_SIZE); @@ -2409,7 +2405,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 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See previous commit for rationale. Signed-off-by: Philippe Mathieu-Daud=C3=A9 [rth: Retain _ARCH_PPC64 check in udiv_qrnnd] Signed-off-by: Richard Henderson Message-ID: <20251014173900.87497-4-philmd@linaro.org> Reviewed-by: Thomas Huth --- include/qemu/timer.h | 13 +------------ disas/disas-host.c | 4 +--- util/cacheflush.c | 4 ++-- configure | 19 +++++-------------- 4 files changed, 9 insertions(+), 31 deletions(-) diff --git a/include/qemu/timer.h b/include/qemu/timer.h index aec730ac25..406d741120 100644 --- a/include/qemu/timer.h +++ b/include/qemu/timer.h @@ -850,12 +850,11 @@ static inline int64_t get_clock(void) /*******************************************/ /* host CPU ticks (if available) */ =20 -#if defined(_ARCH_PPC) +#if defined(_ARCH_PPC64) =20 static inline int64_t cpu_get_host_ticks(void) { int64_t retval; -#ifdef _ARCH_PPC64 /* This reads timebase in one 64bit go and includes Cell workaround fr= om: http://ozlabs.org/pipermail/linuxppc-dev/2006-October/027052.html */ @@ -863,16 +862,6 @@ static inline int64_t cpu_get_host_ticks(void) "cmpwi %0,0\n\t" "beq- $-8" : "=3Dr" (retval)); -#else - /* http://ozlabs.org/pipermail/linuxppc-dev/1999-October/003889.html */ - unsigned long junk; - __asm__ __volatile__ ("mfspr %1,269\n\t" /* mftbu */ - "mfspr %L0,268\n\t" /* mftb */ - "mfspr %0,269\n\t" /* mftbu */ - "cmpw %0,%1\n\t" - "bne $-16" - : "=3Dr" (retval), "=3Dr" (junk)); -#endif return retval; } =20 diff --git a/disas/disas-host.c b/disas/disas-host.c index 8146fafe80..4b06f41fa6 100644 --- a/disas/disas-host.c +++ b/disas/disas-host.c @@ -56,11 +56,9 @@ static void initialize_debug_host(CPUDebug *s) s->info.cap_mode =3D CS_MODE_64; s->info.cap_insn_unit =3D 1; s->info.cap_insn_split =3D 8; -#elif defined(_ARCH_PPC) +#elif defined(_ARCH_PPC64) s->info.cap_arch =3D CS_ARCH_PPC; -# ifdef _ARCH_PPC64 s->info.cap_mode =3D CS_MODE_64; -# endif #elif defined(__riscv) #if defined(_ILP32) || (__riscv_xlen =3D=3D 32) s->info.print_insn =3D print_insn_riscv32; diff --git a/util/cacheflush.c b/util/cacheflush.c index 17c58918de..69c9614e2c 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -153,7 +153,7 @@ static void arch_cache_info(int *isize, int *dsize) } } =20 -#elif defined(_ARCH_PPC) && defined(__linux__) +#elif defined(_ARCH_PPC64) && defined(__linux__) # include "elf.h" =20 static void arch_cache_info(int *isize, int *dsize) @@ -187,7 +187,7 @@ static void fallback_cache_info(int *isize, int *dsize) } else if (*dsize) { *isize =3D *dsize; } else { -#if defined(_ARCH_PPC) +#if defined(_ARCH_PPC64) /* * For PPC, we're going to use the cache sizes computed for * flush_idcache_range. Which means that we must use the diff --git a/configure b/configure index 8263f81370..a2f66f7ff9 100755 --- a/configure +++ b/configure @@ -391,15 +391,11 @@ elif check_define __sparc__ ; then else cpu=3D"sparc" fi -elif check_define _ARCH_PPC ; then - if check_define _ARCH_PPC64 ; then - if check_define _LITTLE_ENDIAN ; then - cpu=3D"ppc64le" - else - cpu=3D"ppc64" - fi +elif check_define _ARCH_PPC64 ; then + if check_define _LITTLE_ENDIAN ; then + cpu=3D"ppc64le" else - cpu=3D"ppc" + cpu=3D"ppc64" fi elif check_define __mips__ ; then if check_define __mips64 ; then @@ -472,11 +468,6 @@ case "$cpu" in linux_arch=3Dmips ;; =20 - ppc) - host_arch=3Dppc - linux_arch=3Dpowerpc - CPU_CFLAGS=3D"-m32" - ;; ppc64) host_arch=3Dppc64 linux_arch=3Dpowerpc @@ -1471,7 +1462,7 @@ probe_target_compiler() { container_image=3Ddebian-all-test-cross container_cross_prefix=3Dmips64-linux-gnuabi64- ;; - ppc|ppc64|ppc64le) + ppc64|ppc64le) container_image=3Ddebian-all-test-cross container_cross_prefix=3Dpowerpc${target_arch#ppc}-linux-gnu- ;; --=20 2.43.0 From nobody Fri Nov 14 18:19:12 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760564452; cv=none; d=zohomail.com; s=zohoarc; b=HWa04MAal4AG/MSQSGcEx9rY3aTrs575CzK50tLnp9uzBDwMud+mE9ScFSuYWQ+pcyxd/tWGRUQZ8e0vPuj1/Srf6liBnMubW3zb7e/5SEYz0O6XlB4LcYsawDzoHppQAHHN2QwB8U8NchJlCKVuFa2T/ruOJS+jQRHVyr5WUPU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760564452; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=x12NKAEaKijEy74pcpn85abMXE4ifHPmR+0QV24arY0=; b=Y3eISO3Olc4bwfnRUhP7AoUYk2UVKgF3sAQKIqrWW+DcWJ2lydlw8fMnhsZU61f2SMnWQVftAkLzKWPLyjXysEhLUmz71n2coDgggiOw9MkgfV33+6GaAKbuwOfAc+d9lrwwPA9k+CXwKrP5VWOsU6a5uOoEL7AuPsNiF6KpmV0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17605644521656.427227527939522; Wed, 15 Oct 2025 14:40:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v99D6-0003c1-Bn; Wed, 15 Oct 2025 17:39:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v99D0-0003a0-2f for qemu-devel@nongnu.org; Wed, 15 Oct 2025 17:39:01 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v99Cu-000502-P0 for qemu-devel@nongnu.org; Wed, 15 Oct 2025 17:38:57 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-27ee41e0798so926335ad.1 for ; Wed, 15 Oct 2025 14:38:52 -0700 (PDT) Received: from stoup.. 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The next release being v10.2, we can remove the TCG backend for 32-bit PPC hosts. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-ID: <20251014173900.87497-2-philmd@linaro.org> --- tcg/ppc/tcg-target-has.h | 5 +- tcg/ppc/tcg-target-reg-bits.h | 8 +- tcg/ppc/tcg-target.c.inc | 388 +++++++--------------------------- 3 files changed, 81 insertions(+), 320 deletions(-) diff --git a/tcg/ppc/tcg-target-has.h b/tcg/ppc/tcg-target-has.h index 81ec5aece7..a3711feeae 100644 --- a/tcg/ppc/tcg-target-has.h +++ b/tcg/ppc/tcg-target-has.h @@ -17,12 +17,9 @@ #define have_vsx (cpuinfo & CPUINFO_VSX) =20 /* optional instructions */ -#if TCG_TARGET_REG_BITS =3D=3D 64 #define TCG_TARGET_HAS_extr_i64_i32 0 -#endif =20 -#define TCG_TARGET_HAS_qemu_ldst_i128 \ - (TCG_TARGET_REG_BITS =3D=3D 64 && have_isa_2_07) +#define TCG_TARGET_HAS_qemu_ldst_i128 have_isa_2_07 =20 #define TCG_TARGET_HAS_tst 1 =20 diff --git a/tcg/ppc/tcg-target-reg-bits.h b/tcg/ppc/tcg-target-reg-bits.h index 0efa80e7e0..3a15d7bee4 100644 --- a/tcg/ppc/tcg-target-reg-bits.h +++ b/tcg/ppc/tcg-target-reg-bits.h @@ -7,10 +7,10 @@ #ifndef TCG_TARGET_REG_BITS_H #define TCG_TARGET_REG_BITS_H =20 -#ifdef _ARCH_PPC64 -# define TCG_TARGET_REG_BITS 64 -#else -# define TCG_TARGET_REG_BITS 32 +#ifndef _ARCH_PPC64 +# error Expecting 64-bit host architecture #endif =20 +#define TCG_TARGET_REG_BITS 64 + #endif diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index b8b23d44d5..dad9d24d48 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -29,35 +29,18 @@ * Apple XCode does not define _CALL_DARWIN. * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV or _CALL_AIX. */ -#if TCG_TARGET_REG_BITS =3D=3D 64 -# ifdef _CALL_AIX +#ifdef _CALL_AIX /* ok */ -# elif defined(_CALL_ELF) && _CALL_ELF =3D=3D 1 +#elif defined(_CALL_ELF) && _CALL_ELF =3D=3D 1 # define _CALL_AIX -# elif defined(_CALL_ELF) && _CALL_ELF =3D=3D 2 +#elif defined(_CALL_ELF) && _CALL_ELF =3D=3D 2 /* ok */ -# else -# error "Unknown ABI" -# endif #else -# if defined(_CALL_SYSV) || defined(_CALL_DARWIN) - /* ok */ -# elif defined(__APPLE__) -# define _CALL_DARWIN -# elif defined(__ELF__) -# define _CALL_SYSV -# else # error "Unknown ABI" -# endif #endif =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND -# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL -#else -# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL -# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF -#endif +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL #ifdef _CALL_SYSV # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN # define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF @@ -81,7 +64,7 @@ #define TCG_VEC_TMP2 TCG_REG_V1 =20 #define TCG_REG_TB TCG_REG_R31 -#define USE_REG_TB (TCG_TARGET_REG_BITS =3D=3D 64 && !have_isa_3_00) +#define USE_REG_TB !have_isa_3_00 =20 /* Shorthand for size of a pointer. Avoid promotion to unsigned. */ #define SZP ((int)sizeof(void *)) @@ -327,8 +310,7 @@ static bool tcg_target_const_match(int64_t sval, int ct, if (uval =3D=3D (uint32_t)uval && mask_operand(uval, &mb, &me)= ) { return 1; } - if (TCG_TARGET_REG_BITS =3D=3D 64 && - mask64_operand(uval << clz64(uval), &mb, &me)) { + if (mask64_operand(uval << clz64(uval), &mb, &me)) { return 1; } return 0; @@ -857,10 +839,8 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, T= CGReg ret, TCGReg arg) return true; } switch (type) { - case TCG_TYPE_I64: - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); - /* fallthru */ case TCG_TYPE_I32: + case TCG_TYPE_I64: if (ret < TCG_REG_V0) { if (arg < TCG_REG_V0) { tcg_out32(s, OR | SAB(arg, ret, arg)); @@ -898,7 +878,6 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) static void tcg_out_rld_rc(TCGContext *s, int op, TCGReg ra, TCGReg rs, int sh, int mb, bool rc) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); sh =3D SH(sh & 0x1f) | (((sh >> 5) & 1) << 1); mb =3D MB64((mb >> 5) | ((mb << 1) & 0x3f)); tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb | rc); @@ -946,13 +925,11 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg dst,= TCGReg src) =20 static void tcg_out_ext32s(TCGContext *s, TCGReg dst, TCGReg src) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out32(s, EXTSW | RA(dst) | RS(src)); } =20 static void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_rld(s, RLDICL, dst, src, 0, 32); } =20 @@ -968,7 +945,6 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg = dst, TCGReg src) =20 static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_mov(s, TCG_TYPE_I32, rd, rn); } =20 @@ -1037,9 +1013,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType t= ype, TCGReg ret, tcg_target_long tmp; int shift; =20 - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); - - if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I32) { + if (type =3D=3D TCG_TYPE_I32) { arg =3D (int32_t)arg; } =20 @@ -1076,7 +1050,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType t= ype, TCGReg ret, =20 /* Load 32-bit immediates with two insns. Note that we've already eliminated bare ADDIS, so we know both insns are required. */ - if (TCG_TARGET_REG_BITS =3D=3D 32 || arg =3D=3D (int32_t)arg) { + if (arg =3D=3D (int32_t)arg) { tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); tcg_out32(s, ORI | SAI(ret, ret, arg)); return; @@ -1227,19 +1201,10 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType= type, unsigned vece, if (have_vsx) { load_insn =3D type =3D=3D TCG_TYPE_V64 ? LXSDX : LXVDSX; load_insn |=3D VRT(ret) | RB(TCG_REG_TMP1); - if (TCG_TARGET_REG_BITS =3D=3D 64) { - new_pool_label(s, val, rel, s->code_ptr, add); - } else { - new_pool_l2(s, rel, s->code_ptr, add, val >> 32, val); - } + new_pool_label(s, val, rel, s->code_ptr, add); } else { load_insn =3D LVX | VRT(ret) | RB(TCG_REG_TMP1); - if (TCG_TARGET_REG_BITS =3D=3D 64) { - new_pool_l2(s, rel, s->code_ptr, add, val, val); - } else { - new_pool_l4(s, rel, s->code_ptr, add, - val >> 32, val, val >> 32, val); - } + new_pool_l2(s, rel, s->code_ptr, add, val, val); } =20 if (USE_REG_TB) { @@ -1351,7 +1316,6 @@ static void tcg_out_andi64(TCGContext *s, TCGReg dst,= TCGReg src, uint64_t c) { int mb, me; =20 - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); if (mask64_operand(c, &mb, &me)) { if (mb =3D=3D 0) { tcg_out_rld(s, RLDICR, dst, src, 0, me); @@ -1543,7 +1507,6 @@ static void tcg_out_ld(TCGContext *s, TCGType type, T= CGReg ret, break; case TCG_TYPE_I64: if (ret < TCG_REG_V0) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_mem_long(s, LD, LDX, ret, base, offset); break; } @@ -1598,7 +1561,6 @@ static void tcg_out_st(TCGContext *s, TCGType type, T= CGReg arg, break; case TCG_TYPE_I64: if (arg < TCG_REG_V0) { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_mem_long(s, STD, STDX, arg, base, offset); break; } @@ -1641,7 +1603,7 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType= type, TCGArg val, static void tcg_out_test(TCGContext *s, TCGReg dest, TCGReg arg1, TCGArg a= rg2, bool const_arg2, TCGType type, bool rc) { - int mb, me; + int mb, me, sh; =20 if (!const_arg2) { tcg_out32(s, AND | SAB(arg1, dest, arg2) | rc); @@ -1664,12 +1626,10 @@ static void tcg_out_test(TCGContext *s, TCGReg dest= , TCGReg arg1, TCGArg arg2, tcg_out_rlw_rc(s, RLWINM, dest, arg1, 0, mb, me, rc); return; } - if (TCG_TARGET_REG_BITS =3D=3D 64) { - int sh =3D clz64(arg2); - if (mask64_operand(arg2 << sh, &mb, &me)) { - tcg_out_rld_rc(s, RLDICR, dest, arg1, sh, me, rc); - return; - } + sh =3D clz64(arg2); + if (mask64_operand(arg2 << sh, &mb, &me)) { + tcg_out_rld_rc(s, RLDICR, dest, arg1, sh, me, rc); + return; } /* Constraints should satisfy this. */ g_assert_not_reached(); @@ -1680,8 +1640,6 @@ static void tcg_out_cmp(TCGContext *s, int cond, TCGA= rg arg1, TCGArg arg2, { uint32_t op; =20 - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); - /* * Simplify the comparisons below wrt CMPI. * All of the tests are 16-bit, so a 32-bit sign extend always works. @@ -1747,7 +1705,7 @@ static void tcg_out_cmp(TCGContext *s, int cond, TCGA= rg arg1, TCGArg arg2, static void tcg_out_setcond_eq0(TCGContext *s, TCGType type, TCGReg dst, TCGReg src, bool neg) { - if (neg && (TCG_TARGET_REG_BITS =3D=3D 32 || type =3D=3D TCG_TYPE_I64)= ) { + if (neg && type =3D=3D TCG_TYPE_I64) { /* * X !=3D 0 implies X + -1 generates a carry. * RT =3D (~X + X) + CA @@ -1774,7 +1732,7 @@ static void tcg_out_setcond_eq0(TCGContext *s, TCGTyp= e type, static void tcg_out_setcond_ne0(TCGContext *s, TCGType type, TCGReg dst, TCGReg src, bool neg) { - if (!neg && (TCG_TARGET_REG_BITS =3D=3D 32 || type =3D=3D TCG_TYPE_I64= )) { + if (!neg && type =3D=3D TCG_TYPE_I64) { /* * X !=3D 0 implies X + -1 generates a carry. Extra addition * trickery means: R =3D X-1 + ~X + C =3D X-1 + (-X+1) + C =3D C. @@ -1814,8 +1772,6 @@ static void tcg_out_setcond(TCGContext *s, TCGType ty= pe, TCGCond cond, int sh; bool inv; =20 - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); - /* Ignore high bits of a potential constant arg2. */ if (type =3D=3D TCG_TYPE_I32) { arg2 =3D (uint32_t)arg2; @@ -2117,109 +2073,6 @@ static void tcg_out_cntxz(TCGContext *s, TCGType ty= pe, uint32_t opc, } } =20 -static void tcg_out_cmp2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, - TCGArg bl, bool blconst, TCGArg bh, bool bhconst) -{ - static const struct { uint8_t bit1, bit2; } bits[] =3D { - [TCG_COND_LT ] =3D { CR_LT, CR_LT }, - [TCG_COND_LE ] =3D { CR_LT, CR_GT }, - [TCG_COND_GT ] =3D { CR_GT, CR_GT }, - [TCG_COND_GE ] =3D { CR_GT, CR_LT }, - [TCG_COND_LTU] =3D { CR_LT, CR_LT }, - [TCG_COND_LEU] =3D { CR_LT, CR_GT }, - [TCG_COND_GTU] =3D { CR_GT, CR_GT }, - [TCG_COND_GEU] =3D { CR_GT, CR_LT }, - }; - - TCGCond cond2; - int op, bit1, bit2; - - switch (cond) { - case TCG_COND_EQ: - op =3D CRAND; - goto do_equality; - case TCG_COND_NE: - op =3D CRNAND; - do_equality: - tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32); - tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32); - tcg_out32(s, op | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); - break; - - case TCG_COND_TSTEQ: - case TCG_COND_TSTNE: - if (blconst) { - tcg_out_andi32(s, TCG_REG_R0, al, bl); - } else { - tcg_out32(s, AND | SAB(al, TCG_REG_R0, bl)); - } - if (bhconst) { - tcg_out_andi32(s, TCG_REG_TMP1, ah, bh); - } else { - tcg_out32(s, AND | SAB(ah, TCG_REG_TMP1, bh)); - } - tcg_out32(s, OR | SAB(TCG_REG_R0, TCG_REG_R0, TCG_REG_TMP1) | 1); - break; - - case TCG_COND_LT: - case TCG_COND_LE: - case TCG_COND_GT: - case TCG_COND_GE: - case TCG_COND_LTU: - case TCG_COND_LEU: - case TCG_COND_GTU: - case TCG_COND_GEU: - bit1 =3D bits[cond].bit1; - bit2 =3D bits[cond].bit2; - op =3D (bit1 !=3D bit2 ? CRANDC : CRAND); - cond2 =3D tcg_unsigned_cond(cond); - - tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32); - tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32); - tcg_out32(s, op | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2)); - tcg_out32(s, CROR | BT(0, CR_EQ) | BA(6, bit1) | BB(0, CR_EQ)); - break; - - default: - g_assert_not_reached(); - } -} - -static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, - TCGArg bh, bool const_bh) -{ - tcg_out_cmp2(s, cond, al, ah, bl, const_bl, bh, const_bh); - tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(0)); - tcg_out_rlw(s, RLWINM, ret, TCG_REG_R0, CR_EQ + 0*4 + 1, 31, 31); -} - -#if TCG_TARGET_REG_BITS !=3D 32 -__attribute__((unused)) -#endif -static const TCGOutOpSetcond2 outop_setcond2 =3D { - .base.static_constraint =3D C_O1_I4(r, r, r, rU, rC), - .out =3D tgen_setcond2, -}; - -static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, - TCGArg bh, bool const_bh, TCGLabel *l) -{ - assert(TCG_TARGET_REG_BITS =3D=3D 32); - tcg_out_cmp2(s, cond, al, ah, bl, const_bl, bh, const_bh); - tcg_out_bc_lab(s, TCG_COND_EQ, l); -} - -#if TCG_TARGET_REG_BITS !=3D 32 -__attribute__((unused)) -#endif -static const TCGOutOpBrcond2 outop_brcond2 =3D { - .base.static_constraint =3D C_O0_I4(r, r, rU, rC), - .out =3D tgen_brcond2, -}; - static void tcg_out_mb(TCGContext *s, unsigned a0) { uint32_t insn; @@ -2438,13 +2291,8 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContex= t *s, HostAddress *h, tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off); =20 /* Extract the page index, shifted into place for tlb index. */ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_shri32(s, TCG_REG_R0, addr, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - } else { - tcg_out_shri64(s, TCG_REG_R0, addr, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - } + tcg_out_shri64(s, TCG_REG_R0, addr, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); =20 /* @@ -2453,8 +2301,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, * We will ignore the high bits with tcg_out_cmp(..., addr_type). */ if (cmp_off =3D=3D 0) { - tcg_out32(s, (TCG_TARGET_REG_BITS =3D=3D 64 ? LDUX : LWZUX) - | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)); + tcg_out32(s, LDUX | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TM= P2)); } else { tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP= 2)); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP1, cmp_of= f); @@ -2464,51 +2311,36 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, * Load the TLB addend for use on the fast path. * Do this asap to minimize any load use delay. */ - if (TCG_TARGET_REG_BITS =3D=3D 64 || addr_type =3D=3D TCG_TYPE_I32= ) { - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, - offsetof(CPUTLBEntry, addend)); - } + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, + offsetof(CPUTLBEntry, addend)); =20 /* Clear the non-page, non-alignment bits from the address in R0. = */ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - /* - * We don't support unaligned accesses on 32-bits. - * Preserve the bottom bits and thus trigger a comparison - * failure on unaligned accesses. - */ - if (a_bits < s_bits) { - a_bits =3D s_bits; - } - tcg_out_rlw(s, RLWINM, TCG_REG_R0, addr, 0, + TCGReg t =3D addr; + + /* + * If the access is unaligned, we need to make sure we fail if we + * cross a page boundary. The trick is to add the access size-1 + * to the address before masking the low bits. That will make the + * address overflow to the next page if we cross a page boundary, + * which will then force a mismatch of the TLB compare. + */ + if (a_bits < s_bits) { + unsigned a_mask =3D (1 << a_bits) - 1; + unsigned s_mask =3D (1 << s_bits) - 1; + tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); + t =3D TCG_REG_R0; + } + + /* Mask the address for the requested alignment. */ + if (addr_type =3D=3D TCG_TYPE_I32) { + tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); + } else if (a_bits =3D=3D 0) { + tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS= ); } else { - TCGReg t =3D addr; - - /* - * If the access is unaligned, we need to make sure we fail if= we - * cross a page boundary. The trick is to add the access size= -1 - * to the address before masking the low bits. That will make= the - * address overflow to the next page if we cross a page bounda= ry, - * which will then force a mismatch of the TLB compare. - */ - if (a_bits < s_bits) { - unsigned a_mask =3D (1 << a_bits) - 1; - unsigned s_mask =3D (1 << s_bits) - 1; - tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); - t =3D TCG_REG_R0; - } - - /* Mask the address for the requested alignment. */ - if (addr_type =3D=3D TCG_TYPE_I32) { - tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, - (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); - } else if (a_bits =3D=3D 0) { - tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_= BITS); - } else { - tcg_out_rld(s, RLDICL, TCG_REG_R0, t, - 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bi= ts); - tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE= _BITS, 0); - } + tcg_out_rld(s, RLDICL, TCG_REG_R0, t, + 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits); + tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BIT= S, 0); } =20 /* Full comparison into cr0. */ @@ -2537,7 +2369,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, h->base =3D guest_base ? TCG_GUEST_BASE_REG : 0; } =20 - if (TCG_TARGET_REG_BITS =3D=3D 64 && addr_type =3D=3D TCG_TYPE_I32) { + if (addr_type =3D=3D TCG_TYPE_I32) { /* Zero-extend the guest address for use in the host address. */ tcg_out_ext32u(s, TCG_REG_TMP2, addr); h->index =3D TCG_REG_TMP2; @@ -2554,40 +2386,22 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOp opc =3D get_memop(oi); TCGLabelQemuLdst *ldst; HostAddress h; + uint32_t insn =3D qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; =20 ldst =3D prepare_host_addr(s, &h, addr, oi, true); =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - if (opc & MO_BSWAP) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); - tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); - tcg_out32(s, LWBRX | TAB(datahi, h.base, TCG_REG_R0)); - } else if (h.base !=3D 0) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); - tcg_out32(s, LWZX | TAB(datahi, h.base, h.index)); - tcg_out32(s, LWZX | TAB(datalo, h.base, TCG_REG_R0)); - } else if (h.index =3D=3D datahi) { - tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); - tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); - } else { - tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); - tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); - } + if (!have_isa_2_06 && insn =3D=3D LDBRX) { + tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); + tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); + tcg_out32(s, LWBRX | TAB(TCG_REG_R0, h.base, TCG_REG_R0)); + tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0); + } else if (insn) { + tcg_out32(s, insn | TAB(datalo, h.base, h.index)); } else { - uint32_t insn =3D qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; - if (!have_isa_2_06 && insn =3D=3D LDBRX) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); - tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); - tcg_out32(s, LWBRX | TAB(TCG_REG_R0, h.base, TCG_REG_R0)); - tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0); - } else if (insn) { - tcg_out32(s, insn | TAB(datalo, h.base, h.index)); - } else { - insn =3D qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; - tcg_out32(s, insn | TAB(datalo, h.base, h.index)); - tcg_out_movext(s, TCG_TYPE_REG, datalo, - TCG_TYPE_REG, opc & MO_SSIZE, datalo); - } + insn =3D qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; + tcg_out32(s, insn | TAB(datalo, h.base, h.index)); + tcg_out_movext(s, TCG_TYPE_REG, datalo, + TCG_TYPE_REG, opc & MO_SSIZE, datalo); } =20 if (ldst) { @@ -2604,32 +2418,17 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOp opc =3D get_memop(oi); TCGLabelQemuLdst *ldst; HostAddress h; + uint32_t insn =3D qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)]; =20 ldst =3D prepare_host_addr(s, &h, addr, oi, false); =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - if (opc & MO_BSWAP) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); - tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); - tcg_out32(s, STWBRX | SAB(datahi, h.base, TCG_REG_R0)); - } else if (h.base !=3D 0) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); - tcg_out32(s, STWX | SAB(datahi, h.base, h.index)); - tcg_out32(s, STWX | SAB(datalo, h.base, TCG_REG_R0)); - } else { - tcg_out32(s, STW | TAI(datahi, h.index, 0)); - tcg_out32(s, STW | TAI(datalo, h.index, 4)); - } + if (!have_isa_2_06 && insn =3D=3D STDBRX) { + tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); + tcg_out32(s, ADDI | TAI(TCG_REG_TMP2, h.index, 4)); + tcg_out_shri64(s, TCG_REG_R0, datalo, 32); + tcg_out32(s, STWBRX | SAB(TCG_REG_R0, h.base, TCG_REG_TMP2)); } else { - uint32_t insn =3D qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)]; - if (!have_isa_2_06 && insn =3D=3D STDBRX) { - tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); - tcg_out32(s, ADDI | TAI(TCG_REG_TMP2, h.index, 4)); - tcg_out_shri64(s, TCG_REG_R0, datalo, 32); - tcg_out32(s, STWBRX | SAB(TCG_REG_R0, h.base, TCG_REG_TMP2)); - } else { - tcg_out32(s, insn | SAB(datalo, h.base, h.index)); - } + tcg_out32(s, insn | SAB(datalo, h.base, h.index)); } =20 if (ldst) { @@ -2709,16 +2508,11 @@ static const TCGOutOpQemuLdSt outop_qemu_ld =3D { static void tgen_qemu_ld2(TCGContext *s, TCGType type, TCGReg datalo, TCGReg datahi, TCGReg addr, MemOpIdx oi) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_qemu_ld(s, datalo, datahi, addr, oi, type); - } else { - tcg_out_qemu_ldst_i128(s, datalo, datahi, addr, oi, true); - } + tcg_out_qemu_ldst_i128(s, datalo, datahi, addr, oi, true); } =20 static const TCGOutOpQemuLdSt2 outop_qemu_ld2 =3D { - .base.static_constraint =3D - TCG_TARGET_REG_BITS =3D=3D 64 ? C_N1O1_I1(o, m, r) : C_O2_I1(r, r,= r), + .base.static_constraint =3D C_N1O1_I1(o, m, r), .out =3D tgen_qemu_ld2, }; =20 @@ -2736,16 +2530,11 @@ static const TCGOutOpQemuLdSt outop_qemu_st =3D { static void tgen_qemu_st2(TCGContext *s, TCGType type, TCGReg datalo, TCGReg datahi, TCGReg addr, MemOpIdx oi) { - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_qemu_st(s, datalo, datahi, addr, oi, type); - } else { - tcg_out_qemu_ldst_i128(s, datalo, datahi, addr, oi, false); - } + tcg_out_qemu_ldst_i128(s, datalo, datahi, addr, oi, false); } =20 static const TCGOutOpQemuLdSt2 outop_qemu_st2 =3D { - .base.static_constraint =3D - TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I3(o, m, r) : C_O0_I3(r, r, r= ), + .base.static_constraint =3D C_O0_I3(o, m, r), .out =3D tgen_qemu_st2, }; =20 @@ -2767,16 +2556,11 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int = count) #elif defined(_CALL_DARWIN) # define LINK_AREA_SIZE (6 * SZR) # define LR_OFFSET (2 * SZR) -#elif TCG_TARGET_REG_BITS =3D=3D 64 +#else # if defined(_CALL_ELF) && _CALL_ELF =3D=3D 2 # define LINK_AREA_SIZE (4 * SZR) # define LR_OFFSET (1 * SZR) # endif -#else /* TCG_TARGET_REG_BITS =3D=3D 32 */ -# if defined(_CALL_SYSV) -# define LINK_AREA_SIZE (2 * SZR) -# define LR_OFFSET (1 * SZR) -# endif #endif #ifndef LR_OFFSET # error "Unhandled abi" @@ -3107,7 +2891,6 @@ static void tgen_eqv(TCGContext *s, TCGType type, tcg_out32(s, EQV | SAB(a1, a0, a2)); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg= a1) { tcg_out_shri64(s, a0, a1, 32); @@ -3117,7 +2900,6 @@ static const TCGOutOpUnary outop_extrh_i64_i32 =3D { .base.static_constraint =3D C_O1_I1(r, r), .out_rr =3D tgen_extrh_i64_i32, }; -#endif =20 static void tgen_divs(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, TCGReg a2) @@ -3596,7 +3378,6 @@ static const TCGOutOpBswap outop_bswap32 =3D { .out_rr =3D tgen_bswap32, }; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg dst, TCGReg s= rc) { TCGReg t0 =3D dst =3D=3D src ? TCG_REG_R0 : dst; @@ -3639,7 +3420,6 @@ static const TCGOutOpUnary outop_bswap64 =3D { .base.static_constraint =3D C_O1_I1(r, r), .out_rr =3D tgen_bswap64, }; -#endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ =20 static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) { @@ -3776,7 +3556,6 @@ static const TCGOutOpLoad outop_ld16s =3D { .out =3D tgen_ld16s, }; =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 static void tgen_ld32u(TCGContext *s, TCGType type, TCGReg dest, TCGReg base, ptrdiff_t offset) { @@ -3798,7 +3577,6 @@ static const TCGOutOpLoad outop_ld32s =3D { .base.static_constraint =3D C_O1_I1(r, r), .out =3D tgen_ld32s, }; -#endif =20 static void tgen_st8(TCGContext *s, TCGType type, TCGReg data, TCGReg base, ptrdiff_t offset) @@ -4278,14 +4056,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, tcg_out_bitsel_vec(s, a0, a1, a2, args[3]); return; =20 - case INDEX_op_dup2_vec: - assert(TCG_TARGET_REG_BITS =3D=3D 32); - /* With inputs a1 =3D xLxx, a2 =3D xHxx */ - tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 =3D xx= HL */ - tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp =3D HL= xx */ - tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 =3D HL= HL */ - return; - case INDEX_op_ppc_mrgh_vec: insn =3D mrgh_op[vece]; break; @@ -4311,6 +4081,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, =20 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ + case INDEX_op_dup2_vec: default: g_assert_not_reached(); } @@ -4438,8 +4209,7 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne= d flags) case INDEX_op_qemu_st: return C_O0_I2(r, r); case INDEX_op_qemu_st2: - return TCG_TARGET_REG_BITS =3D=3D 64 - ? C_O0_I3(o, m, r) : C_O0_I3(r, r, r); + return C_O0_I3(o, m, r); =20 case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -4549,9 +4319,7 @@ static void tcg_target_init(TCGContext *s) #if defined(_CALL_SYSV) tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */ #endif -#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS =3D=3D 64 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ -#endif tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1); @@ -4572,11 +4340,7 @@ typedef struct { /* We're expecting a 2 byte uleb128 encoded value. */ QEMU_BUILD_BUG_ON(FRAME_SIZE >=3D (1 << 14)); =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -# define ELF_HOST_MACHINE EM_PPC64 -#else -# define ELF_HOST_MACHINE EM_PPC -#endif +#define ELF_HOST_MACHINE EM_PPC64 =20 static DebugFrame debug_frame =3D { .cie.len =3D sizeof(DebugFrameCIE)-4, /* length after .len member */ --=20 2.43.0 From nobody Fri Nov 14 18:19:12 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760564419; cv=none; d=zohomail.com; s=zohoarc; b=OVxx6ACqqe4KCnyHWpbDPtjs1eDSk2taqCmgvb+O5hzJ/igiODdwMBkeGvHC5BMK/5RG/M8J+iLZOARxXHoWJHfIzHeJDwTialKtEMHGHhx6YPfcMGVjHqV7uqX8JPAp7e0EXwvBMe761n8KqzZ/afXj3OW7+onKCmIz2kjhYOk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760564419; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3CC+r7Wb6n6cAdbv0+2LZtn+JgBjXFbtsFceXgXxGGs=; b=dk1KSjlilT0mKCp2hefbb5K3yxUqLL5NpR8og5rq8GNTcYAv+vTNNBCPmbiNFWOnASLBmKkxxGE1ZZXsCjBdXNwIg2/LFN9dbtLX8ItG5lsCMXnDaZZlRDKvzQfb1EeNGvqkJZOO5Fh+BNfhb6BTLTX8m02WNMk5ITB+z0EUJ28= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760564419697845.1909130334226; Wed, 15 Oct 2025 14:40:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v99DB-0003ee-N3; Wed, 15 Oct 2025 17:39:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v99Cy-0003Zr-Gg for qemu-devel@nongnu.org; Wed, 15 Oct 2025 17:39:00 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v99Cw-00050G-Qa for qemu-devel@nongnu.org; Wed, 15 Oct 2025 17:38:56 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-267f0fe72a1so466665ad.2 for ; Wed, 15 Oct 2025 14:38:53 -0700 (PDT) Received: from stoup.. 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Fixes: 86fe5c2597c ("tcg: Convert qemu_st{2} to TCGOutOpLdSt{2}") Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 5 ----- 1 file changed, 5 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index dad9d24d48..85cda6ecaa 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -4206,11 +4206,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) { switch (op) { - case INDEX_op_qemu_st: - return C_O0_I2(r, r); - case INDEX_op_qemu_st2: - return C_O0_I3(o, m, r); - case INDEX_op_add_vec: case INDEX_op_sub_vec: case INDEX_op_mul_vec: --=20 2.43.0