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Iglesias" , Anton Johansson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 5/7] target/microblaze: Have compute_ldst_addr_type[ab] return TCG_i32 Date: Wed, 15 Oct 2025 19:57:15 +0200 Message-ID: <20251015175717.93945-6-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251015175717.93945-1-philmd@linaro.org> References: <20251015175717.93945-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760551147908154100 Both compute_ldst_addr_typea() and compute_ldst_addr_typeb() bodies use a TCG_i32, so return the same type. Suggested-by: Anton Johansson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/microblaze/translate.c | 48 +++++++++++++++++------------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index bc38ff0af92..002f921e00f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -604,7 +604,7 @@ static bool trans_wdic(DisasContext *dc, arg_wdic *a) DO_TYPEA(xor, false, tcg_gen_xor_i32) DO_TYPEBI(xori, false, tcg_gen_xori_i32) =20 -static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb) +static TCG_i32 compute_ldst_addr_typea(DisasContext *dc, int ra, int rb) { TCG_i32 ret; =20 @@ -626,7 +626,7 @@ static TCGv compute_ldst_addr_typea(DisasContext *dc, i= nt ra, int rb) return ret; } =20 -static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm) +static TCG_i32 compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm) { TCG_i32 ret; =20 @@ -750,13 +750,13 @@ static bool do_load(DisasContext *dc, int rd, TCGv ad= dr, MemOp mop, =20 static bool trans_lbu(DisasContext *dc, arg_typea *arg) { - TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCG_i32 addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, false); } =20 static bool trans_lbur(DisasContext *dc, arg_typea *arg) { - TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCG_i32 addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, true); } =20 @@ -776,19 +776,19 @@ static bool trans_lbuea(DisasContext *dc, arg_typea *= arg) =20 static bool trans_lbui(DisasContext *dc, arg_typeb *arg) { - TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + TCG_i32 addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); return do_load(dc, arg->rd, addr, MO_UB, dc->mem_index, false); } =20 static bool trans_lhu(DisasContext *dc, arg_typea *arg) { - TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCG_i32 addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } =20 static bool trans_lhur(DisasContext *dc, arg_typea *arg) { - TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCG_i32 addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, true); } =20 @@ -810,19 +810,19 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *= arg) =20 static bool trans_lhui(DisasContext *dc, arg_typeb *arg) { - TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + TCG_i32 addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } =20 static bool trans_lw(DisasContext *dc, arg_typea *arg) { - TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCG_i32 addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } =20 static bool trans_lwr(DisasContext *dc, arg_typea *arg) { - TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCG_i32 addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, true); } =20 @@ -844,16 +844,16 @@ static bool trans_lwea(DisasContext *dc, arg_typea *a= rg) =20 static bool trans_lwi(DisasContext *dc, arg_typeb *arg) { - TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + TCG_i32 addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } =20 static bool trans_lwx(DisasContext *dc, arg_typea *arg) { - TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCG_i32 addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); =20 /* lwx does not throw unaligned access errors, so force alignment */ - tcg_gen_andi_tl(addr, addr, ~3); + tcg_gen_andi_i32(addr, addr, ~3); =20 tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, mo_endian(dc) | MO_UL); @@ -910,13 +910,13 @@ static bool do_store(DisasContext *dc, int rd, TCGv a= ddr, MemOp mop, =20 static bool trans_sb(DisasContext *dc, arg_typea *arg) { - TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCG_i32 addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, false); } =20 static bool trans_sbr(DisasContext *dc, arg_typea *arg) { - TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCG_i32 addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, true); } =20 @@ -936,19 +936,19 @@ static bool trans_sbea(DisasContext *dc, arg_typea *a= rg) =20 static bool trans_sbi(DisasContext *dc, arg_typeb *arg) { - TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + TCG_i32 addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); return do_store(dc, arg->rd, addr, MO_UB, dc->mem_index, false); } =20 static bool trans_sh(DisasContext *dc, arg_typea *arg) { - TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCG_i32 addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } =20 static bool trans_shr(DisasContext *dc, arg_typea *arg) { - TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCG_i32 addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, true); } =20 @@ -970,19 +970,19 @@ static bool trans_shea(DisasContext *dc, arg_typea *a= rg) =20 static bool trans_shi(DisasContext *dc, arg_typeb *arg) { - TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + TCG_i32 addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false); } =20 static bool trans_sw(DisasContext *dc, arg_typea *arg) { - TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCG_i32 addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } =20 static bool trans_swr(DisasContext *dc, arg_typea *arg) { - TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCG_i32 addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, true); } =20 @@ -1004,19 +1004,19 @@ static bool trans_swea(DisasContext *dc, arg_typea = *arg) =20 static bool trans_swi(DisasContext *dc, arg_typeb *arg) { - TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); + TCG_i32 addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false); } =20 static bool trans_swx(DisasContext *dc, arg_typea *arg) { - TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); + TCG_i32 addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); TCGLabel *swx_done =3D gen_new_label(); TCGLabel *swx_fail =3D gen_new_label(); TCGv_i32 tval; =20 /* swx does not throw unaligned access errors, so force alignment */ - tcg_gen_andi_tl(addr, addr, ~3); + tcg_gen_andi_i32(addr, addr, ~3); =20 /* * Compare the address vs the one we used during lwx. --=20 2.51.0