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charset="utf-8" Add IgvmNativeVpContextX64 struct holding the register state (see igvm spec), and the qigvm_x86_load_context() function to load the register state. Wire up using two new functions: qigvm_x86_set_vp_context() is called from igvm file handling code and stores the boot processor context. qigvm_x86_bsp_reset() is called from i386 target cpu reset code and loads the context into the cpu registers. Signed-off-by: Gerd Hoffmann Reviewed-by: Stefano Garzarella --- include/system/igvm.h | 2 + target/i386/cpu.h | 3 + backends/igvm.c | 30 +++++----- stubs/igvm.c | 5 ++ target/i386/cpu.c | 4 ++ target/i386/igvm.c | 133 ++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 162 insertions(+), 15 deletions(-) diff --git a/include/system/igvm.h b/include/system/igvm.h index 3f72a40b8897..48ce20604259 100644 --- a/include/system/igvm.h +++ b/include/system/igvm.h @@ -23,5 +23,7 @@ int qigvm_process_file(IgvmCfg *igvm, ConfidentialGuestSu= pport *cgs, int qigvm_x86_get_mem_map_entry(int index, ConfidentialGuestMemoryMapEntry *entry, Error **errp); +int qigvm_x86_set_vp_context(void *data, int index, + Error **errp); =20 #endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ce948861a765..78d4b427c67a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2867,6 +2867,9 @@ void x86_cpu_dump_local_apic_state(CPUState *cs, int = flags); =20 #endif =20 +/* igvm.c */ +void qigvm_x86_bsp_reset(CPUX86State *env); + /* cpu.c */ bool cpu_is_bsp(X86CPU *cpu); =20 diff --git a/backends/igvm.c b/backends/igvm.c index e949c81abb9a..ee5ee74c7a66 100644 --- a/backends/igvm.c +++ b/backends/igvm.c @@ -432,18 +432,6 @@ static int qigvm_directive_vp_context(QIgvm *ctx, cons= t uint8_t *header_data, return 0; } =20 - /* - * A confidential guest support object must be provided for setting - * a VP context. - */ - if (!ctx->cgs) { - error_setg( - errp, - "A VP context is present in the IGVM file but is not supported= " - "by the current system."); - return -1; - } - data_handle =3D igvm_get_header_data(ctx->file, IGVM_HEADER_SECTION_DI= RECTIVE, ctx->current_header_index); if (data_handle < 0) { @@ -453,9 +441,21 @@ static int qigvm_directive_vp_context(QIgvm *ctx, cons= t uint8_t *header_data, } =20 data =3D (uint8_t *)igvm_get_buffer(ctx->file, data_handle); - result =3D ctx->cgsc->set_guest_state( - vp_context->gpa, data, igvm_get_buffer_size(ctx->file, data_handle= ), - CGS_PAGE_TYPE_VMSA, vp_context->vp_index, errp); + + if (ctx->cgs) { + result =3D ctx->cgsc->set_guest_state( + vp_context->gpa, data, igvm_get_buffer_size(ctx->file, data_ha= ndle), + CGS_PAGE_TYPE_VMSA, vp_context->vp_index, errp); + } else if (target_arch() =3D=3D SYS_EMU_TARGET_X86_64) { + result =3D qigvm_x86_set_vp_context(data, vp_context->vp_index, er= rp); + } else { + error_setg( + errp, + "A VP context is present in the IGVM file but is not supported= " + "by the current system."); + result =3D -1; + } + igvm_free_buffer(ctx->file, data_handle); if (result < 0) { return result; diff --git a/stubs/igvm.c b/stubs/igvm.c index c32058eb2a6e..17cd1e903e35 100644 --- a/stubs/igvm.c +++ b/stubs/igvm.c @@ -19,3 +19,8 @@ int qigvm_x86_get_mem_map_entry(int index, { return -1; } + +int qigvm_x86_set_vp_context(void *data, int index, Error **errp) +{ + return -1; +} diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 455caff6b230..8dd5ac8020c2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8770,6 +8770,10 @@ static void x86_cpu_reset_hold(Object *obj, ResetTyp= e type) =20 cs->halted =3D !cpu_is_bsp(cpu); =20 + if (cpu_is_bsp(cpu)) { + qigvm_x86_bsp_reset(env); + } + if (kvm_enabled()) { kvm_arch_reset_vcpu(cpu); } diff --git a/target/i386/igvm.c b/target/i386/igvm.c index 2ed6cd052c79..0921ec830508 100644 --- a/target/i386/igvm.c +++ b/target/i386/igvm.c @@ -11,9 +11,114 @@ =20 #include "qemu/osdep.h" =20 +#include "cpu.h" #include "hw/i386/e820_memory_layout.h" #include "system/igvm.h" =20 +struct IgvmNativeVpContextX64 { + uint64_t rax; + uint64_t rcx; + uint64_t rdx; + uint64_t rbx; + uint64_t rsp; + uint64_t rbp; + uint64_t rsi; + uint64_t rdi; + uint64_t r8; + uint64_t r9; + uint64_t r10; + uint64_t r11; + uint64_t r12; + uint64_t r13; + uint64_t r14; + uint64_t r15; + uint64_t rip; + uint64_t rflags; + uint64_t idtr_base; + uint16_t idtr_limit; + uint16_t reserved[2]; + uint16_t gdtr_limit; + uint64_t gdtr_base; + + uint16_t code_selector; + uint16_t code_attributes; + uint32_t code_base; + uint32_t code_limit; + + uint16_t data_selector; + uint16_t data_attributes; + uint32_t data_base; + uint32_t data_limit; + + uint64_t gs_base; + uint64_t cr0; + uint64_t cr3; + uint64_t cr4; + uint64_t efer; +}; + +#define FLAGS_TO_SEGCACHE(flags) \ + (((unsigned int)flags) << 8) + +static void qigvm_x86_load_context(struct IgvmNativeVpContextX64 *context,= CPUX86State *env) +{ + cpu_load_efer(env, context->efer); + cpu_x86_update_cr4(env, context->cr4); + cpu_x86_update_cr0(env, context->cr0); + cpu_x86_update_cr3(env, context->cr3); + + cpu_x86_load_seg_cache( + env, R_CS, context->code_selector, + context->code_base, context->code_limit, + FLAGS_TO_SEGCACHE(context->code_attributes)); + cpu_x86_load_seg_cache( + env, R_DS, context->data_selector, + context->data_base, context->data_limit, + FLAGS_TO_SEGCACHE(context->data_attributes)); + cpu_x86_load_seg_cache( + env, R_ES, context->data_selector, + context->data_base, context->data_limit, + FLAGS_TO_SEGCACHE(context->data_attributes)); + cpu_x86_load_seg_cache( + env, R_FS, context->data_selector, + context->data_base, context->data_limit, + FLAGS_TO_SEGCACHE(context->data_attributes)); + cpu_x86_load_seg_cache( + env, R_GS, context->data_selector, + context->data_base, context->data_limit, + FLAGS_TO_SEGCACHE(context->data_attributes)); + cpu_x86_load_seg_cache( + env, R_SS, context->data_selector, + context->data_base, context->data_limit, + FLAGS_TO_SEGCACHE(context->data_attributes)); + + env->gdt.base =3D context->gdtr_base; + env->gdt.limit =3D context->gdtr_limit; + env->idt.base =3D context->idtr_base; + env->idt.limit =3D context->idtr_limit; + + env->regs[R_EAX] =3D context->rax; + env->regs[R_ECX] =3D context->rcx; + env->regs[R_EDX] =3D context->rdx; + env->regs[R_EBX] =3D context->rbx; + env->regs[R_ESP] =3D context->rsp; + env->regs[R_EBP] =3D context->rbp; + env->regs[R_ESI] =3D context->rsi; + env->regs[R_EDI] =3D context->rdi; +#ifdef TARGET_X86_64 + env->regs[R_R8] =3D context->r8; + env->regs[R_R9] =3D context->r9; + env->regs[R_R10] =3D context->r10; + env->regs[R_R11] =3D context->r11; + env->regs[R_R12] =3D context->r12; + env->regs[R_R13] =3D context->r13; + env->regs[R_R14] =3D context->r14; + env->regs[R_R15] =3D context->r15; +#endif + env->eip =3D context->rip; + env->eflags =3D context->rflags; +} + /* * convert e820 table into igvm memory map */ @@ -44,3 +149,31 @@ int qigvm_x86_get_mem_map_entry(int index, } return 0; } + +/* + * set initial cpu context + */ +static struct IgvmNativeVpContextX64 *bsp_context; + +int qigvm_x86_set_vp_context(void *data, int index, Error **errp) +{ + if (index !=3D 0) { + error_setg(errp, "context can be set for BSP only"); + return -1; + } + + if (bsp_context =3D=3D NULL) { + bsp_context =3D g_new0(struct IgvmNativeVpContextX64, 1); + } + memcpy(bsp_context, data, sizeof(struct IgvmNativeVpContextX64)); + return 0; +} + +void qigvm_x86_bsp_reset(CPUX86State *env) +{ + if (bsp_context =3D=3D NULL) { + return; + } + + qigvm_x86_load_context(bsp_context, env); +} --=20 2.51.0