From nobody Fri Nov 14 19:45:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1760509610; cv=none; d=zohomail.com; s=zohoarc; b=f7VVo3epTWmEoijqufcy7c692GbLWkXq2xTVOY9pey9fjsMinUwG3FB5ULLhdQ3WH+MuljD0enLlmYo0Qg8/wRRCtqy/xVtY2/KVwJ79Myx+kjaCAbun1UJFTzL4YNcLGMxgxOTgibCwUiGefGqmyza9B6CyX0HjNVoYKt10agE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760509610; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=mz+e64WHC5gUWgyIFzpp8vaZl5WPmRTlZLex7IPYS8k=; b=LuD0A/dqsWFww7qiukND8HA+2Grdcv/jXPNVST0mYFkhEvGzc8G730a+kADDo/m2fDzEKFJzPRZQyh4SNPF1iEp21s9mBBZoSkk8m5YSKeNW+50ibVCWCCZJRLI4CL29J4nfiwkm9Jhzzye71YEcw4/s7xuOqiHQvDSfOu13HBE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760509610096364.0308205686938; Tue, 14 Oct 2025 23:26:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v8uus-0001An-JV; Wed, 15 Oct 2025 02:23:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v8uuj-00014H-DG; Wed, 15 Oct 2025 02:23:12 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v8uuf-0002xW-Oi; Wed, 15 Oct 2025 02:23:09 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 15 Oct 2025 14:22:12 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 15 Oct 2025 14:22:12 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 05/12] hw/arm/ast27x0: Share single SCU instance across PSP, SSP, and TSP Date: Wed, 15 Oct 2025 14:22:00 +0800 Message-ID: <20251015062210.3128710-6-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251015062210.3128710-1-jamin_lin@aspeedtech.com> References: <20251015062210.3128710-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1760509611632154100 AST2700 has a single SCU hardware block, memory-mapped at 0x12C02000=E2=80=930x12C03FFF from the perspective of the main CA35 process= or (PSP). The SSP and TSP coprocessors access this same SCU block at different addresses: 0x72C02000=E2=80=930x72C03FFF. Previously, each subsystem (PSP, SSP, and TSP) instantiated its own SCU device, resulting in three independent SCU instances in the QEMU model. In real hardware, however, only a single SCU exists and is shared among all processors. This commit reworks the SCU model to correctly reflect the hardware behavior by allowing SSP and TSP to reference the PSP=E2=80=99s SCU instanc= e. The following changes are introduced: - Add a scu property to AspeedCoprocessorState for linking the coprocessor to the PSP=E2=80=99s SCU instance. - Replace per-coprocessor SCU instantiation with a shared SCU link. - Add "MemoryRegion scu_alias" to model address remapping for SSP and TSP. - Create SCU alias regions in both SSP and TSP coprocessors and map them at 0x72C02000 to mirror the PSP=E2=80=99s SCU registers. - Ensure the SCU device in PSP is realized before SSP/TSP alias setup. With this change, PSP, SSP, and TSP now share a consistent SCU state, matching the single-SCU hardware design of AST2700. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_coprocessor.h | 4 ++-- hw/arm/aspeed_ast27x0-fc.c | 4 ++++ hw/arm/aspeed_ast27x0-ssp.c | 13 +++++-------- hw/arm/aspeed_ast27x0-tsp.c | 13 +++++-------- hw/arm/aspeed_coprocessor_common.c | 2 ++ 5 files changed, 18 insertions(+), 18 deletions(-) diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h index d9a5f517d7..c1f2c549c3 100644 --- a/include/hw/arm/aspeed_coprocessor.h +++ b/include/hw/arm/aspeed_coprocessor.h @@ -19,9 +19,10 @@ struct AspeedCoprocessorState { MemoryRegion sdram; MemoryRegion *sram; MemoryRegion sram_alias; + MemoryRegion scu_alias; Clock *sysclk; =20 - AspeedSCUState scu; + AspeedSCUState *scu; AspeedSCUState scuio; AspeedTimerCtrlState timerctrl; SerialMM uart[ASPEED_UARTS_NUM]; @@ -36,7 +37,6 @@ struct AspeedCoprocessorClass { =20 /** valid_cpu_types: NULL terminated array of a single CPU type. */ const char * const *valid_cpu_types; - uint32_t silicon_rev; const hwaddr *memmap; const int *irqmap; int uarts_base; diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index dfac7d1e17..ba43a46207 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -138,6 +138,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, E= rror **errp) sc->uarts_num, serial_hd(1)); object_property_set_link(OBJECT(&s->ssp), "sram", OBJECT(&psp->sram), &error_abort); + object_property_set_link(OBJECT(&s->ssp), "scu", + OBJECT(&psp->scu), &error_abort); if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) { return false; } @@ -170,6 +172,8 @@ static bool ast2700fc_tsp_init(MachineState *machine, E= rror **errp) sc->uarts_num, serial_hd(2)); object_property_set_link(OBJECT(&s->tsp), "sram", OBJECT(&psp->sram), &error_abort); + object_property_set_link(OBJECT(&s->tsp), "scu", + OBJECT(&psp->scu), &error_abort); if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) { return false; } diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 66c4ef6d1b..577a3379c6 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -137,9 +137,7 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj) int i; =20 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); - object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); - qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev); =20 for (i =3D 0; i < sc->uarts_num; i++) { object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M= M); @@ -203,11 +201,11 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState= *dev_soc, Error **errp) &s->sram_alias); =20 /* SCU */ - if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { - return; - } - aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0, - sc->memmap[ASPEED_DEV_SCU]); + memory_region_init_alias(&s->scu_alias, OBJECT(s), "scu.alias", + &s->scu->iomem, 0, + memory_region_size(&s->scu->iomem)); + memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU], + &s->scu_alias); =20 /* INTC */ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { @@ -285,7 +283,6 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClas= s *klass, dc->realize =3D aspeed_soc_ast27x0ssp_realize; =20 sc->valid_cpu_types =3D valid_cpu_types; - sc->silicon_rev =3D AST2700_A1_SILICON_REV; sc->uarts_num =3D 13; sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast27x0ssp_irqmap; diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 56b68adf54..a7c141678f 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -137,9 +137,7 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj) int i; =20 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); - object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); - qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev); =20 for (i =3D 0; i < sc->uarts_num; i++) { object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M= M); @@ -203,11 +201,11 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState= *dev_soc, Error **errp) &s->sram_alias); =20 /* SCU */ - if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { - return; - } - aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0, - sc->memmap[ASPEED_DEV_SCU]); + memory_region_init_alias(&s->scu_alias, OBJECT(s), "scu.alias", + &s->scu->iomem, 0, + memory_region_size(&s->scu->iomem)); + memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU], + &s->scu_alias); =20 /* INTC */ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { @@ -285,7 +283,6 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClas= s *klass, dc->realize =3D aspeed_soc_ast27x0tsp_realize; =20 sc->valid_cpu_types =3D valid_cpu_types; - sc->silicon_rev =3D AST2700_A1_SILICON_REV; sc->uarts_num =3D 13; sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast27x0tsp_irqmap; diff --git a/hw/arm/aspeed_coprocessor_common.c b/hw/arm/aspeed_coprocessor= _common.c index 8322ad5eb5..14e26bbe23 100644 --- a/hw/arm/aspeed_coprocessor_common.c +++ b/hw/arm/aspeed_coprocessor_common.c @@ -27,6 +27,8 @@ static const Property aspeed_coprocessor_properties[] =3D= { TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_LINK("sram", AspeedCoprocessorState, sram, TYPE_MEMORY_REG= ION, MemoryRegion *), + DEFINE_PROP_LINK("scu", AspeedCoprocessorState, scu, TYPE_ASPEED_SCU, + AspeedSCUState *), }; =20 static void aspeed_coprocessor_class_init(ObjectClass *oc, const void *dat= a) --=20 2.43.0