From nobody Fri Nov 14 19:45:35 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1760509486; cv=none; d=zohomail.com; s=zohoarc; b=J0T6uHPshIbYejSNeIlIdsgxK+Zccf6xuoaYrHt0KSx9aGbBpIo1bVcPw16rnBhtORFAudb9hRCSaCTqRotPFRKOHkp3O4VCUlowRMnXcJlLB1xgoaBTHevU+HNOnJY9Pi8tO4bE73FeOnQuOvKQGSjHRe2pJ4iZXlNgZXOvFT8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760509486; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=kJfgW/S0zJ6n56vzF5fPcI1kj7IrGmB21JttGWrtKNM=; b=EroQh9+KItrRsTNKUVADyTM8NcdKJZHq7ccNzgZWbH0axkA1KQ3ffHR02vPQtXZBFL+C3piRgT8upFWAX6GmHNkN8HQM3NpxKxQ7ax094Xzp2VgJObg6p9WmiwTRE+zLtORe9cDx8N3fdAUn/mOKiI9/0T4+vwaY7sh7xZLYj/4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17605094868771010.59141090597; Tue, 14 Oct 2025 23:24:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v8uuY-0000xp-09; Wed, 15 Oct 2025 02:22:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v8uuV-0000wo-P5; Wed, 15 Oct 2025 02:22:55 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v8uuT-0002xW-H1; Wed, 15 Oct 2025 02:22:55 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 15 Oct 2025 14:22:11 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 15 Oct 2025 14:22:11 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 03/12] hw/arm/ast27x0: Add SRAM link and alias mapping for SSP coprocessor Date: Wed, 15 Oct 2025 14:21:58 +0800 Message-ID: <20251015062210.3128710-4-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251015062210.3128710-1-jamin_lin@aspeedtech.com> References: <20251015062210.3128710-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1760509489893158500 AST2700 has a 128KB SRAM, physically mapped at 0x10000000=E2=80=930x1001FFF= F for the PSP (CA35) processor. The SSP coprocessor shares this same SRAM but accesses it through a different address window at 0x70000000=E2=80=930x7001= FFFF. To model this shared-memory behavior in QEMU, this commit introduces a linked SRAM property and alias mapping between the PSP and SSP subsystems. Changes include: - Add a "MemoryRegion *sram" link and "MemoryRegion sram_alias" to AspeedCoprocessorState. - Register the new "sram" property in aspeed_coprocessor_common.c. - In aspeed_ast27x0-fc.c, connect the SSP coprocessor=E2=80=99s "sram" link= to the PSP=E2=80=99s SRAM region. - In aspeed_ast27x0-ssp.c, create an alias mapping for SRAM at 0x70000000 =E2=80=93 0x7001FFFF in the SSP=E2=80=99s memory map. This ensures that the SSP can correctly access the shared SRAM contents through its own address space while maintaining a consistent physical backing region. It also guarantees that the SRAM is realized before the SSP device, ensuring successful alias setup. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_coprocessor.h | 3 ++- hw/arm/aspeed_ast27x0-fc.c | 4 ++++ hw/arm/aspeed_ast27x0-ssp.c | 7 +++++++ hw/arm/aspeed_coprocessor_common.c | 2 ++ 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h index 0c7168a89c..d9a5f517d7 100644 --- a/include/hw/arm/aspeed_coprocessor.h +++ b/include/hw/arm/aspeed_coprocessor.h @@ -17,7 +17,8 @@ struct AspeedCoprocessorState { =20 MemoryRegion *memory; MemoryRegion sdram; - MemoryRegion sram; + MemoryRegion *sram; + MemoryRegion sram_alias; Clock *sysclk; =20 AspeedSCUState scu; diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index a61ecff390..25e668a648 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -118,6 +118,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, E= rror **errp) AspeedCoprocessorState *soc; AspeedCoprocessorClass *sc; Ast2700FCState *s =3D AST2700A1FC(machine); + AspeedSoCState *psp =3D ASPEED_SOC(&s->ca35); + s->ssp_sysclk =3D clock_new(OBJECT(s), "SSP_SYSCLK"); clock_set_hz(s->ssp_sysclk, 200000000ULL); =20 @@ -134,6 +136,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, E= rror **errp) sc =3D ASPEED_COPROCESSOR_GET_CLASS(soc); aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART4, sc->uarts_base, sc->uarts_num, serial_hd(1)); + object_property_set_link(OBJECT(&s->ssp), "sram", + OBJECT(&psp->sram), &error_abort); if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) { return false; } diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 9f3a1933a0..66c4ef6d1b 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -20,6 +20,7 @@ =20 static const hwaddr aspeed_soc_ast27x0ssp_memmap[] =3D { [ASPEED_DEV_SDRAM] =3D 0x00000000, + [ASPEED_DEV_SRAM] =3D 0x70000000, [ASPEED_DEV_INTC] =3D 0x72100000, [ASPEED_DEV_SCU] =3D 0x72C02000, [ASPEED_DEV_SCUIO] =3D 0x74C02000, @@ -195,6 +196,12 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState = *dev_soc, Error **errp) sc->memmap[ASPEED_DEV_SDRAM], &s->sdram); =20 + /* SRAM */ + memory_region_init_alias(&s->sram_alias, OBJECT(s), "sram.alias", + s->sram, 0, memory_region_size(s->sram)); + memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM], + &s->sram_alias); + /* SCU */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; diff --git a/hw/arm/aspeed_coprocessor_common.c b/hw/arm/aspeed_coprocessor= _common.c index 8a94b44f07..8322ad5eb5 100644 --- a/hw/arm/aspeed_coprocessor_common.c +++ b/hw/arm/aspeed_coprocessor_common.c @@ -25,6 +25,8 @@ static void aspeed_coprocessor_realize(DeviceState *dev, = Error **errp) static const Property aspeed_coprocessor_properties[] =3D { DEFINE_PROP_LINK("memory", AspeedCoprocessorState, memory, TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_LINK("sram", AspeedCoprocessorState, sram, TYPE_MEMORY_REG= ION, + MemoryRegion *), }; =20 static void aspeed_coprocessor_class_init(ObjectClass *oc, const void *dat= a) --=20 2.43.0