From nobody Thu Oct 16 04:52:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1760474144; cv=none; d=zohomail.com; s=zohoarc; b=K1t8n7022RdJ/kIdxVZbhXLepcdNupEONbodQ+xZmJY0LmlQCSOvEiTQhWtNRzt4J3hEZK71pkzDr+rnRJcaFWez9pyTebxOPbMVHUlaUT1JzfDFFAWmlLSWdCnKPQPy8mKQPeqYu/+3hbqnTbR032jb97T0wvpNRmJdOhym+Go= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760474144; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=lC2jGNrhLAvyuYMCT1r/zgn1IyRpsTkm9KLh05/eFiw=; b=lOr/+udNZekePbY9bKZArrllXRPAYbeN5ZW4obyaGSpzlm/h3oYPlCei76kwbzDLg4MM6k+4ivBUxDNX77VeJKqAIHFVNPhbUsp8f+izNw6ZVnhoaC/zbReuRMVV/k595iTZS2Wsha3FzFXO6bjwwUucOg2CCvSlRj0vAl41WVk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760474144127146.7338707728153; Tue, 14 Oct 2025 13:35:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v8lis-0001OG-3w; Tue, 14 Oct 2025 16:34:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v8liq-0001Na-4i for qemu-devel@nongnu.org; Tue, 14 Oct 2025 16:34:16 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v8lih-0000YK-EU for qemu-devel@nongnu.org; Tue, 14 Oct 2025 16:34:15 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=lC2jGNrhLAvyuYMCT1r/zgn1IyRpsTkm9KLh05/eFiw=; b=DbE8WwWeOM3C9o3 /idK/b1IygXZxA42FV7O/1z37f2Nt1fJkncScbftMaA9FTkYNUctxo4pJ9Vc8V0rZsuU+AsKDjskO VtoS/Htni1f6N+eoptwxNVkh9mwXnZm2tBp3QryezPpHfTJY82kcaa766gW1sz9yGHghxsoiqsUKn 8w=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com Subject: [PATCH v3 33/34] target/riscv: Introduce externally facing CSR access functions Date: Tue, 14 Oct 2025 22:35:10 +0200 Message-ID: <20251014203512.26282-34-anjo@rev.ng> In-Reply-To: <20251014203512.26282-1-anjo@rev.ng> References: <20251014203512.26282-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1760474146274158500 Content-Type: text/plain; charset="utf-8" Convert riscv_csr_[read|write]() into target_ulong angnostic CSR access functions that can be safely used from outside of target/ without knowledge of the target register size. Replace the 4 existing CSR accesses in hw/ and linux-user/. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier --- target/riscv/cpu.h | 7 ++++++- target/riscv/csr.h | 13 ------------- hw/riscv/riscv_hart.c | 7 +++---- linux-user/riscv/signal.c | 5 +++-- target/riscv/csr.c | 17 +++++++++++++++++ 5 files changed, 29 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a83930a85f..4b039ff92b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -858,7 +858,12 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env); uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm); =20 -#include "csr.h" +/* + * Externally facing CSR access functions, wrappers around riscv_csr*(). + */ + +int riscv_csr_write_i64(CPURISCVState *env, int csrno, uint64_t val); +int riscv_csr_read_i64(CPURISCVState *env, int csrn, uint64_t *res); =20 /* * The event id are encoded based on the encoding specified in the diff --git a/target/riscv/csr.h b/target/riscv/csr.h index 5b92f6fecc..552e6c5de5 100644 --- a/target/riscv/csr.h +++ b/target/riscv/csr.h @@ -23,19 +23,6 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int= csrno, target_ulong new_value, target_ulong write_mask); =20 -static inline void riscv_csr_write(CPURISCVState *env, int csrno, - target_ulong val) -{ - riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS= ), 0); -} - -static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) -{ - target_ulong val =3D 0; - riscv_csrr(env, csrno, &val); - return val; -} - typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 7f2676008c..c7e98a4308 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -67,12 +67,11 @@ static void csr_call(char *cmd, uint64_t cpu_num, int c= srno, uint64_t *val) RISCVCPU *cpu =3D RISCV_CPU(cpu_by_arch_id(cpu_num)); CPURISCVState *env =3D &cpu->env; =20 - int ret =3D RISCV_EXCP_NONE; + RISCVException ret =3D RISCV_EXCP_NONE; if (strcmp(cmd, "get_csr") =3D=3D 0) { - ret =3D riscv_csrr(env, csrno, (target_ulong *)val); + ret =3D riscv_csr_read_i64(env, csrno, val); } else if (strcmp(cmd, "set_csr") =3D=3D 0) { - ret =3D riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, - MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0); + ret =3D riscv_csr_write_i64(env, csrno, *val); } =20 g_assert(ret =3D=3D RISCV_EXCP_NONE); diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c index 358fa1d82d..9d5ba300e4 100644 --- a/linux-user/riscv/signal.c +++ b/linux-user/riscv/signal.c @@ -90,7 +90,8 @@ static void setup_sigcontext(struct target_sigcontext *sc= , CPURISCVState *env) __put_user(env->fpr[i], &sc->fpr[i]); } =20 - uint32_t fcsr =3D riscv_csr_read(env, CSR_FCSR); + uint64_t fcsr; + riscv_csr_read_i64(env, CSR_FCSR, &fcsr); __put_user(fcsr, &sc->fcsr); } =20 @@ -159,7 +160,7 @@ static void restore_sigcontext(CPURISCVState *env, stru= ct target_sigcontext *sc) =20 uint32_t fcsr; __get_user(fcsr, &sc->fcsr); - riscv_csr_write(env, CSR_FCSR, fcsr); + riscv_csr_write_i64(env, CSR_FCSR, fcsr); } =20 static void restore_ucontext(CPURISCVState *env, struct target_ucontext *u= c) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 2da27441f8..2983d5bfe4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5658,6 +5658,23 @@ RISCVException riscv_csrrw(CPURISCVState *env, int c= srno, return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask, = ra); } =20 +int riscv_csr_write_i64(CPURISCVState *env, int csrno, uint64_t val) +{ + RISCVException ret; + ret =3D riscv_csrrw(env, csrno, NULL, val, + MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0); + return ret; +} + +int riscv_csr_read_i64(CPURISCVState *env, int csrno, uint64_t *res) +{ + RISCVException ret; + target_ulong val =3D 0; + ret =3D riscv_csrr(env, csrno, &val); + *res =3D val; + return ret; +} + static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, Int128 *ret_value, Int128 new_value, --=20 2.51.0