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Tue, 14 Oct 2025 13:07:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 28/37] target/arm: Implement TLBIP RVAE1, RVAAE1, RVALE1, RVAALE1 Date: Tue, 14 Oct 2025 13:07:09 -0700 Message-ID: <20251014200718.422022-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251014200718.422022-1-richard.henderson@linaro.org> References: <20251014200718.422022-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760472717963154100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/tcg/tlb-insns.c | 93 ++++++++++++++++++++++++++++++-------- 1 file changed, 74 insertions(+), 19 deletions(-) diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c index f7510a1208..daadba7bfc 100644 --- a/target/arm/tcg/tlb-insns.c +++ b/target/arm/tcg/tlb-insns.c @@ -918,16 +918,43 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env= , ARMMMUIdx mmuidx, return ret; } =20 -static void do_rvae_write(CPUARMState *env, uint64_t value, - int idxmap, bool synced) +static TLBIRange tlbi_aa64_get_range128(CPUARMState *env, ARMMMUIdx mmuidx, + uint64_t vallo, uint64_t valhi) { - ARMMMUIdx one_idx =3D ARM_MMU_IDX_A | ctz32(idxmap); - TLBIRange range; - int bits; + uint64_t uaddr =3D extract64(valhi << 12, 0, 56); + ARMVAParameters param =3D aa64_va_parameters(env, uaddr, mmuidx, true,= false); + TLBIRange ret =3D { }; + unsigned page_size_granule =3D extract64(vallo, 46, 2); + ARMGranuleSize gran =3D tlbi_range_tg_to_gran_size(page_size_granule); =20 - range =3D tlbi_aa64_get_range(env, one_idx, value); - bits =3D tlbbits_for_regime(env, one_idx, range.base); + /* The granule encoded in value must match the granule in use. */ + if (gran !=3D param.gran) { + qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\= n", + page_size_granule); + } else { + unsigned page_shift =3D arm_granule_bits(gran); + unsigned num =3D extract64(vallo, 39, 5); + unsigned scale =3D extract64(vallo, 44, 2); + unsigned exponent =3D (5 * scale) + 1; + uint64_t max =3D 1ull << 56; =20 + ret.length =3D (num + 1) << (exponent + page_shift); + ret.length =3D MIN(ret.length, max - uaddr); + /* + * Note that TLBIPRange ignores the high bits, because the HW TLB + * does not use it. But the qemu softmmu tlb does, so sign-extend + * if and only if the regime has two ranges. + */ + ret.base =3D uaddr | (-(uint64_t)param.select << 56); + } + + return ret; +} + +static void do_flush_range(CPUARMState *env, ARMMMUIdx one_idx, int idxmap, + bool synced, TLBIRange range) +{ + int bits =3D tlbbits_for_regime(env, one_idx, range.base); if (synced) { tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env), range.base, @@ -940,6 +967,22 @@ static void do_rvae_write(CPUARMState *env, uint64_t v= alue, } } =20 +static void do_rvae_write(CPUARMState *env, uint64_t value, + int idxmap, bool synced) +{ + ARMMMUIdx one_idx =3D ARM_MMU_IDX_A | ctz32(idxmap); + do_flush_range(env, one_idx, idxmap, synced, + tlbi_aa64_get_range(env, one_idx, value)); +} + +static void do_rvae_write128(CPUARMState *env, uint64_t vallo, uint64_t va= lhi, + int idxmap, bool synced) +{ + ARMMMUIdx one_idx =3D ARM_MMU_IDX_A | ctz32(idxmap); + do_flush_range(env, one_idx, idxmap, synced, + tlbi_aa64_get_range128(env, one_idx, vallo, valhi)); +} + static void tlbi_aa64_rvae1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) @@ -955,6 +998,14 @@ static void tlbi_aa64_rvae1_write(CPUARMState *env, tlb_force_broadcast(env)); } =20 +static void tlbi_aa64_rvae1_write128(CPUARMState *env, + const ARMCPRegInfo *ri, + uint64_t vallo, uint64_t valhi) +{ + do_rvae_write128(env, vallo, valhi, vae1_tlbmask(env), + tlb_force_broadcast(env)); +} + static void tlbi_aa64_rvae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) @@ -1095,28 +1146,32 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, - .access =3D PL1_W, .accessfn =3D access_ttlb, - .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access =3D PL1_W, .accessfn =3D access_ttlb, .access128fn =3D acces= s_ttlb, + .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT, .fgt =3D FGT_TLBIRVAE1, - .writefn =3D tlbi_aa64_rvae1_write }, + .writefn =3D tlbi_aa64_rvae1_write, + .write128fn =3D tlbi_aa64_rvae1_write128 }, { .name =3D "TLBI_RVAAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 3, - .access =3D PL1_W, .accessfn =3D access_ttlb, - .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access =3D PL1_W, .accessfn =3D access_ttlb, .access128fn =3D acces= s_ttlb, + .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT, .fgt =3D FGT_TLBIRVAAE1, - .writefn =3D tlbi_aa64_rvae1_write }, + .writefn =3D tlbi_aa64_rvae1_write, + .write128fn =3D tlbi_aa64_rvae1_write128 }, { .name =3D "TLBI_RVALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, - .access =3D PL1_W, .accessfn =3D access_ttlb, - .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access =3D PL1_W, .accessfn =3D access_ttlb, .access128fn =3D acces= s_ttlb, + .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT, .fgt =3D FGT_TLBIRVALE1, - .writefn =3D tlbi_aa64_rvae1_write }, + .writefn =3D tlbi_aa64_rvae1_write, + .write128fn =3D tlbi_aa64_rvae1_write128 }, { .name =3D "TLBI_RVAALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 7, - .access =3D PL1_W, .accessfn =3D access_ttlb, - .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, + .access =3D PL1_W, .accessfn =3D access_ttlb, .access128fn =3D acces= s_ttlb, + .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT, .fgt =3D FGT_TLBIRVAALE1, - .writefn =3D tlbi_aa64_rvae1_write }, + .writefn =3D tlbi_aa64_rvae1_write, + .write128fn =3D tlbi_aa64_rvae1_write128 }, { .name =3D "TLBI_RIPAS2E1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 2, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS, --=20 2.43.0