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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 1 + target/arm/helper.c | 30 +++++++++++++++++++++--------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index f539bbe58e..a65386aaed 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1391,6 +1391,7 @@ typedef struct ARMVAParameters { bool hd : 1; ARMGranuleSize gran : 2; bool pie : 1; + bool aie : 1; } ARMVAParameters; =20 /** diff --git a/target/arm/helper.c b/target/arm/helper.c index e4d1651440..8c0b8889db 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6098,6 +6098,9 @@ static void tcr2_el1_write(CPUARMState *env, const AR= MCPRegInfo *ri, if (cpu_isar_feature(aa64_s1pie, cpu)) { valid_mask |=3D TCR2_PIE; } + if (cpu_isar_feature(aa64_aie, cpu)) { + valid_mask |=3D TCR2_AIE; + } value &=3D valid_mask; raw_write(env, ri, value); } @@ -6111,7 +6114,10 @@ static void tcr2_el2_write(CPUARMState *env, const A= RMCPRegInfo *ri, if (cpu_isar_feature(aa64_s1pie, cpu)) { valid_mask |=3D TCR2_PIE; } - if (cpu_isar_feature(aa64_mec, env_archcpu(env))) { + if (cpu_isar_feature(aa64_aie, cpu)) { + valid_mask |=3D TCR2_AIE; + } + if (cpu_isar_feature(aa64_mec, cpu)) { valid_mask |=3D TCR2_AMEC0 | TCR2_AMEC1; } value &=3D valid_mask; @@ -9666,6 +9672,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, = uint64_t va, { uint64_t tcr =3D regime_tcr(env, mmu_idx); bool epd, hpd, tsz_oob, ds, ha, hd, pie =3D false; + bool aie =3D false; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; ARMGranuleSize gran; ARMCPU *cpu =3D env_archcpu(env); @@ -9688,10 +9695,12 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, if (r_el =3D=3D 3) { pie =3D (extract64(tcr, 35, 1) && cpu_isar_feature(aa64_s1pie, cpu)); - } else { - pie =3D ((env->cp15.tcr2_el[2] & TCR2_PIE) - && (!arm_feature(env, ARM_FEATURE_EL3) - || (env->cp15.scr_el3 & SCR_TCR2EN))); + aie =3D (extract64(tcr, 37, 1) + && cpu_isar_feature(aa64_aie, cpu)); + } else if (!arm_feature(env, ARM_FEATURE_EL3) + || (env->cp15.scr_el3 & SCR_TCR2EN)) { + pie =3D env->cp15.tcr2_el[2] & TCR2_PIE; + aie =3D env->cp15.tcr2_el[2] & TCR2_AIE; } } epd =3D false; @@ -9733,10 +9742,12 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, epd =3D true; } =20 - pie =3D ((env->cp15.tcr2_el[r_el] & TCR2_PIE) - && (!arm_feature(env, ARM_FEATURE_EL3) - || (env->cp15.scr_el3 & SCR_TCR2EN)) - && (r_el =3D=3D 2 || (arm_hcrx_el2_eff(env) & HCRX_TCR2EN))= ); + if ((!arm_feature(env, ARM_FEATURE_EL3) + || (env->cp15.scr_el3 & SCR_TCR2EN)) + && (r_el =3D=3D 2 || (arm_hcrx_el2_eff(env) & HCRX_TCR2EN))) { + pie =3D env->cp15.tcr2_el[r_el] & TCR2_PIE; + aie =3D env->cp15.tcr2_el[r_el] & TCR2_AIE; + } } hpd |=3D pie; =20 @@ -9818,6 +9829,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, = uint64_t va, .hd =3D ha && hd, .gran =3D gran, .pie =3D pie, + .aie =3D aie, }; } =20 --=20 2.43.0