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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359520; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dFF38vbJCcqoZ0VZSxZGGvoYn4TrbGzQbFCWQwTPafY=; b=bW/xyD+cshS4u+DXB89x3ftvYh/uryic8RCG/wGU7VrwKQW2w2wr4fcKdj3XQa4RCVU7Uz oBU+pA5Ej5yLNUrwjKzIeUJBdSEyJ9xsOMQLVa6eJUnMlPrpXBc9jgGlp6SQrLLJuyORcD iKm54B41/PGmg4xo3KBLYWPAjoD+3ao= X-MC-Unique: lfSNv7ogMjSCSs_8G8Yxmw-1 X-Mimecast-MFC-AGG-ID: lfSNv7ogMjSCSs_8G8Yxmw_1760359514 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 25/29] hw/arm/aspeed_ast27x0-ssp: Change to use Aspeed27x0CoprocessorState Date: Mon, 13 Oct 2025 14:44:16 +0200 Message-ID: <20251013124421.71977-26-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359942988154100 From: Jamin Lin Refactor the AST27x0 SSP implementation to use the unified Aspeed27x0CoprocessorState structure shared between SSP and TSP. Previously, SSP and TSP each defined separate state structures (Aspeed27x0SSPSoCState and Aspeed27x0TSPSoCState), which contained identical members and caused unnecessary code duplication. This change removes Aspeed27x0SSPSoCState and replaces it with Aspeed27x0CoprocessorState, consolidating shared coprocessor state fields into a single definition in aspeed_coprocessor.h. This refactor unifies SSP and TSP under the same coprocessor state type, improving code maintainability and consistency across Aspeed coprocessor implementations. No functional change. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-13-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_coprocessor.h | 4 ++-- hw/arm/aspeed_ast27x0-fc.c | 2 +- hw/arm/aspeed_ast27x0-ssp.c | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h index f09c2ed267b2..d799726635df 100644 --- a/include/hw/arm/aspeed_coprocessor.h +++ b/include/hw/arm/aspeed_coprocessor.h @@ -41,7 +41,7 @@ struct AspeedCoprocessorClass { int uarts_num; }; =20 -struct Aspeed27x0SSPSoCState { +struct Aspeed27x0CoprocessorState { AspeedCoprocessorState parent; AspeedINTCState intc[2]; UnimplementedDeviceState ipc[2]; @@ -51,7 +51,7 @@ struct Aspeed27x0SSPSoCState { }; =20 #define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc" -OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC) +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0CoprocessorState, ASPEED27X0SSP_SOC) =20 struct Aspeed27x0TSPSoCState { AspeedCoprocessorState parent; diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index b34cd54e4e7f..cd09a2dcf0b9 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -42,7 +42,7 @@ struct Ast2700FCState { Clock *tsp_sysclk; =20 Aspeed27x0SoCState ca35; - Aspeed27x0SSPSoCState ssp; + Aspeed27x0CoprocessorState ssp; Aspeed27x0TSPSoCState tsp; =20 bool mmio_exec; diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 1ebf06299ebe..f8319c95fd41 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -108,7 +108,7 @@ static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = =3D { static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedCoprocessorState *s, int dev) { - Aspeed27x0SSPSoCState *a =3D ASPEED27X0SSP_SOC(s); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0SSP_SOC(s); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); =20 int or_idx; @@ -130,7 +130,7 @@ static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedCop= rocessorState *s, =20 static void aspeed_soc_ast27x0ssp_init(Object *obj) { - Aspeed27x0SSPSoCState *a =3D ASPEED27X0SSP_SOC(obj); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0SSP_SOC(obj); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(obj); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); int i; @@ -161,7 +161,7 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj) =20 static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **er= rp) { - Aspeed27x0SSPSoCState *a =3D ASPEED27X0SSP_SOC(dev_soc); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0SSP_SOC(dev_soc); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(dev_soc); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); DeviceState *armv7m; @@ -288,7 +288,7 @@ static const TypeInfo aspeed_soc_ast27x0ssp_types[] =3D= { { .name =3D TYPE_ASPEED27X0SSP_SOC, .parent =3D TYPE_ASPEED_COPROCESSOR, - .instance_size =3D sizeof(Aspeed27x0SSPSoCState), + .instance_size =3D sizeof(Aspeed27x0CoprocessorState), .instance_init =3D aspeed_soc_ast27x0ssp_init, .class_init =3D aspeed_soc_ast27x0ssp_class_init, }, --=20 2.51.0