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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359470; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=o9XJQoWj0w1litKRtm7b6WTU9qbMY5CqhuJH/7tfqOI=; b=iumP59N8pxWcQZJHBZ1cZWoWrwTPQ2UmfV68aaHlhFmqpdaMy07vpQkf30088Rp+dWnyqC c7hd0v6fk7kpjR5A2k2OBkfrb6wgZJXEvyREMUqY+Jn+/5VqcohKPWOYJ7jH0OkerZX9qH ghmgX7Kslm3Rlx8TQhHvM1t5vp1x3Bo= X-MC-Unique: WdDIGCHnN2aMOSfkr7yc2w-1 X-Mimecast-MFC-AGG-ID: WdDIGCHnN2aMOSfkr7yc2w_1760359466 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 01/29] tests/functional/aarch64/aspeed_ast2700: Add PCIe and network tests Date: Mon, 13 Oct 2025 14:43:52 +0200 Message-ID: <20251013124421.71977-2-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359544979158500 From: Jamin Lin Extend the AST2700 and AST2700fc functional tests with PCIe and network checks. This patch introduces a helper "do_ast2700_pcie_test()" that runs "lspci" on the emulated system and verifies the expected PCIe devices: - 0002:00:00.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge - 0002:01:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Networ= k Connection Additional changes: - Add `-device e1000e,netdev=3Dnet1,bus=3Dpcie.2 -netdev user,id=3Dnet1` to= the AST2700 and AST2700fc test machines. - In the AST2700 vbootrom test, assign an IP address to the e1000e interface and verify it using `ip addr`. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-15-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- .../functional/aarch64/test_aspeed_ast2700.py | 21 +++++++++++++++++++ .../aarch64/test_aspeed_ast2700fc.py | 13 ++++++++++++ 2 files changed, 34 insertions(+) diff --git a/tests/functional/aarch64/test_aspeed_ast2700.py b/tests/functi= onal/aarch64/test_aspeed_ast2700.py index a3db26729499..0973fce0e995 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700.py +++ b/tests/functional/aarch64/test_aspeed_ast2700.py @@ -69,6 +69,16 @@ def do_ast2700_i2c_test(self): exec_command_and_wait_for_pattern(self, 'cat /sys/bus/i2c/devices/1-004d/hwmon/hwmon*/temp1_input', '1= 8000') =20 + def do_ast2700_pcie_test(self): + exec_command_and_wait_for_pattern(self, + 'lspci -s 0002:00:00.0', + '0002:00:00.0 PCI bridge: ' + 'ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge') + exec_command_and_wait_for_pattern(self, + 'lspci -s 0002:01:00.0', + '0002:01:00.0 Ethernet controller: ' + 'Intel Corporation 82574L Gigabit Network Connection') + def start_ast2700_test(self, name): num_cpu =3D 4 uboot_size =3D os.path.getsize(self.scratch_file(name, @@ -125,20 +135,31 @@ def test_aarch64_ast2700a0_evb_sdk_v09_06(self): =20 def test_aarch64_ast2700a1_evb_sdk_v09_06(self): self.set_machine('ast2700a1-evb') + self.require_netdev('user') =20 self.archive_extract(self.ASSET_SDK_V906_AST2700A1) + self.vm.add_args('-device', 'e1000e,netdev=3Dnet1,bus=3Dpcie.2') + self.vm.add_args('-netdev', 'user,id=3Dnet1') self.start_ast2700_test('ast2700-default') self.verify_openbmc_boot_and_login('ast2700-default') self.do_ast2700_i2c_test() + self.do_ast2700_pcie_test() =20 def test_aarch64_ast2700a1_evb_sdk_vbootrom_v09_07(self): self.set_machine('ast2700a1-evb') + self.require_netdev('user') =20 self.archive_extract(self.ASSET_SDK_V907_AST2700A1_VBOOROM) + self.vm.add_args('-device', 'e1000e,netdev=3Dnet1,bus=3Dpcie.2') + self.vm.add_args('-netdev', 'user,id=3Dnet1') self.start_ast2700_test_vbootrom('ast2700-default') self.verify_vbootrom_firmware_flow() self.verify_openbmc_boot_and_login('ast2700-default') self.do_ast2700_i2c_test() + self.do_ast2700_pcie_test() + exec_command_and_wait_for_pattern(self, + 'ip addr show dev eth2', + 'inet 10.0.2.15/24') =20 if __name__ =3D=3D '__main__': QemuSystemTest.main() diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/func= tional/aarch64/test_aspeed_ast2700fc.py index b85370e182ea..28b66614d970 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700fc.py +++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py @@ -20,6 +20,8 @@ def do_test_aarch64_aspeed_sdk_start(self, image): self.vm.set_console() self.vm.add_args('-device', 'tmp105,bus=3Daspeed.i2c.bus.1,address=3D0x4d,id= =3Dtmp-test') + self.vm.add_args('-device', 'e1000e,netdev=3Dnet1,bus=3Dpcie.2') + self.vm.add_args('-netdev', 'user,id=3Dnet1') self.vm.add_args('-drive', 'file=3D' + image + ',if=3Dmtd,format= =3Draw', '-net', 'nic', '-net', 'user', '-snapshot') =20 @@ -49,6 +51,16 @@ def do_ast2700_i2c_test(self): exec_command_and_wait_for_pattern(self, 'cat /sys/bus/i2c/devices/1-004d/hwmon/hwmon*/temp1_input', '1= 8000') =20 + def do_ast2700_pcie_test(self): + exec_command_and_wait_for_pattern(self, + 'lspci -s 0002:00:00.0', + '0002:00:00.0 PCI bridge: ' + 'ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge') + exec_command_and_wait_for_pattern(self, + 'lspci -s 0002:01:00.0', + '0002:01:00.0 Ethernet controller: ' + 'Intel Corporation 82574L Gigabit Network Connection') + def do_ast2700fc_ssp_test(self): self.vm.shutdown() self.vm.set_console(console_index=3D1) @@ -128,6 +140,7 @@ def test_aarch64_ast2700fc_sdk_v09_06(self): self.start_ast2700fc_test('ast2700-default') self.verify_openbmc_boot_and_login('ast2700-default') self.do_ast2700_i2c_test() + self.do_ast2700_pcie_test() self.do_ast2700fc_ssp_test() self.do_ast2700fc_tsp_test() =20 --=20 2.51.0 From nobody Fri Nov 14 18:17:42 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1760359556; cv=none; d=zohomail.com; s=zohoarc; b=YLz2vj/cCadp7Zt6Lm2m2pDuNQf+DUJoCIbln4yy2Pi8gH5f4NeIVs0TIDAzJN8q2/CRgcC0+G+uYFUiJq/FvlORGno0dtg9mfCwgNKgXmeDKXWrwaYDfSGu8zEPgCFPoF7nfIV2aoIE2h6YxFAfJgoc8G6DiR7+vXBwFYP5Nu8= ARC-Message-Signature: i=1; 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Mon, 13 Oct 2025 12:44:28 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.225.105]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id E4B241800446; Mon, 13 Oct 2025 12:44:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359472; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PH43Dh/oEMaltFLCgST7LlrkWmG9Na+ZM+oAkdq05pY=; b=LJbKeb+uS+Magq0u3tnOjJ+tDai48KrClyViU3YnGz3MsoAV7E1m+9Az/etat/GOXkf9jb BR0HoqxqeeN3BzkQicjnxCGczd/zO/nRn79DZZ5+O5uhQIIXROAbh1AlazWnrOt2v93AmZ XrHGVB4rc4mZ0HDJuXu1vV94tDNQ7cc= X-MC-Unique: TjzMoI0yMrydITepsxQ4SQ-1 X-Mimecast-MFC-AGG-ID: TjzMoI0yMrydITepsxQ4SQ_1760359468 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 02/29] aspeed: Don't set 'auto_create_sdcard' Date: Mon, 13 Oct 2025 14:43:53 +0200 Message-ID: <20251013124421.71977-3-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359558569154100 The Aspeed machines inherited from a 'no_sdcard' attribute when first introduced in QEMU. This attribute was later renamed to 'auto_create_sdcard' by commit cdc8d7cadaac ("hw/boards: Rename no_sdcard -> auto_create_sdcard") and set to 'true'. This has the indesirable efect to automatically create SD cards at init time. Remove 'auto_create_sdcard' to avoid creating a SD card device. Cc: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Link: https://lore.kernel.org/qemu-devel/20251003103024.1863551-1-clg@redha= t.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 6046ec0bb2a2..58cfbc713794 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1418,7 +1418,6 @@ static void aspeed_machine_palmetto_class_init(Object= Class *oc, amc->spi_model =3D "mx25l25635f"; amc->num_cs =3D 1; amc->i2c_init =3D palmetto_bmc_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 256 * MiB; aspeed_machine_class_init_cpus_defaults(mc); }; @@ -1436,7 +1435,6 @@ static void aspeed_machine_quanta_q71l_class_init(Obj= ectClass *oc, amc->spi_model =3D "mx25l25635e"; amc->num_cs =3D 1; amc->i2c_init =3D quanta_q71l_bmc_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 128 * MiB; aspeed_machine_class_init_cpus_defaults(mc); } @@ -1455,7 +1453,6 @@ static void aspeed_machine_supermicrox11_bmc_class_in= it(ObjectClass *oc, amc->num_cs =3D 1; amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; amc->i2c_init =3D palmetto_bmc_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 256 * MiB; aspeed_machine_class_init_cpus_defaults(mc); } @@ -1474,7 +1471,6 @@ static void aspeed_machine_supermicro_x11spi_bmc_clas= s_init(ObjectClass *oc, amc->num_cs =3D 1; amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; amc->i2c_init =3D palmetto_bmc_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 512 * MiB; aspeed_machine_class_init_cpus_defaults(mc); } @@ -1492,7 +1488,6 @@ static void aspeed_machine_ast2500_evb_class_init(Obj= ectClass *oc, amc->spi_model =3D "mx25l25635f"; amc->num_cs =3D 1; amc->i2c_init =3D ast2500_evb_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 512 * MiB; aspeed_machine_class_init_cpus_defaults(mc); }; @@ -1511,7 +1506,6 @@ static void aspeed_machine_yosemitev2_class_init(Obje= ctClass *oc, amc->spi_model =3D "mx25l25635e"; amc->num_cs =3D 2; amc->i2c_init =3D yosemitev2_bmc_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 512 * MiB; aspeed_machine_class_init_cpus_defaults(mc); }; @@ -1529,7 +1523,6 @@ static void aspeed_machine_romulus_class_init(ObjectC= lass *oc, amc->spi_model =3D "mx66l1g45g"; amc->num_cs =3D 2; amc->i2c_init =3D romulus_bmc_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 512 * MiB; aspeed_machine_class_init_cpus_defaults(mc); }; @@ -1548,7 +1541,6 @@ static void aspeed_machine_tiogapass_class_init(Objec= tClass *oc, amc->spi_model =3D "mx25l25635e"; amc->num_cs =3D 2; amc->i2c_init =3D tiogapass_bmc_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); }; @@ -1566,7 +1558,6 @@ static void aspeed_machine_sonorapass_class_init(Obje= ctClass *oc, amc->spi_model =3D "mx66l1g45g"; amc->num_cs =3D 2; amc->i2c_init =3D sonorapass_bmc_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 512 * MiB; aspeed_machine_class_init_cpus_defaults(mc); }; @@ -1584,7 +1575,6 @@ static void aspeed_machine_witherspoon_class_init(Obj= ectClass *oc, amc->spi_model =3D "mx66l1g45g"; amc->num_cs =3D 2; amc->i2c_init =3D witherspoon_bmc_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 512 * MiB; aspeed_machine_class_init_cpus_defaults(mc); }; @@ -1606,7 +1596,6 @@ static void aspeed_machine_ast2600_evb_class_init(Obj= ectClass *oc, ASPEED_MAC3_ON; amc->sdhci_wp_inverted =3D true; amc->i2c_init =3D ast2600_evb_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); aspeed_machine_ast2600_class_emmc_init(oc); @@ -1625,7 +1614,6 @@ static void aspeed_machine_g220a_class_init(ObjectCla= ss *oc, const void *data) amc->num_cs =3D 2; amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; amc->i2c_init =3D g220a_bmc_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 1024 * MiB; aspeed_machine_class_init_cpus_defaults(mc); }; @@ -1644,7 +1632,6 @@ static void aspeed_machine_fp5280g2_class_init(Object= Class *oc, amc->num_cs =3D 2; amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON; amc->i2c_init =3D fp5280g2_bmc_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 512 * MiB; aspeed_machine_class_init_cpus_defaults(mc); }; @@ -1663,7 +1650,6 @@ static void aspeed_machine_rainier_class_init(ObjectC= lass *oc, const void *data) amc->num_cs =3D 2; amc->macs_mask =3D ASPEED_MAC2_ON | ASPEED_MAC3_ON; amc->i2c_init =3D rainier_bmc_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); aspeed_machine_ast2600_class_emmc_init(oc); @@ -1686,7 +1672,6 @@ static void aspeed_machine_fuji_class_init(ObjectClas= s *oc, const void *data) amc->macs_mask =3D ASPEED_MAC3_ON; amc->i2c_init =3D fuji_bmc_i2c_init; amc->uart_default =3D ASPEED_DEV_UART1; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D FUJI_BMC_RAM_SIZE; aspeed_machine_class_init_cpus_defaults(mc); }; @@ -1708,7 +1693,6 @@ static void aspeed_machine_bletchley_class_init(Objec= tClass *oc, amc->num_cs =3D 2; amc->macs_mask =3D ASPEED_MAC2_ON; amc->i2c_init =3D bletchley_bmc_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D BLETCHLEY_BMC_RAM_SIZE; aspeed_machine_class_init_cpus_defaults(mc); } @@ -1728,7 +1712,6 @@ static void aspeed_machine_catalina_class_init(Object= Class *oc, amc->num_cs =3D 2; amc->macs_mask =3D ASPEED_MAC2_ON; amc->i2c_init =3D catalina_bmc_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D CATALINA_BMC_RAM_SIZE; aspeed_machine_class_init_cpus_defaults(mc); aspeed_machine_ast2600_class_emmc_init(oc); @@ -1796,7 +1779,6 @@ static void aspeed_machine_fby35_class_init(ObjectCla= ss *oc, const void *data) amc->num_cs =3D 2; amc->macs_mask =3D ASPEED_MAC3_ON; amc->i2c_init =3D fby35_i2c_init; - mc->auto_create_sdcard =3D true; /* FIXME: Replace this macro with something more general */ mc->default_ram_size =3D FUJI_BMC_RAM_SIZE; aspeed_machine_class_init_cpus_defaults(mc); @@ -1909,7 +1891,6 @@ static void aspeed_machine_ast2700a0_evb_class_init(O= bjectClass *oc, amc->uart_default =3D ASPEED_DEV_UART12; amc->i2c_init =3D ast2700_evb_i2c_init; amc->vbootrom =3D true; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); } @@ -1932,7 +1913,6 @@ static void aspeed_machine_ast2700a1_evb_class_init(O= bjectClass *oc, amc->uart_default =3D ASPEED_DEV_UART12; amc->i2c_init =3D ast2700_evb_i2c_init; amc->vbootrom =3D true; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); } @@ -1953,7 +1933,6 @@ static void aspeed_machine_qcom_dc_scm_v1_class_init(= ObjectClass *oc, amc->num_cs =3D 2; amc->macs_mask =3D ASPEED_MAC2_ON | ASPEED_MAC3_ON; amc->i2c_init =3D qcom_dc_scm_bmc_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); }; @@ -1973,7 +1952,6 @@ static void aspeed_machine_qcom_firework_class_init(O= bjectClass *oc, amc->num_cs =3D 2; amc->macs_mask =3D ASPEED_MAC2_ON | ASPEED_MAC3_ON; amc->i2c_init =3D qcom_dc_scm_firework_i2c_init; - mc->auto_create_sdcard =3D true; mc->default_ram_size =3D 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); }; --=20 2.51.0 From nobody Fri Nov 14 18:17:42 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1760360044; cv=none; d=zohomail.com; s=zohoarc; b=CsPsQ8qyYB3A8j2BcAjcBRBFzHDvt8IiF3OkYJlktHXcyEYkoL4zMXy+jYvuQuE243kz3/1hY7HDZblsVTLC3wpRWZp4sxYlSIBQn3sZvf6CxT9JmQZZTOtfhN2P+JhmPD1RUdJDnH0+VUyhZaUJ+vc7bRACPeqik69QnwxOsR4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760360044; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760360046596154100 From: Jamin Lin Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251003072107.3530642-2-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- tests/functional/arm/test_aspeed_ast1030.py | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/tests/functional/arm/test_aspeed_ast1030.py b/tests/functional= /arm/test_aspeed_ast1030.py index e47b597d0bd9..60e2b0251c6c 100755 --- a/tests/functional/arm/test_aspeed_ast1030.py +++ b/tests/functional/arm/test_aspeed_ast1030.py @@ -13,17 +13,17 @@ =20 class AST1030Machine(AspeedTest): =20 - ASSET_ZEPHYR_3_02 =3D Asset( + ASSET_ZEPHYR_3_03 =3D Asset( ('https://github.com/AspeedTech-BMC' - '/zephyr/releases/download/v00.03.02/ast1030-evb-demo.zip'), - '1ec83caab3ddd5d09481772801be7210e222cb015ce22ec6fffb8a76956dcd4f') + '/zephyr/releases/download/v00.03.03/ast1030-evb-demo.zip'), + '27cd73cdee6374bceb4ee58b3ace87989fa3f0684f4e612510804b588b24d4e0= ') =20 - def test_arm_ast1030_zephyros_3_02(self): + def test_arm_ast1030_zephyros_3_03(self): self.set_machine('ast1030-evb') =20 - kernel_name =3D "ast1030-evb-demo-3/zephyr.elf" + kernel_name =3D "ast1030-evb-demo/zephyr.elf" kernel_file =3D self.archive_extract( - self.ASSET_ZEPHYR_3_02, member=3Dkernel_name) + self.ASSET_ZEPHYR_3_03, member=3Dkernel_name) =20 self.vm.set_console() self.vm.add_args('-kernel', kernel_file, '-nographic') @@ -72,8 +72,9 @@ def test_arm_ast1030_zephyros_1_07(self): def test_arm_ast1030_otp_blockdev_device(self): self.vm.set_machine("ast1030-evb") =20 - kernel_name =3D "ast1030-evb-demo-3/zephyr.elf" - kernel_file =3D self.archive_extract(self.ASSET_ZEPHYR_3_02, membe= r=3Dkernel_name) + kernel_name =3D "ast1030-evb-demo/zephyr.elf" + kernel_file =3D self.archive_extract(self.ASSET_ZEPHYR_3_03, + member=3Dkernel_name) otp_img =3D self.generate_otpmem_image() =20 self.vm.set_console() --=20 2.51.0 From nobody Fri Nov 14 18:17:42 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359476; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+wLLowZR2JYVxvfqBLFtcuXNC0kQInOKATiif4no2gM=; b=AP/Pyd/LuUTX9KhX2y81kQ1AUGBAo/KB9AWJCw4LEGn4EtZzDsU0eFnpj9VBfeDNSZ8Fta ZB2wCzfTJ68C1bT2fnrVSghJi9azxgja/z61cTB/FpeAT8zN5/y+IdiwYSrgA5W6LlH3Yv QyJRgFAl27CqQxPbr5D/bB88KnGkgWo= X-MC-Unique: eNHDJ9ZxM3yD-UXWfh3Shw-1 X-Mimecast-MFC-AGG-ID: eNHDJ9ZxM3yD-UXWfh3Shw_1760359472 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 04/29] tests/functional/arm/test_aspeed_ast2500: Update test ASPEED SDK v09.08 Date: Mon, 13 Oct 2025 14:43:55 +0200 Message-ID: <20251013124421.71977-5-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359476; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jD3whb+AyK7uL3c3NqSwfzWssZjTm1+031MKx9wOVv4=; b=T3v2n5xOwVdioU0VRM5mn28fOka2+6c4lUcwn784CkW72gED1fM/XYG2tyVEmEGX8jgtQm pHJpLwQgXiyW1olkjSCY3DHH+B/Azui6jh4YSE6h6EMy/BcjFwZ1PWFEq0Nn8lEbfbma2T VTydA1VCIAz3gJFRUU8fCrc0pfNvseU= X-MC-Unique: ZkwlIG2ANYC8fToh4ysKHQ-1 X-Mimecast-MFC-AGG-ID: ZkwlIG2ANYC8fToh4ysKHQ_1760359474 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 05/29] tests/functional/arm/test_aspeed_ast2600: Update test ASPEED SDK v09.08 Date: Mon, 13 Oct 2025 14:43:56 +0200 Message-ID: <20251013124421.71977-6-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359481; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=y1n9/TEVgsijBQW/VTwJkBgfQKQp+H/4+6pCunli+Ks=; b=GTelR5ruyhbZViWNRNtIwWwmekzH2RgVH/Xp/fLqxGfOZNzO1HSJd0zDXwA6h3NRIyJcz2 Is9BmK9o+3JkT9mnDx+/6nIEl6mIQH9r2Jxjjk4I3cic7O19Xltued3y69WsnT+6WWzEot pE2rDBRWwNEA6DW/hlxwdWuqRONykRA= X-MC-Unique: ZqlNdHRsOouNqxZHUYz7qA-1 X-Mimecast-MFC-AGG-ID: ZqlNdHRsOouNqxZHUYz7qA_1760359476 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 06/29] tests/functional/aarch64/test_aspeed_ast2700: Update test ASPEED SDK v09.08 for A1 Date: Mon, 13 Oct 2025 14:43:57 +0200 Message-ID: <20251013124421.71977-7-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359631926158500 From: Jamin Lin Support for AST2700 A0 was dropped starting from SDK v09.07. The new SDK v09.08 only updates support for AST2700 A1. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251003072107.3530642-5-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- .../functional/aarch64/test_aspeed_ast2700.py | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/tests/functional/aarch64/test_aspeed_ast2700.py b/tests/functi= onal/aarch64/test_aspeed_ast2700.py index 0973fce0e995..0e9f10d991ea 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700.py +++ b/tests/functional/aarch64/test_aspeed_ast2700.py @@ -50,13 +50,9 @@ def verify_openbmc_boot_and_login(self, name): 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v= 09.06/ast2700-a0-default-obmc.tar.gz', '7247b6f19dbfb700686f8d9f723ac23f3eb229226c0589cb9b06b80d1b61f= 3cb') =20 - ASSET_SDK_V906_AST2700A1 =3D Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v= 09.06/ast2700-default-obmc.tar.gz', - 'f1d53e0be8a404ecce3e105f72bc50fa4e090ad13160ffa91b10a6e0233a9= dc6') - - ASSET_SDK_V907_AST2700A1_VBOOROM =3D Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v= 09.07/ast2700-default-obmc.tar.gz', - '6e9e0c4b13e0f26040eca3f4a7f17cf09fc0f5c37c820500ff79370cc3c44= add') + ASSET_SDK_V908_AST2700A1 =3D Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v= 09.08/ast2700-default-obmc.tar.gz', + 'eac3dc409b7ea3cd4b03d4792d3cebd469792ad893cb51e1d15f0fc20bd1e= 2cd') =20 def do_ast2700_i2c_test(self): exec_command_and_wait_for_pattern(self, @@ -133,11 +129,11 @@ def test_aarch64_ast2700a0_evb_sdk_v09_06(self): self.verify_openbmc_boot_and_login('ast2700-a0-default') self.do_ast2700_i2c_test() =20 - def test_aarch64_ast2700a1_evb_sdk_v09_06(self): + def test_aarch64_ast2700a1_evb_sdk_v09_08(self): self.set_machine('ast2700a1-evb') self.require_netdev('user') =20 - self.archive_extract(self.ASSET_SDK_V906_AST2700A1) + self.archive_extract(self.ASSET_SDK_V908_AST2700A1) self.vm.add_args('-device', 'e1000e,netdev=3Dnet1,bus=3Dpcie.2') self.vm.add_args('-netdev', 'user,id=3Dnet1') self.start_ast2700_test('ast2700-default') @@ -145,11 +141,11 @@ def test_aarch64_ast2700a1_evb_sdk_v09_06(self): self.do_ast2700_i2c_test() self.do_ast2700_pcie_test() =20 - def test_aarch64_ast2700a1_evb_sdk_vbootrom_v09_07(self): + def test_aarch64_ast2700a1_evb_sdk_vbootrom_v09_08(self): self.set_machine('ast2700a1-evb') self.require_netdev('user') =20 - self.archive_extract(self.ASSET_SDK_V907_AST2700A1_VBOOROM) + self.archive_extract(self.ASSET_SDK_V908_AST2700A1) self.vm.add_args('-device', 'e1000e,netdev=3Dnet1,bus=3Dpcie.2') self.vm.add_args('-netdev', 'user,id=3Dnet1') self.start_ast2700_test_vbootrom('ast2700-default') --=20 2.51.0 From nobody Fri Nov 14 18:17:42 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359482; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RnZ5UGj66iRaGtOQx3od5fSCxnQ3bZZNz27AYF+HCkk=; b=gWTTqauZXF+YNoqrlgFZ0vNmKjLCV+IXVEQ9rRSJBo6klqKC6827nhyq5nx8ttFEKfoEr8 Xzkvp6sCytp7C6824fkRxa3Fc8eh0KQZIAnsgLNmMFKMD8uc0EzdYz7adTilCOZPu7kfpB jzvjll92JrpPfuK/1hToLkbfa/rbmKY= X-MC-Unique: VHSMWpxHP3yJKU6p4cKc_Q-1 X-Mimecast-MFC-AGG-ID: VHSMWpxHP3yJKU6p4cKc_Q_1760359478 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 07/29] tests/functional/aarch64/test_aspeed_ast2700: Move eth2 IP check into common function Date: Mon, 13 Oct 2025 14:43:58 +0200 Message-ID: <20251013124421.71977-8-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359560669154100 From: Jamin Lin The eth2 IP address check was previously only performed in test_aarch64_ast2700a1_evb_sdk_vbootrom_v09_08. This patch moves the check into do_ast2700_pcie_test(), ensuring it is executed consistently across all AST2700 PCIe test runs. This avoids code duplication. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251003072107.3530642-6-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- tests/functional/aarch64/test_aspeed_ast2700.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/functional/aarch64/test_aspeed_ast2700.py b/tests/functi= onal/aarch64/test_aspeed_ast2700.py index 0e9f10d991ea..ef7ed522afc3 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700.py +++ b/tests/functional/aarch64/test_aspeed_ast2700.py @@ -74,6 +74,9 @@ def do_ast2700_pcie_test(self): 'lspci -s 0002:01:00.0', '0002:01:00.0 Ethernet controller: ' 'Intel Corporation 82574L Gigabit Network Connection') + exec_command_and_wait_for_pattern(self, + 'ip addr show dev eth2', + 'inet 10.0.2.15/24') =20 def start_ast2700_test(self, name): num_cpu =3D 4 @@ -153,9 +156,6 @@ def test_aarch64_ast2700a1_evb_sdk_vbootrom_v09_08(self= ): self.verify_openbmc_boot_and_login('ast2700-default') self.do_ast2700_i2c_test() self.do_ast2700_pcie_test() - exec_command_and_wait_for_pattern(self, - 'ip addr show dev eth2', - 'inet 10.0.2.15/24') =20 if __name__ =3D=3D '__main__': QemuSystemTest.main() --=20 2.51.0 From nobody Fri Nov 14 18:17:42 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359487; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hww3OPPAibTp42VYH/eWUnNj009Mb5L7mPS7FawiJtM=; b=CEIr0sZEuDvukHyV/+aI+72oOMdaOPhtMZOXbyXFKq1BnR+3vk9mBTjC920sPE5rk2xOJE I7tg3fvFMb4lb8h8x7+/yusA4Dx3nhBDj3AmXhCvI0w7gPZySdtqzYw4TJ72xYmvKqUrGI xEWFEF3hUfp27tZuDqkO6KI1q977mzY= X-MC-Unique: uK1OZIcQPDGpX2CDnpCSkA-1 X-Mimecast-MFC-AGG-ID: uK1OZIcQPDGpX2CDnpCSkA_1760359480 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Thomas Huth , Jamin Lin Subject: [PULL 08/29] tests/functional/arm: Split the ast2600 tests in two files Date: Mon, 13 Oct 2025 14:43:59 +0200 Message-ID: <20251013124421.71977-9-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359787241154100 The ast2600 test file currently includes tests for both the Buildroot and SDK images. Since the SDK image tests can take long to run, split them into a separate file to clearly distinguish the two sets of tests, improve parallelism and allow for different CI timeouts. Reviewed-by: Thomas Huth Reviewed-by: Jamin Lin Link: https://lore.kernel.org/qemu-devel/20251007090031.679003-1-clg@redhat= .com Signed-off-by: C=C3=A9dric Le Goater --- tests/functional/arm/meson.build | 6 +- ...00.py =3D> test_aspeed_ast2600_buildroot.py} | 74 --------------- .../functional/arm/test_aspeed_ast2600_sdk.py | 94 +++++++++++++++++++ 3 files changed, 98 insertions(+), 76 deletions(-) rename tests/functional/arm/{test_aspeed_ast2600.py =3D> test_aspeed_ast26= 00_buildroot.py} (57%) create mode 100755 tests/functional/arm/test_aspeed_ast2600_sdk.py diff --git a/tests/functional/arm/meson.build b/tests/functional/arm/meson.= build index e4e7dba8d087..d1ed076a6aa8 100644 --- a/tests/functional/arm/meson.build +++ b/tests/functional/arm/meson.build @@ -5,7 +5,8 @@ test_arm_timeouts =3D { 'aspeed_romulus' : 120, 'aspeed_witherspoon' : 120, 'aspeed_ast2500' : 720, - 'aspeed_ast2600' : 1200, + 'aspeed_ast2600_buildroot' : 720, + 'aspeed_ast2600_sdk' : 1200, 'aspeed_bletchley' : 480, 'aspeed_catalina' : 480, 'aspeed_gb200nvl_bmc' : 480, @@ -31,7 +32,8 @@ tests_arm_system_thorough =3D [ 'aspeed_romulus', 'aspeed_witherspoon', 'aspeed_ast2500', - 'aspeed_ast2600', + 'aspeed_ast2600_buildroot', + 'aspeed_ast2600_sdk', 'aspeed_bletchley', 'aspeed_catalina', 'aspeed_gb200nvl_bmc', diff --git a/tests/functional/arm/test_aspeed_ast2600.py b/tests/functional= /arm/test_aspeed_ast2600_buildroot.py similarity index 57% rename from tests/functional/arm/test_aspeed_ast2600.py rename to tests/functional/arm/test_aspeed_ast2600_buildroot.py index 0127913cfb65..51f2676c9061 100755 --- a/tests/functional/arm/test_aspeed_ast2600.py +++ b/tests/functional/arm/test_aspeed_ast2600_buildroot.py @@ -97,80 +97,6 @@ def test_arm_ast2600_evb_buildroot_tpm(self): =20 self.do_test_arm_aspeed_buildroot_poweroff() =20 - ASSET_SDK_V908_AST2600 =3D Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.0= 8/ast2600-default-obmc.tar.gz', - 'a0414f14ad696550efe083c2156dbeda855c08cc9ae7f40fe1b41bf292295f82') - - def do_ast2600_pcie_test(self): - exec_command_and_wait_for_pattern(self, - 'lspci -s 80:00.0', - '80:00.0 Host bridge: ' - 'ASPEED Technology, Inc. Device 2600') - exec_command_and_wait_for_pattern(self, - 'lspci -s 80:08.0', - '80:08.0 PCI bridge: ' - 'ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge') - exec_command_and_wait_for_pattern(self, - 'lspci -s 81:00.0', - '81:00.0 Ethernet controller: ' - 'Intel Corporation 82574L Gigabit Network Connection') - exec_command_and_wait_for_pattern(self, - 'ip addr show dev eth4', - 'inet 10.0.2.15/24') - - def test_arm_ast2600_evb_sdk(self): - self.set_machine('ast2600-evb') - self.require_netdev('user') - - self.archive_extract(self.ASSET_SDK_V908_AST2600) - - self.vm.add_args('-device', - 'tmp105,bus=3Daspeed.i2c.bus.5,address=3D0x4d,id=3Dtmp-test') - self.vm.add_args('-device', - 'ds1338,bus=3Daspeed.i2c.bus.5,address=3D0x32') - self.vm.add_args('-device', 'e1000e,netdev=3Dnet1,bus=3Dpcie.0') - self.vm.add_args('-netdev', 'user,id=3Dnet1') - self.do_test_arm_aspeed_sdk_start( - self.scratch_file("ast2600-default", "image-bmc")) - - self.wait_for_console_pattern('ast2600-default login:') - - exec_command_and_wait_for_pattern(self, 'root', 'Password:') - exec_command_and_wait_for_pattern(self, '0penBmc', - 'root@ast2600-default:~#') - - exec_command_and_wait_for_pattern(self, - 'echo lm75 0x4d > /sys/class/i2c-dev/i2c-5/device/new_device', - 'i2c i2c-5: new_device: Instantiated device lm75 at 0x4d') - exec_command_and_wait_for_pattern(self, - 'cat /sys/class/hwmon/hwmon19/temp1_input', '0') - self.vm.cmd('qom-set', path=3D'/machine/peripheral/tmp-test', - property=3D'temperature', value=3D18000) - exec_command_and_wait_for_pattern(self, - 'cat /sys/class/hwmon/hwmon19/temp1_input', '18000') - - exec_command_and_wait_for_pattern(self, - 'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-5/device/new_devic= e', - 'i2c i2c-5: new_device: Instantiated device ds1307 at 0x32') - year =3D time.strftime("%Y") - exec_command_and_wait_for_pattern(self, - '/sbin/hwclock -f /dev/rtc1', year) - self.do_ast2600_pcie_test() - - def test_arm_ast2600_otp_blockdev_device(self): - self.vm.set_machine("ast2600-evb") - - image_path =3D self.archive_extract(self.ASSET_SDK_V908_AST2600) - otp_img =3D self.generate_otpmem_image() - - self.vm.set_console() - self.vm.add_args( - "-blockdev", f"driver=3Dfile,filename=3D{otp_img},node-name=3D= otp", - "-global", "aspeed-otp.drive=3Dotp", - ) - self.do_test_arm_aspeed_sdk_start( - self.scratch_file("ast2600-default", "image-bmc")) - self.wait_for_console_pattern("ast2600-default login:") =20 if __name__ =3D=3D '__main__': AspeedTest.main() diff --git a/tests/functional/arm/test_aspeed_ast2600_sdk.py b/tests/functi= onal/arm/test_aspeed_ast2600_sdk.py new file mode 100755 index 000000000000..e3d4ed09e2ee --- /dev/null +++ b/tests/functional/arm/test_aspeed_ast2600_sdk.py @@ -0,0 +1,94 @@ +#!/usr/bin/env python3 +# +# Functional test that boots the ASPEED machines +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import os +import time + +from qemu_test import Asset +from aspeed import AspeedTest +from qemu_test import exec_command_and_wait_for_pattern + + +class AST2600Machine(AspeedTest): + + ASSET_SDK_V908_AST2600 =3D Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.0= 8/ast2600-default-obmc.tar.gz', + 'a0414f14ad696550efe083c2156dbeda855c08cc9ae7f40fe1b41bf292295f82') + + def do_ast2600_pcie_test(self): + exec_command_and_wait_for_pattern(self, + 'lspci -s 80:00.0', + '80:00.0 Host bridge: ' + 'ASPEED Technology, Inc. Device 2600') + exec_command_and_wait_for_pattern(self, + 'lspci -s 80:08.0', + '80:08.0 PCI bridge: ' + 'ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge') + exec_command_and_wait_for_pattern(self, + 'lspci -s 81:00.0', + '81:00.0 Ethernet controller: ' + 'Intel Corporation 82574L Gigabit Network Connection') + exec_command_and_wait_for_pattern(self, + 'ip addr show dev eth4', + 'inet 10.0.2.15/24') + + def test_arm_ast2600_evb_sdk(self): + self.set_machine('ast2600-evb') + self.require_netdev('user') + + self.archive_extract(self.ASSET_SDK_V908_AST2600) + + self.vm.add_args('-device', + 'tmp105,bus=3Daspeed.i2c.bus.5,address=3D0x4d,id=3Dtmp-test') + self.vm.add_args('-device', + 'ds1338,bus=3Daspeed.i2c.bus.5,address=3D0x32') + self.vm.add_args('-device', 'e1000e,netdev=3Dnet1,bus=3Dpcie.0') + self.vm.add_args('-netdev', 'user,id=3Dnet1') + self.do_test_arm_aspeed_sdk_start( + self.scratch_file("ast2600-default", "image-bmc")) + + self.wait_for_console_pattern('ast2600-default login:') + + exec_command_and_wait_for_pattern(self, 'root', 'Password:') + exec_command_and_wait_for_pattern(self, '0penBmc', + 'root@ast2600-default:~#') + + exec_command_and_wait_for_pattern(self, + 'echo lm75 0x4d > /sys/class/i2c-dev/i2c-5/device/new_device', + 'i2c i2c-5: new_device: Instantiated device lm75 at 0x4d') + exec_command_and_wait_for_pattern(self, + 'cat /sys/class/hwmon/hwmon19/temp1_input', '0') + self.vm.cmd('qom-set', path=3D'/machine/peripheral/tmp-test', + property=3D'temperature', value=3D18000) + exec_command_and_wait_for_pattern(self, + 'cat /sys/class/hwmon/hwmon19/temp1_input', '18000') + + exec_command_and_wait_for_pattern(self, + 'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-5/device/new_devic= e', + 'i2c i2c-5: new_device: Instantiated device ds1307 at 0x32') + year =3D time.strftime("%Y") + exec_command_and_wait_for_pattern(self, + '/sbin/hwclock -f /dev/rtc1', year) + self.do_ast2600_pcie_test() + + def test_arm_ast2600_otp_blockdev_device(self): + self.vm.set_machine("ast2600-evb") + + image_path =3D self.archive_extract(self.ASSET_SDK_V908_AST2600) + otp_img =3D self.generate_otpmem_image() + + self.vm.set_console() + self.vm.add_args( + "-blockdev", f"driver=3Dfile,filename=3D{otp_img},node-name=3D= otp", + "-global", "aspeed-otp.drive=3Dotp", + ) + self.do_test_arm_aspeed_sdk_start( + self.scratch_file("ast2600-default", "image-bmc")) + self.wait_for_console_pattern("ast2600-default login:") + + +if __name__ =3D=3D '__main__': + AspeedTest.main() --=20 2.51.0 From nobody Fri Nov 14 18:17:42 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359486; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ijCwE0uUK8yoWCTNQnVIDnTuHcOQiowpag0WnR7dcns=; b=LtYcpSrslT0A8ww0ym/anO7BlmcF6Y2Q/MxlZ3yulYAcPTTIaYMTpEU7MuUPOi9Z+ymqwn B7yJORF2CWl4Per6o+LCluWVB1et8qTq9l4yB+j8VQnZlC1HM2hYLEMNcBplure46t/Z6v 97fpaLtl1jjtdo6LbBGf7Qn25R27bBM= X-MC-Unique: arH30Y27PvaJ0UWwBSETtA-1 X-Mimecast-MFC-AGG-ID: arH30Y27PvaJ0UWwBSETtA_1760359482 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Patrick Williams Subject: [PULL 09/29] aspeed: Deprecate the sonorapass-bmc machine Date: Mon, 13 Oct 2025 14:44:00 +0200 Message-ID: <20251013124421.71977-10-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359803723158500 The 'sonorapass-bmc' machine represents a lab server that never entered production. There are no functional tests for this machine which makes harder to determine when something becomes deprecated or unused. Since the machine does not rely on any specific device models, it can be replaced by the 'ast2500-evb' machine using the 'fmc-model' option to specify the flash type. The I2C devices connected to the board can be defined via the QEMU command line. Cc: Patrick Williams Link: https://lore.kernel.org/qemu-devel/20251007141604.761686-2-clg@redhat= .com Signed-off-by: C=C3=A9dric Le Goater --- docs/about/deprecated.rst | 9 +++++++++ hw/arm/aspeed.c | 1 + 2 files changed, 10 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 67e527740c0e..ce8fe9ac1be7 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -285,6 +285,15 @@ and serves as the initial engineering sample rather th= an a production version. A newer revision, A1, is now supported, and the ``ast2700a1-evb`` should replace the older A0 version. =20 +Arm ``sonorapass-bmc`` machine (since 10.2) +''''''''''''''''''''''''''''''''''''''''''' + +The ``sonorapass-bmc`` machine represents a lab server that never +entered production. Since it does not rely on any specific device +models, it can be replaced by the ``ast2500-evb`` machine using the +``fmc-model`` option to specify the flash type. The I2C devices +connected to the board can be defined via the QEMU command line. + RISC-V default machine option (since 10.0) '''''''''''''''''''''''''''''''''''''''''' =20 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 58cfbc713794..d3a0c81f454f 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1552,6 +1552,7 @@ static void aspeed_machine_sonorapass_class_init(Obje= ctClass *oc, AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); =20 mc->desc =3D "OCP SonoraPass BMC (ARM1176)"; + mc->deprecation_reason =3D "use 'ast2500-evb' instead"; amc->soc_name =3D "ast2500-a1"; amc->hw_strap1 =3D SONORAPASS_BMC_HW_STRAP1; amc->fmc_model =3D "mx66l1g45g"; --=20 2.51.0 From nobody Fri Nov 14 18:17:42 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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bh=8WfXGILBNYR99ZcZmGRV3dHeIDrpAHHauEYKqToDeHM=; b=b3qfwJclU8/NhtPuBrgiLy7Ux1s+VOaFDkE++Kg4yACtYkAyswKM1JaJ4y4vtGrq65h/eW ZN6h6E/CFuR1wNt7o2JMhOyXvEhTnoc/ut61u66PyN6VSLPWhtFwL9jN6xrhfwPSA5c3iQ mNXjtzZ67pl8S0YTg4ItC26rQqmWWas= X-MC-Unique: kAr_k-8yMGKtFE_G_mp39A-1 X-Mimecast-MFC-AGG-ID: kAr_k-8yMGKtFE_G_mp39A_1760359484 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Jae Hyun Yoo Subject: [PULL 10/29] aspeed: Deprecate the qcom-dc-scm-v1-bmc and qcom-firework-bmc machines Date: Mon, 13 Oct 2025 14:44:01 +0200 Message-ID: <20251013124421.71977-11-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359694057154100 There are no functional tests for the 'qcom-dc-scm-v1-bmc' and 'qcom-firework-bmc' machines which makes harder to determine when something becomes deprecated or unused. Since the machines do not rely on any specific device models, they can be replaced by the 'ast2600-evb' machine using the 'fmc-model' option to specify the flash type. The I2C devices connected to the board can be defined via the QEMU command line. Cc: Jae Hyun Yoo Link: https://lore.kernel.org/qemu-devel/20251007141604.761686-3-clg@redhat= .com Signed-off-by: C=C3=A9dric Le Goater --- docs/about/deprecated.rst | 10 ++++++++++ hw/arm/aspeed.c | 2 ++ 2 files changed, 12 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index ce8fe9ac1be7..f6410037ead2 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -294,6 +294,16 @@ models, it can be replaced by the ``ast2500-evb`` mach= ine using the ``fmc-model`` option to specify the flash type. The I2C devices connected to the board can be defined via the QEMU command line. =20 +Arm ``qcom-dc-scm-v1-bmc`` and ``qcom-firework-bmc`` machine (since 10.2) +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +The ``qcom-dc-scm-v1-bmc`` and ``qcom-firework-bmc`` represent lab +servers that never entered production. Since they do not rely on any +specific device models, they can be replaced by the ``ast2600-evb`` +machine using the ``fmc-model`` option to specify the flash type. The +I2C devices connected to the board can be defined via the QEMU command +line. + RISC-V default machine option (since 10.0) '''''''''''''''''''''''''''''''''''''''''' =20 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index d3a0c81f454f..0707a760fda6 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1926,6 +1926,7 @@ static void aspeed_machine_qcom_dc_scm_v1_class_init(= ObjectClass *oc, AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); =20 mc->desc =3D "Qualcomm DC-SCM V1 BMC (Cortex A7)"; + mc->deprecation_reason =3D "use 'ast2600-evb' instead"; amc->soc_name =3D "ast2600-a3"; amc->hw_strap1 =3D QCOM_DC_SCM_V1_BMC_HW_STRAP1; amc->hw_strap2 =3D QCOM_DC_SCM_V1_BMC_HW_STRAP2; @@ -1945,6 +1946,7 @@ static void aspeed_machine_qcom_firework_class_init(O= bjectClass *oc, AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); =20 mc->desc =3D "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; + mc->deprecation_reason =3D "use 'ast2600-evb' instead"; amc->soc_name =3D "ast2600-a3"; amc->hw_strap1 =3D QCOM_DC_SCM_V1_BMC_HW_STRAP1; amc->hw_strap2 =3D QCOM_DC_SCM_V1_BMC_HW_STRAP2; --=20 2.51.0 From nobody Fri Nov 14 18:17:42 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1760359936; cv=none; d=zohomail.com; s=zohoarc; b=ltjVt7MtlHQdT0Fy5wv0YnWOZ01TJVgc88s3ZPaCE/Ohg1ryhZyRQY9GgbA1+QZzdVMIluMYfMFmtaqZEzB1fjL+Pmsi9kkNJ/tD66gXTvT5cgBTBxl/cj+yXIu0UhO6s03sgezBte8mp+G8esZ9dk7QUrn+zIzdqDeYattnz9U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760359936; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=L9vgsJ6bfc1NYPsE3zN5lYySPC6wzDYbQwka3TMd7pQ=; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359488; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=L9vgsJ6bfc1NYPsE3zN5lYySPC6wzDYbQwka3TMd7pQ=; b=cCPArEot1Ezk4ktKQcyNJmPP5Z5PqqdjC/me58yJ5FXd4b4fMsvozK1WLaRqNBslP6TJEH JnMrtQFsp6WOtzDcSy6AZAyfUGhFbXjFUM3YCUrDTH4lciIaop/zXdao3APEGISFLnVaGM S+ASSYDIuZmSK6T983ieKtQZnwcKIuc= X-MC-Unique: EEYH1uyiMuaM28RLlcOMJQ-1 X-Mimecast-MFC-AGG-ID: EEYH1uyiMuaM28RLlcOMJQ_1760359486 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , John Wang Subject: [PULL 11/29] aspeed: Deprecate the fp5280g2-bmc machine Date: Mon, 13 Oct 2025 14:44:02 +0200 Message-ID: <20251013124421.71977-12-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359938981154100 There are no functional tests for the 'fp5280g2-bmc' machine which makes harder to determine when something becomes deprecated or unused. Since the machine does not rely on any specific device models, it can be replaced by the 'ast2500-evb' machine using the 'fmc-model' option to specify the flash type. The I2C devices connected to the board can be defined via the QEMU command line. Cc: John Wang Link: https://lore.kernel.org/qemu-devel/20251007141604.761686-4-clg@redhat= .com Signed-off-by: C=C3=A9dric Le Goater --- docs/about/deprecated.rst | 8 ++++++++ hw/arm/aspeed.c | 1 + 2 files changed, 9 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index f6410037ead2..98361f5832dc 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -304,6 +304,14 @@ machine using the ``fmc-model`` option to specify the = flash type. The I2C devices connected to the board can be defined via the QEMU command line. =20 +Arm ``fp5280g2-bmc`` machine (since 10.2) +''''''''''''''''''''''''''''''''''''''''''' + +The ``fp5280g2-bmc`` machine does not rely on any specific device +models, it can be replaced by the ``ast2500-evb`` machine using the +``fmc-model`` option to specify the flash type. The I2C devices +connected to the board can be defined via the QEMU command line. + RISC-V default machine option (since 10.0) '''''''''''''''''''''''''''''''''''''''''' =20 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 0707a760fda6..e73185eeb35c 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1626,6 +1626,7 @@ static void aspeed_machine_fp5280g2_class_init(Object= Class *oc, AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); =20 mc->desc =3D "Inspur FP5280G2 BMC (ARM1176)"; + mc->deprecation_reason =3D "use 'ast2500-evb' instead"; amc->soc_name =3D "ast2500-a1"; amc->hw_strap1 =3D FP5280G2_BMC_HW_STRAP1; amc->fmc_model =3D "n25q512a"; --=20 2.51.0 From nobody Fri Nov 14 18:17:42 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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bh=Khd9Ah7PVkvKBXPNxXDw7F9r6smK+lE2bENEWbULZ70=; b=D9PB2lAAe7P2itQjuUfrmnW7flWc9a98WEMz9YSJCy37MA2Pgkg8hUk+8jsyqO8fFa9mLf 1Ov+iO7QhqKbwoMSi5QPYvZ8QvdKyzFS8xrbqBn1yOwrz92reNttySonTRdSUFcIbGEJBT /8iFVSNOJbkYFBT/fEaDcn7HuGsrLTk= X-MC-Unique: 2E_i42YFO8m0Y3dG2tdXuw-1 X-Mimecast-MFC-AGG-ID: 2E_i42YFO8m0Y3dG2tdXuw_1760359488 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Thomas Huth , Jamin Lin Subject: [PULL 12/29] test/functional/aarch64: Remove test for the ast2700a0-evb machine Date: Mon, 13 Oct 2025 14:44:03 +0200 Message-ID: <20251013124421.71977-13-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359900431154100 The 'ast2700a0-evb' machine was deprecated in commit 6888a4a9c860 and removal is scheduled in the QEMU 11.0 release. This change removes the corresponding tests ahead of time to save CI resources. Cc: Thomas Huth Reviewed-by: Thomas Huth Reviewed-by: Jamin Lin Link: https://lore.kernel.org/qemu-devel/20251007141604.761686-5-clg@redhat= .com Signed-off-by: C=C3=A9dric Le Goater --- tests/functional/aarch64/test_aspeed_ast2700.py | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/tests/functional/aarch64/test_aspeed_ast2700.py b/tests/functi= onal/aarch64/test_aspeed_ast2700.py index ef7ed522afc3..a60dc1259f69 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700.py +++ b/tests/functional/aarch64/test_aspeed_ast2700.py @@ -46,10 +46,6 @@ def verify_openbmc_boot_and_login(self, name): exec_command_and_wait_for_pattern(self, 'root', 'Password:') exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~= #') =20 - ASSET_SDK_V906_AST2700 =3D Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v= 09.06/ast2700-a0-default-obmc.tar.gz', - '7247b6f19dbfb700686f8d9f723ac23f3eb229226c0589cb9b06b80d1b61f= 3cb') - ASSET_SDK_V908_AST2700A1 =3D Asset( 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v= 09.08/ast2700-default-obmc.tar.gz', 'eac3dc409b7ea3cd4b03d4792d3cebd469792ad893cb51e1d15f0fc20bd1e= 2cd') @@ -124,14 +120,6 @@ def start_ast2700_test_vbootrom(self, name): self.do_test_aarch64_aspeed_sdk_start( self.scratch_file(name, 'image-bmc')) =20 - def test_aarch64_ast2700a0_evb_sdk_v09_06(self): - self.set_machine('ast2700a0-evb') - - self.archive_extract(self.ASSET_SDK_V906_AST2700) - self.start_ast2700_test('ast2700-a0-default') - self.verify_openbmc_boot_and_login('ast2700-a0-default') - self.do_ast2700_i2c_test() - def test_aarch64_ast2700a1_evb_sdk_v09_08(self): self.set_machine('ast2700a1-evb') self.require_netdev('user') --=20 2.51.0 From nobody Fri Nov 14 18:17:42 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359494; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zj8RUAWBVOGH7gmS2hiKjB5z3WQq2i5b5hBsObdM3AU=; b=SFEbHOOK25TzNghG1LjD/y2o1iUeM2OJ32MzFS7qNMCWO1XnHkYHgotZxdtTFLVRz6r+FN Zl2xcfCdrPrAW1rboE1GpCzm3ZYnUTA8ytVxp93V3s/F74PA20f9jKi88xzKXC06VnpR8j dcDsyKMzFTkkIEipT1t8YOOM4NXkj0o= X-MC-Unique: XhIp4oITMl6a2JLF9XuftA-1 X-Mimecast-MFC-AGG-ID: XhIp4oITMl6a2JLF9XuftA_1760359491 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Thomas Huth , Jamin Lin Subject: [PULL 13/29] test/functional/aarch64: Split the ast2700a1-evb OpenBMC boot test Date: Mon, 13 Oct 2025 14:44:04 +0200 Message-ID: <20251013124421.71977-14-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359651535154100 The 'ast2700a1-evb' machine has two functional tests: one loading firmware components into memory and another using a vbootrom image. Both tests perform a full OpenBMC boot and run checks on I2C and PCIe devices, which is redundant and time-consuming. To save CI resources, the vbootrom test is refactored to focus on the firmware boot process only. The OpenBMC boot verification logic is split and a new verify_openbmc_boot_start() helper is introduced to only wait for the kernel to start. The vbootrom test now uses this function and the less essential I2C and PCIe checks have been removed from this test case. Cc: Thomas Huth Reviewed-by: Thomas Huth Reviewed-by: Jamin Lin Link: https://lore.kernel.org/qemu-devel/20251007141604.761686-6-clg@redhat= .com [ clg: Changed pattern from 'Starting kernel ...' to 'Linux version ' ] Signed-off-by: C=C3=A9dric Le Goater --- tests/functional/aarch64/test_aspeed_ast2700.py | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/tests/functional/aarch64/test_aspeed_ast2700.py b/tests/functi= onal/aarch64/test_aspeed_ast2700.py index a60dc1259f69..0ced1a25021d 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700.py +++ b/tests/functional/aarch64/test_aspeed_ast2700.py @@ -37,10 +37,13 @@ def verify_vbootrom_firmware_flow(self): wait_for_console_pattern(self, 'done') wait_for_console_pattern(self, 'Jumping to BL31 (Trusted Firmware-= A)') =20 - def verify_openbmc_boot_and_login(self, name): + def verify_openbmc_boot_start(self): wait_for_console_pattern(self, 'U-Boot 2023.10') wait_for_console_pattern(self, '## Loading kernel from FIT Image') - wait_for_console_pattern(self, 'Starting kernel ...') + wait_for_console_pattern(self, 'Linux version ') + + def verify_openbmc_boot_and_login(self, name): + self.verify_openbmc_boot_start() =20 wait_for_console_pattern(self, f'{name} login:') exec_command_and_wait_for_pattern(self, 'root', 'Password:') @@ -141,9 +144,7 @@ def test_aarch64_ast2700a1_evb_sdk_vbootrom_v09_08(self= ): self.vm.add_args('-netdev', 'user,id=3Dnet1') self.start_ast2700_test_vbootrom('ast2700-default') self.verify_vbootrom_firmware_flow() - self.verify_openbmc_boot_and_login('ast2700-default') - self.do_ast2700_i2c_test() - self.do_ast2700_pcie_test() + self.verify_openbmc_boot_start() =20 if __name__ =3D=3D '__main__': QemuSystemTest.main() --=20 2.51.0 From nobody Fri Nov 14 18:17:42 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359497; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ndGAITILTBfTxJbWiNsuyE3u127Ud0cKP6n5GASFFH4=; b=ZP/AeMUSvXDCl/Q5JG74bHbDD5PSlD0VkRf+UkKmlKFj8VB6I+11yDMH9IgIaWh74Xy1k8 +NSPJCObhgM5JcYBZbEJKpE4k/0spSjjT+pD0XD43w24vXyGO8iQBkwGIowW35v5lb69oL FrO+D5gw2qKlT8jWZqhHYb/KNeZ4KYQ= X-MC-Unique: 1LmrVFt0Na6gjZ5cZeTeng-1 X-Mimecast-MFC-AGG-ID: 1LmrVFt0Na6gjZ5cZeTeng_1760359493 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 14/29] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_uart_first() API Date: Mon, 13 Oct 2025 14:44:05 +0200 Message-ID: <20251013124421.71977-15-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359708383154100 From: Jamin Lin Refactor the aspeed_uart_first() helper to remove its dependency on AspeedSoCState and make the UART helper APIs more generic. The function now takes uarts_base as an integer parameter instead of requiring a full SoC class instance. Corresponding call sites in aspeed.c and aspeed_soc_common.c are updated accordingly. No functional change. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-2-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 6 +++--- hw/arm/aspeed.c | 2 +- hw/arm/aspeed_soc_common.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index ed32efb543f4..5786fbbcbbe7 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -326,14 +326,14 @@ static inline int aspeed_uart_index(int uart_dev) return uart_dev - ASPEED_DEV_UART0; } =20 -static inline int aspeed_uart_first(AspeedSoCClass *sc) +static inline int aspeed_uart_first(int uarts_base) { - return aspeed_uart_index(sc->uarts_base); + return aspeed_uart_index(uarts_base); } =20 static inline int aspeed_uart_last(AspeedSoCClass *sc) { - return aspeed_uart_first(sc) + sc->uarts_num - 1; + return aspeed_uart_first(sc->uarts_base) + sc->uarts_num - 1; } =20 #endif /* ASPEED_SOC_H */ diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index e73185eeb35c..49d8debf9988 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1310,7 +1310,7 @@ static void aspeed_set_bmc_console(Object *obj, const= char *value, Error **errp) AspeedMachineClass *amc =3D ASPEED_MACHINE_GET_CLASS(bmc); AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(object_class_by_name(amc->soc_= name)); int val; - int uart_first =3D aspeed_uart_first(sc); + int uart_first =3D aspeed_uart_first(sc->uarts_base); int uart_last =3D aspeed_uart_last(sc); =20 if (sscanf(value, "uart%u", &val) !=3D 1) { diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index bc70e864fba7..a4e74acdce77 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -62,7 +62,7 @@ bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **e= rrp) void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr) { AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); - int uart_first =3D aspeed_uart_first(sc); + int uart_first =3D aspeed_uart_first(sc->uarts_base); int uart_index =3D aspeed_uart_index(dev); int i =3D uart_index - uart_first; =20 --=20 2.51.0 From nobody Fri Nov 14 18:17:42 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1760359652; cv=none; d=zohomail.com; s=zohoarc; b=bL8SBh/0rlNnmB8jn0HJXzh6RYnS0Ghmrfie2HW75/kpGS98CU4ArWZj8ANBPLjCphME9udecLP52tB3IDAOTYAHYA1b7ubS62ZPQ2Q16DVB6lrKs1HsG/+WtAqFv9gFv3Zv93d5p6SvNU83Iq09UjiwGRhFbo9NpCOkTZ0wlXo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760359652; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 13 Oct 2025 12:44:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359499; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SrwrWKaIS2o37Qz4VfMfpXaOvS9X4oGUK9EI9bLyxAM=; b=Tb3zTJ2XkxAtuEVEKrvEkIZ3wislfHhLYsq+yXMCKuCHsAYZSRto1hnBPxmDHiLaXFZ15s xiRfR0ON+obAs2THzIEXPK26ZtlaGKzrIAxsSpeQ6rxd61LcIRGOn524tCrWKklTXAxuxG PWDMeJjKe2jPGSc4Fo+tHxg5AMH3Uhw= X-MC-Unique: 4wUgr6e5N_CzxqvL0IlM5w-1 X-Mimecast-MFC-AGG-ID: 4wUgr6e5N_CzxqvL0IlM5w_1760359495 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 15/29] hw/arm/aspeed: Remove AspeedSoCClass dependency from aspeed_uart_last() API Date: Mon, 13 Oct 2025 14:44:06 +0200 Message-ID: <20251013124421.71977-16-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359655979158500 From: Jamin Lin Refactor the aspeed_uart_last() helper to remove its dependency on AspeedSoCClass and make the UART helper APIs more generic. The function now takes uarts_base and uarts_num as integer parameters instead of requiring a full SoC class instance. All related call sites in aspeed.c are updated accordingly. No functional change. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-3-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 4 ++-- hw/arm/aspeed.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 5786fbbcbbe7..0162738f884e 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -331,9 +331,9 @@ static inline int aspeed_uart_first(int uarts_base) return aspeed_uart_index(uarts_base); } =20 -static inline int aspeed_uart_last(AspeedSoCClass *sc) +static inline int aspeed_uart_last(int uarts_base, int uarts_num) { - return aspeed_uart_first(sc->uarts_base) + sc->uarts_num - 1; + return aspeed_uart_first(uarts_base) + uarts_num - 1; } =20 #endif /* ASPEED_SOC_H */ diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 49d8debf9988..ad17471c8d61 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1311,7 +1311,7 @@ static void aspeed_set_bmc_console(Object *obj, const= char *value, Error **errp) AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(object_class_by_name(amc->soc_= name)); int val; int uart_first =3D aspeed_uart_first(sc->uarts_base); - int uart_last =3D aspeed_uart_last(sc); + int uart_last =3D aspeed_uart_last(sc->uarts_base, sc->uarts_num); =20 if (sscanf(value, "uart%u", &val) !=3D 1) { error_setg(errp, "Bad value for \"uart\" property"); --=20 2.51.0 From nobody Fri Nov 14 18:17:42 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1760359747; cv=none; d=zohomail.com; s=zohoarc; b=CAwvZYSA+Us5aJGfydwcDEpnhjq6TJ3PInSIbylOVd2MXJaHJjCcpTOJD+Jg32QkPHXQGF/cmAfLOh7LzvZJHGTFWV/8+1/nbrg33BnDbViV1c3jlh2IQulz3yOkmKnl+oA6EEipMNTGdPpnaaJomWHtOp7mxJKnoPxLG71nQwk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760359747; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 13 Oct 2025 12:44:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359503; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=p9h37oTgNmYC61PStwVjOgSvI6sNjftmWJs14KANrYw=; b=DolfS/hkV4MDd0H9i2TM3zlzPKxQlRyvfx3d3EWwQoiG3LE38dUAlLf0imc0004Recf2rS zlZnSLUwUJhBVHH2G/4yEWk4KGA59wghYW7NAQkAEu0P+o1nytTrNRw98JjWPSrvCha1xu +rscOIn58eREiseL5cXlC6SSMpcUUzk= X-MC-Unique: N0caCOjZMk2xsald2OvbEQ-1 X-Mimecast-MFC-AGG-ID: N0caCOjZMk2xsald2OvbEQ_1760359497 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 16/29] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_soc_uart_set_chr() API Date: Mon, 13 Oct 2025 14:44:07 +0200 Message-ID: <20251013124421.71977-17-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359759204158500 From: Jamin Lin Refactor the aspeed_soc_uart_set_chr() helper to remove its dependency on AspeedSoCState and make the UART character device binding more generic. The function now takes SerialMM *uart, uarts_base, and uarts_num as arguments instead of relying on AspeedSoCState. All affected call sites in aspeed.c, aspeed_ast27x0-fc.c, and fby35.c are updated to use the new parameter format. This improves API flexibility and enables reuse across different Aspeed SoC variants without requiring access to internal SoC state. No functional change. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-4-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 3 ++- hw/arm/aspeed.c | 6 ++++-- hw/arm/aspeed_ast27x0-fc.c | 13 ++++++++++--- hw/arm/aspeed_soc_common.c | 10 +++++----- hw/arm/fby35.c | 10 ++++++++-- 5 files changed, 29 insertions(+), 13 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 0162738f884e..c870bf55865e 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -306,7 +306,8 @@ enum { =20 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); -void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr); +void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base, + int uarts_num, Chardev *chr); bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr a= ddr); void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index ad17471c8d61..21ee62f75044 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -299,12 +299,14 @@ static void connect_serial_hds_to_uarts(AspeedMachine= State *bmc) AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); int uart_chosen =3D bmc->uart_chosen ? bmc->uart_chosen : amc->uart_de= fault; =20 - aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); + aspeed_soc_uart_set_chr(s->uart, uart_chosen, sc->uarts_base, + sc->uarts_num, serial_hd(0)); for (int i =3D 1, uart =3D sc->uarts_base; i < sc->uarts_num; uart++) { if (uart =3D=3D uart_chosen) { continue; } - aspeed_soc_uart_set_chr(s, uart, serial_hd(i++)); + aspeed_soc_uart_set_chr(s->uart, uart, sc->uarts_base, sc->uarts_n= um, + serial_hd(i++)); } } =20 diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index 2e16a0340a7b..e598f57ca228 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -91,7 +91,8 @@ static bool ast2700fc_ca35_init(MachineState *machine, Er= ror **errp) AST2700FC_HW_STRAP1, &error_abort); object_property_set_int(OBJECT(&s->ca35), "hw-strap2", AST2700FC_HW_STRAP2, &error_abort); - aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART12, serial_hd(0)); + aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART12, sc->uarts_base, + sc->uarts_num, serial_hd(0)); if (!qdev_realize(DEVICE(&s->ca35), NULL, errp)) { return false; } @@ -115,6 +116,7 @@ static bool ast2700fc_ca35_init(MachineState *machine, = Error **errp) static bool ast2700fc_ssp_init(MachineState *machine, Error **errp) { AspeedSoCState *soc; + AspeedSoCClass *sc; Ast2700FCState *s =3D AST2700A1FC(machine); s->ssp_sysclk =3D clock_new(OBJECT(s), "SSP_SYSCLK"); clock_set_hz(s->ssp_sysclk, 200000000ULL); @@ -128,7 +130,9 @@ static bool ast2700fc_ssp_init(MachineState *machine, E= rror **errp) OBJECT(&s->ssp_memory), &error_abort); =20 soc =3D ASPEED_SOC(&s->ssp); - aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART4, serial_hd(1)); + sc =3D ASPEED_SOC_GET_CLASS(soc); + aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART4, sc->uarts_base, + sc->uarts_num, serial_hd(1)); if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) { return false; } @@ -139,6 +143,7 @@ static bool ast2700fc_ssp_init(MachineState *machine, E= rror **errp) static bool ast2700fc_tsp_init(MachineState *machine, Error **errp) { AspeedSoCState *soc; + AspeedSoCClass *sc; Ast2700FCState *s =3D AST2700A1FC(machine); s->tsp_sysclk =3D clock_new(OBJECT(s), "TSP_SYSCLK"); clock_set_hz(s->tsp_sysclk, 200000000ULL); @@ -152,7 +157,9 @@ static bool ast2700fc_tsp_init(MachineState *machine, E= rror **errp) OBJECT(&s->tsp_memory), &error_abort); =20 soc =3D ASPEED_SOC(&s->tsp); - aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART7, serial_hd(2)); + sc =3D ASPEED_SOC_GET_CLASS(soc); + aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base, + sc->uarts_num, serial_hd(2)); if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) { return false; } diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index a4e74acdce77..ddcbba0020ee 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -59,15 +59,15 @@ bool aspeed_soc_uart_realize(AspeedSoCState *s, Error *= *errp) return true; } =20 -void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr) +void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base, + int uarts_num, Chardev *chr) { - AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); - int uart_first =3D aspeed_uart_first(sc->uarts_base); + int uart_first =3D aspeed_uart_first(uarts_base); int uart_index =3D aspeed_uart_index(dev); int i =3D uart_index - uart_first; =20 - g_assert(0 <=3D i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num); - qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); + g_assert(0 <=3D i && i < ASPEED_UARTS_NUM && i < uarts_num); + qdev_prop_set_chr(DEVICE(&uart[i]), "chardev", chr); } =20 /* diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c index c14fc2efe9bb..5a94c847d365 100644 --- a/hw/arm/fby35.c +++ b/hw/arm/fby35.c @@ -71,9 +71,11 @@ static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, M= emoryRegion *mr, static void fby35_bmc_init(Fby35State *s) { AspeedSoCState *soc; + AspeedSoCClass *sc; =20 object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3"); soc =3D ASPEED_SOC(&s->bmc); + sc =3D ASPEED_SOC_GET_CLASS(soc); =20 memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory", UINT64_MAX); @@ -91,7 +93,8 @@ static void fby35_bmc_init(Fby35State *s) &error_abort); object_property_set_int(OBJECT(&s->bmc), "hw-strap2", 0x00000003, &error_abort); - aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(0)); + aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART5, sc->uarts_base, + sc->uarts_num, serial_hd(0)); qdev_realize(DEVICE(&s->bmc), NULL, &error_abort); =20 aspeed_board_init_flashes(&soc->fmc, "n25q00", 2, 0); @@ -118,12 +121,14 @@ static void fby35_bmc_init(Fby35State *s) static void fby35_bic_init(Fby35State *s) { AspeedSoCState *soc; + AspeedSoCClass *sc; =20 s->bic_sysclk =3D clock_new(OBJECT(s), "SYSCLK"); clock_set_hz(s->bic_sysclk, 200000000ULL); =20 object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1"); soc =3D ASPEED_SOC(&s->bic); + sc =3D ASPEED_SOC_GET_CLASS(soc); =20 memory_region_init(&s->bic_memory, OBJECT(&s->bic), "bic-memory", UINT64_MAX); @@ -131,7 +136,8 @@ static void fby35_bic_init(Fby35State *s) qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk); object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_mem= ory), &error_abort); - aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(1)); + aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART5, sc->uarts_base, + sc->uarts_num, serial_hd(1)); qdev_realize(DEVICE(&s->bic), NULL, &error_abort); =20 aspeed_board_init_flashes(&soc->fmc, "sst25vf032b", 2, 2); --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1760360109; cv=none; d=zohomail.com; s=zohoarc; b=Tqs6isgrKEbd52TN0W4Xqrzmtp9ZobSFH6g/+wBKkN2QlPX2Dtpl2e5GCzYOxd4TG9pLo2qGTP2UMH/9W4jPKlY+bBiSh9R5rGJlAiT/YFjv8c4/SjgyXcx7irSy/nAqa9i+1tek0VN0PoZzvt0xJtZ+S5r4MK10QkFmmlEhPeM= ARC-Message-Signature: i=1; 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Mon, 13 Oct 2025 12:44:58 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.225.105]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 68E8C1800446; Mon, 13 Oct 2025 12:44:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359503; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UEdbp2eXeKKamlc+9pxois55NeQtijMnAB2hMYnvI08=; b=ci0ikWKDawtde/78HCMp3R8I3iJxo7NxrTD+GnZh5jQgdmSyFwUtVhkLw8vH6nPvRI0rv+ xE5oVkbnq3FXz+RhPepX1lhRLJ6lZHmsmDNsfZIHl1KTPYucwq656TcB1MqtV3YmDrJfCU 0y/hUv//jWx+V6TnREhtdNYhwVFZlXg= X-MC-Unique: Z4Bl88HUNj2ZG0HBgRW6qA-1 X-Mimecast-MFC-AGG-ID: Z4Bl88HUNj2ZG0HBgRW6qA_1760359499 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 17/29] hw/arm/aspeed: Remove AspeedSoCClass dependency from aspeed_soc_cpu_type() API Date: Mon, 13 Oct 2025 14:44:08 +0200 Message-ID: <20251013124421.71977-18-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760360111385154100 From: Jamin Lin Refactor the aspeed_soc_cpu_type() helper to remove its dependency on AspeedSoCClass and make CPU type retrieval more generic. The function now takes valid_cpu_types as a const char * const * parameter instead of requiring a full AspeedSoCClass instance. All corresponding call sites in various Aspeed SoC initialization files (aspeed_ast10x0.c, aspeed_ast2400.c, aspeed_ast2600.c, aspeed_ast27x0.c, and related variants) are updated accordingly. This change simplifies the API, eliminates unnecessary type coupling, and improves code reusability across different SoC families. No functional change. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-5-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 3 +-- hw/arm/aspeed_ast10x0.c | 3 ++- hw/arm/aspeed_ast2400.c | 2 +- hw/arm/aspeed_ast2600.c | 2 +- hw/arm/aspeed_ast27x0-ssp.c | 3 ++- hw/arm/aspeed_ast27x0-tsp.c | 3 ++- hw/arm/aspeed_ast27x0.c | 2 +- hw/arm/aspeed_soc_common.c | 10 +++++----- 8 files changed, 15 insertions(+), 13 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index c870bf55865e..385b657b5096 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -202,8 +202,6 @@ struct AspeedSoCClass { bool (*boot_from_emmc)(AspeedSoCState *s); }; =20 -const char *aspeed_soc_cpu_type(AspeedSoCClass *sc); - enum { ASPEED_DEV_VBOOTROM, ASPEED_DEV_SPI_BOOT, @@ -304,6 +302,7 @@ enum { ASPEED_DEV_IPC1, }; =20 +const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base, diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index c446e70b24a9..dab012aa953d 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -211,7 +211,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) /* AST1030 CPU Core */ armv7m =3D DEVICE(&a->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 256); - qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc)); + qdev_prop_set_string(armv7m, "cpu-type", + aspeed_soc_cpu_type(sc->valid_cpu_types)); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); object_property_set_link(OBJECT(&a->armv7m), "memory", OBJECT(s->memory), &error_abort); diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index c7b0f21887b5..53c2a5156dd5 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -157,7 +157,7 @@ static void aspeed_ast2400_soc_init(Object *obj) =20 for (i =3D 0; i < sc->num_cpus; i++) { object_initialize_child(obj, "cpu[*]", &a->cpu[i], - aspeed_soc_cpu_type(sc)); + aspeed_soc_cpu_type(sc->valid_cpu_types)); } =20 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 03e5df96bb4f..0299d9792918 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -167,7 +167,7 @@ static void aspeed_soc_ast2600_init(Object *obj) =20 for (i =3D 0; i < sc->num_cpus; i++) { object_initialize_child(obj, "cpu[*]", &a->cpu[i], - aspeed_soc_cpu_type(sc)); + aspeed_soc_cpu_type(sc->valid_cpu_types)); } =20 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 80ec5996c1d1..490e98b924df 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -174,7 +174,8 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *= dev_soc, Error **errp) /* AST27X0 SSP Core */ armv7m =3D DEVICE(&a->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 256); - qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc)); + qdev_prop_set_string(armv7m, "cpu-type", + aspeed_soc_cpu_type(sc->valid_cpu_types)); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); object_property_set_link(OBJECT(&a->armv7m), "memory", OBJECT(s->memory), &error_abort); diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 4e0efaef07c0..d83f90ef00ce 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -174,7 +174,8 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *= dev_soc, Error **errp) /* AST27X0 TSP Core */ armv7m =3D DEVICE(&a->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 256); - qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc)); + qdev_prop_set_string(armv7m, "cpu-type", + aspeed_soc_cpu_type(sc->valid_cpu_types)); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); object_property_set_link(OBJECT(&a->armv7m), "memory", OBJECT(s->memory), &error_abort); diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 853339119ff6..2f018e9e588a 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -436,7 +436,7 @@ static void aspeed_soc_ast2700_init(Object *obj) =20 for (i =3D 0; i < sc->num_cpus; i++) { object_initialize_child(obj, "cpu[*]", &a->cpu[i], - aspeed_soc_cpu_type(sc)); + aspeed_soc_cpu_type(sc->valid_cpu_types)); } =20 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index ddcbba0020ee..16c7c4bb78d4 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -22,12 +22,12 @@ #include "qemu/datadir.h" =20 =20 -const char *aspeed_soc_cpu_type(AspeedSoCClass *sc) +const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types) { - assert(sc->valid_cpu_types); - assert(sc->valid_cpu_types[0]); - assert(!sc->valid_cpu_types[1]); - return sc->valid_cpu_types[0]; + assert(valid_cpu_types); + assert(valid_cpu_types[0]); + assert(!valid_cpu_types[1]); + return valid_cpu_types[0]; } =20 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1760359609; cv=none; d=zohomail.com; s=zohoarc; b=YUV2V7BGHaPSe2CUs+USCV2/Ds4TYQarrgMAg0k9z0DU6dwfrUB1xr2WDEX94Rn/DQizEOmCpj8eLaruHtS1dbOTwS55OlXIP6o6Sy4LL5bTOY4xizxKKyoiR2TVpZ9RzZtvqecCQTarg27Dwss4uP39UK3mex3Vr7kpTO5iqQo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760359609; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 13 Oct 2025 12:44:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359505; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=44LG9gRX1yYjCPty+caKSlORbFjlHp1hjLiAApQ0Evo=; b=IWojAQSXJpYPKTTJfUCt+WmWoNgRBl6pBtiKaxasB/q6x+O62Q46VotNOcVYmjjC34RXH9 EfvZBqE3dYzvxJ9mJqCLRpeHx0zcPF83+7GfgqNGn5Li40rRjM0zuCY5h+Tf6TcOtZvOZf jyvpxnWqNvC0j5eBJHV4xu0CQ6nGkDo= X-MC-Unique: xJ-5lJ2UMbWbNkEWwAOVRA-1 X-Mimecast-MFC-AGG-ID: xJ-5lJ2UMbWbNkEWwAOVRA_1760359501 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 18/29] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_mmio_map() API Date: Mon, 13 Oct 2025 14:44:09 +0200 Message-ID: <20251013124421.71977-19-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359611442154100 From: Jamin Lin Refactor aspeed_mmio_map() to take MemoryRegion * instead of AspeedSoCState *, making the MMIO mapping helper more generic and decoupled from SoC state. Update all call sites to pass s->memory (or equivalent) explicitly. Touched files include: headers, aspeed_soc_common.c, and SoC realize paths in AST10x0/2400/2600/27x0 (SSP/TSP) and AST2700. This reduces coupling, improves reuse across variants, and clarifies the API boundary between SoC state and memory mapping. No functional change. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-6-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 3 +- hw/arm/aspeed_ast10x0.c | 37 ++++++++++++--------- hw/arm/aspeed_ast2400.c | 47 +++++++++++++++------------ hw/arm/aspeed_ast2600.c | 65 +++++++++++++++++++++---------------- hw/arm/aspeed_ast27x0-ssp.c | 7 ++-- hw/arm/aspeed_ast27x0-tsp.c | 7 ++-- hw/arm/aspeed_ast27x0.c | 60 +++++++++++++++++++--------------- hw/arm/aspeed_soc_common.c | 8 ++--- 8 files changed, 133 insertions(+), 101 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 385b657b5096..606cf6bb6193 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -308,7 +308,8 @@ bool aspeed_soc_uart_realize(AspeedSoCState *s, Error *= *errp); void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base, int uarts_num, Chardev *chr); bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); -void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr a= ddr); +void aspeed_mmio_map(MemoryRegion *memory, SysBusDevice *dev, int n, + hwaddr addr); void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, const char *name, hwaddr addr, uint64_t size); diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index dab012aa953d..caa9feb667ec 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -242,7 +242,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_S= CU]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0, + sc->memmap[ASPEED_DEV_SCU]); =20 /* I2C */ =20 @@ -251,7 +252,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I= 2C]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0, + sc->memmap[ASPEED_DEV_I2C]); for (i =3D 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { qemu_irq irq =3D qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[ASPEED_DEV_I2C] + i); @@ -263,7 +265,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I= 3C]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i3c), 0, + sc->memmap[ASPEED_DEV_I3C]); for (i =3D 0; i < ASPEED_I3C_NR_DEVICES; i++) { qemu_irq irq =3D qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[ASPEED_DEV_I3C] + i); @@ -275,7 +278,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0, sc->memmap[ASPEED_DEV_PECI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); @@ -284,7 +287,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_L= PC]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->lpc), 0, + sc->memmap[ASPEED_DEV_LPC]); =20 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, @@ -320,7 +324,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0, sc->memmap[ASPEED_DEV_TIMER1]); for (i =3D 0; i < ASPEED_TIMER_NR_TIMERS; i++) { qemu_irq irq =3D aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); @@ -331,7 +335,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_A= DC]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0, + sc->memmap[ASPEED_DEV_ADC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); =20 @@ -341,8 +346,9 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_F= MC]); - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0, + sc->memmap[ASPEED_DEV_FMC]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1, ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); @@ -354,9 +360,9 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0, sc->memmap[ASPEED_DEV_SPI1 + i]); - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1, ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_bas= e); } =20 @@ -364,7 +370,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_S= BC]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sbc), 0, + sc->memmap[ASPEED_DEV_SBC]); =20 /* HACE */ object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram), @@ -372,7 +379,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); @@ -387,14 +394,14 @@ static void aspeed_soc_ast1030_realize(DeviceState *d= ev_soc, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offs= et); } =20 /* GPIO */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index 53c2a5156dd5..669075221581 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -289,13 +289,15 @@ static void aspeed_ast2400_soc_realize(DeviceState *d= ev, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_S= CU]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0, + sc->memmap[ASPEED_DEV_SCU]); =20 /* VIC */ if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_V= IC]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->vic), 0, + sc->memmap[ASPEED_DEV_VIC]); sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0, qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1, @@ -305,7 +307,8 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_R= TC]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->rtc), 0, + sc->memmap[ASPEED_DEV_RTC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); =20 @@ -315,7 +318,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0, sc->memmap[ASPEED_DEV_TIMER1]); for (i =3D 0; i < ASPEED_TIMER_NR_TIMERS; i++) { qemu_irq irq =3D aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); @@ -326,7 +329,8 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_A= DC]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0, + sc->memmap[ASPEED_DEV_ADC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); =20 @@ -341,7 +345,8 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I= 2C]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0, + sc->memmap[ASPEED_DEV_I2C]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, aspeed_soc_get_irq(s, ASPEED_DEV_I2C)); =20 @@ -349,7 +354,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0, sc->memmap[ASPEED_DEV_PECI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); @@ -360,8 +365,9 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_F= MC]); - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0, + sc->memmap[ASPEED_DEV_FMC]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1, ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); @@ -377,9 +383,9 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0, sc->memmap[ASPEED_DEV_SPI1 + i]); - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1, ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_bas= e); } =20 @@ -388,7 +394,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ehci[i]), 0, sc->memmap[ASPEED_DEV_EHCI1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); @@ -398,7 +404,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); =20 /* Watch dog */ @@ -411,7 +417,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offs= et); } =20 /* RAM */ @@ -426,7 +432,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, sc->memmap[ASPEED_DEV_ETH1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); @@ -436,7 +442,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->xdma), 0, sc->memmap[ASPEED_DEV_XDMA]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); @@ -445,7 +451,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); @@ -454,7 +460,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdhci), 0, sc->memmap[ASPEED_DEV_SDHCI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); @@ -463,7 +469,8 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_L= PC]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->lpc), 0, + sc->memmap[ASPEED_DEV_LPC]); =20 /* Connect the LPC IRQ to the VIC */ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, @@ -496,7 +503,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 0299d9792918..bf0ecde0514b 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -324,7 +324,7 @@ static bool aspeed_soc_ast2600_pcie_realize(DeviceState= *dev, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy[0]), errp)) { return false; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie_phy[0]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->pcie_phy[0]), 0, sc->memmap[ASPEED_DEV_PCIE_PHY1]); =20 object_property_set_int(OBJECT(&s->pcie[0]), "dram-base", @@ -335,7 +335,7 @@ static bool aspeed_soc_ast2600_pcie_realize(DeviceState= *dev, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie[0]), errp)) { return false; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie[0]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->pcie[0]), 0, sc->memmap[ASPEED_DEV_PCIE0]); =20 irq =3D qdev_get_gpio_in(DEVICE(&a->a7mpcore), @@ -414,7 +414,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) &error_abort); =20 sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort); - aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_AD= DR); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->a7mpcore), 0, + ASPEED_A7MPCORE_ADDR); =20 for (i =3D 0; i < sc->num_cpus; i++) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(&a->a7mpcore); @@ -448,13 +449,15 @@ static void aspeed_soc_ast2600_realize(DeviceState *d= ev, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_S= CU]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0, + sc->memmap[ASPEED_DEV_SCU]); =20 /* RTC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_R= TC]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->rtc), 0, + sc->memmap[ASPEED_DEV_RTC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); =20 @@ -464,7 +467,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0, sc->memmap[ASPEED_DEV_TIMER1]); for (i =3D 0; i < ASPEED_TIMER_NR_TIMERS; i++) { irq =3D aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); @@ -475,7 +478,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_A= DC]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0, + sc->memmap[ASPEED_DEV_ADC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); =20 @@ -490,7 +494,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I= 2C]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0, + sc->memmap[ASPEED_DEV_I2C]); for (i =3D 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { irq =3D qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[ASPEED_DEV_I2C] + i); @@ -502,7 +507,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0, sc->memmap[ASPEED_DEV_PECI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); @@ -518,8 +523,9 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_F= MC]); - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0, + sc->memmap[ASPEED_DEV_FMC]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1, ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); @@ -537,9 +543,9 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0, sc->memmap[ASPEED_DEV_SPI1 + i]); - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1, ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_bas= e); } =20 @@ -548,7 +554,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ehci[i]), 0, sc->memmap[ASPEED_DEV_EHCI1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); @@ -558,7 +564,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); =20 /* Watch dog */ @@ -571,7 +577,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offs= et); } =20 /* RAM */ @@ -586,7 +592,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, sc->memmap[ASPEED_DEV_ETH1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); @@ -597,7 +603,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) return; } =20 - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->mii[i]), 0, sc->memmap[ASPEED_DEV_MII1 + i]); } =20 @@ -605,7 +611,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->xdma), 0, sc->memmap[ASPEED_DEV_XDMA]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); @@ -614,7 +620,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); @@ -622,7 +628,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio_1_8v), 0, sc->memmap[ASPEED_DEV_GPIO_1_8V]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); @@ -631,7 +637,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdhci), 0, sc->memmap[ASPEED_DEV_SDHCI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); @@ -640,7 +646,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); @@ -649,7 +655,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_L= PC]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->lpc), 0, + sc->memmap[ASPEED_DEV_LPC]); =20 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, @@ -685,7 +692,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); @@ -694,7 +701,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I= 3C]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i3c), 0, + sc->memmap[ASPEED_DEV_I3C]); for (i =3D 0; i < ASPEED_I3C_NR_DEVICES; i++) { irq =3D qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[ASPEED_DEV_I3C] + i); @@ -706,14 +714,15 @@ static void aspeed_soc_ast2600_realize(DeviceState *d= ev, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_S= BC]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sbc), 0, + sc->memmap[ASPEED_DEV_SBC]); =20 /* FSI */ for (i =3D 0; i < ASPEED_FSI_NUM; i++) { if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[i]), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fsi[i]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fsi[i]), 0, sc->memmap[ASPEED_DEV_FSI1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fsi[i]), 0, aspeed_soc_get_irq(s, ASPEED_DEV_FSI1 + i)); diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 490e98b924df..83cf3c14b6c3 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -196,14 +196,15 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState= *dev_soc, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_S= CU]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0, + sc->memmap[ASPEED_DEV_SCU]); =20 /* INTC */ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { return; } =20 - aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[0]), 0, sc->memmap[ASPEED_DEV_INTC]); =20 /* INTCIO */ @@ -211,7 +212,7 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *= dev_soc, Error **errp) return; } =20 - aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0, sc->memmap[ASPEED_DEV_INTCIO]); =20 /* irq source orgates -> INTC0 */ diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index d83f90ef00ce..86aa56560898 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -196,14 +196,15 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState= *dev_soc, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_S= CU]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0, + sc->memmap[ASPEED_DEV_SCU]); =20 /* INTC */ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { return; } =20 - aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[0]), 0, sc->memmap[ASPEED_DEV_INTC]); =20 /* INTCIO */ @@ -211,7 +212,7 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *= dev_soc, Error **errp) return; } =20 - aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0, sc->memmap[ASPEED_DEV_INTCIO]); =20 /* irq source orgates -> INTC */ diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 2f018e9e588a..8db67dc806ac 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -589,9 +589,9 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState = *dev, Error **errp) return false; } =20 - aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->gic), 0, sc->memmap[ASPEED_GIC_DIST]); - aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 1, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->gic), 1, sc->memmap[ASPEED_GIC_REDIST]); =20 for (i =3D 0; i < sc->num_cpus; i++) { @@ -647,7 +647,7 @@ static bool aspeed_soc_ast2700_pcie_realize(DeviceState= *dev, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy[i]), errp)) { return false; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie_phy[i]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->pcie_phy[i]), 0, sc->memmap[ASPEED_DEV_PCIE_PHY0 + i]); =20 object_property_set_int(OBJECT(&s->pcie[i]), "dram-base", @@ -658,7 +658,7 @@ static bool aspeed_soc_ast2700_pcie_realize(DeviceState= *dev, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie[i]), errp)) { return false; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie[i]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->pcie[i]), 0, sc->memmap[ASPEED_DEV_PCIE0 + i]); irq =3D aspeed_soc_get_irq(s, ASPEED_DEV_PCIE0 + i); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie[i].rc), 0, irq); @@ -719,7 +719,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) return; } =20 - aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[0]), 0, sc->memmap[ASPEED_DEV_INTC]); =20 /* INTCIO */ @@ -727,7 +727,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) return; } =20 - aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0, sc->memmap[ASPEED_DEV_INTCIO]); =20 /* irq sources -> orgates -> INTC */ @@ -777,13 +777,14 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_S= CU]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0, + sc->memmap[ASPEED_DEV_SCU]); =20 /* SCU1 */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scuio), 0, sc->memmap[ASPEED_DEV_SCUIO]); =20 /* UART */ @@ -800,8 +801,9 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_F= MC]); - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0, + sc->memmap[ASPEED_DEV_FMC]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1, ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); @@ -819,9 +821,9 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0, sc->memmap[ASPEED_DEV_SPI0 + i]); - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1, ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_bas= e); } =20 @@ -830,7 +832,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ehci[i]), 0, sc->memmap[ASPEED_DEV_EHCI1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); @@ -848,7 +850,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); =20 /* RAM */ @@ -865,7 +867,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, sc->memmap[ASPEED_DEV_ETH1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); @@ -876,7 +878,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) return; } =20 - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->mii[i]), 0, sc->memmap[ASPEED_DEV_MII1 + i]); } =20 @@ -890,26 +892,28 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offs= et); } =20 /* SLI */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_S= LI]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sli), 0, + sc->memmap[ASPEED_DEV_SLI]); =20 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sliio), 0, sc->memmap[ASPEED_DEV_SLIIO]); =20 /* ADC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_A= DC]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0, + sc->memmap[ASPEED_DEV_ADC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); =20 @@ -919,7 +923,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I= 2C]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0, + sc->memmap[ASPEED_DEV_I2C]); for (i =3D 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { /* * The AST2700 I2C controller has one source INTC per bus. @@ -948,7 +953,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); @@ -957,7 +962,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_R= TC]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->rtc), 0, + sc->memmap[ASPEED_DEV_RTC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); =20 @@ -965,7 +971,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdhci), 0, sc->memmap[ASPEED_DEV_SDHCI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); @@ -974,7 +980,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); @@ -985,7 +991,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0, sc->memmap[ASPEED_DEV_TIMER1]); for (i =3D 0; i < ASPEED_TIMER_NR_TIMERS; i++) { irq =3D aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); @@ -998,7 +1004,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { return; } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index 16c7c4bb78d4..ca4e589dce85 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -53,7 +53,7 @@ bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **e= rrp) } =20 sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, u= art)); - aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]); + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart= ]); } =20 return true; @@ -111,10 +111,10 @@ bool aspeed_soc_dram_init(AspeedSoCState *s, Error **= errp) return true; } =20 -void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr a= ddr) +void aspeed_mmio_map(MemoryRegion *memory, SysBusDevice *dev, int n, + hwaddr addr) { - memory_region_add_subregion(s->memory, addr, - sysbus_mmio_get_region(dev, n)); + memory_region_add_subregion(memory, addr, sysbus_mmio_get_region(dev, = n)); } =20 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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bh=vOzTP/IGNoBBnnYrqRH1AZrDTpQKJs1urmCGz64xytk=; b=dwAKB+s/1qRdL2RYpwcZQ+W1QL5YaLaq8KmB1KISZf3s8a7ZGE1axUSBalrZcqzVlh+Dk+ 7VMBR5oyjkk37asUdK+QOa3jOSDmEBM0dvJwNrTEZT1UA5o9/kU1vmgsSdCuYlHPa/DlrP az9ie5vqx0QOCqX9Y0a7ROgf+QHQp+w= X-MC-Unique: 5sGmlVFgMKiyiv1dtANBKA-1 X-Mimecast-MFC-AGG-ID: 5sGmlVFgMKiyiv1dtANBKA_1760359503 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 19/29] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_mmio_map_unimplemented() API Date: Mon, 13 Oct 2025 14:44:10 +0200 Message-ID: <20251013124421.71977-20-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359919182158500 From: Jamin Lin Refactor aspeed_mmio_map_unimplemented() to take MemoryRegion * instead of AspeedSoCState *, removing its dependency on SoC state and aligning it with the updated aspeed_mmio_map() interface. All related call sites are updated to explicitly pass s->memory. Affected files include headers, aspeed_soc_common.c, and SoC realize functions in AST10x0, AST2400, AST2600, AST27x0 (SSP/TSP), and AST2700. This change simplifies the MMIO mapping helpers, improves API consistency, and reduces coupling between SoC logic and memory operations. No functional change. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-7-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 2 +- hw/arm/aspeed_ast10x0.c | 24 ++++++++++++++++-------- hw/arm/aspeed_ast2400.c | 6 ++++-- hw/arm/aspeed_ast2600.c | 12 ++++++++---- hw/arm/aspeed_ast27x0-ssp.c | 8 ++++---- hw/arm/aspeed_ast27x0-tsp.c | 8 ++++---- hw/arm/aspeed_ast27x0.c | 10 +++++----- hw/arm/aspeed_soc_common.c | 4 ++-- 8 files changed, 44 insertions(+), 30 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 606cf6bb6193..957362b88d06 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -310,7 +310,7 @@ void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, i= nt uarts_base, bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); void aspeed_mmio_map(MemoryRegion *memory, SysBusDevice *dev, int n, hwaddr addr); -void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, +void aspeed_mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev, const char *name, hwaddr addr, uint64_t size); void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index caa9feb667ec..e861b6dad699 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -201,10 +201,12 @@ static void aspeed_soc_ast1030_realize(DeviceState *d= ev_soc, Error **errp) } =20 /* General I/O memory space to catch all unimplemented device */ - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io= ", + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem), + "aspeed.io", sc->memmap[ASPEED_DEV_IOMEM], ASPEED_SOC_IOMEM_SIZE); - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sbc_unimplemented), + aspeed_mmio_map_unimplemented(s->memory, + SYS_BUS_DEVICE(&s->sbc_unimplemented), "aspeed.sbc", sc->memmap[ASPEED_DEV_SBC], 0x40000); =20 @@ -406,20 +408,26 @@ static void aspeed_soc_ast1030_realize(DeviceState *d= ev_soc, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); =20 - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->pwm), "aspeed.pwm", + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->pwm), + "aspeed.pwm", sc->memmap[ASPEED_DEV_PWM], 0x100); =20 - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->espi), "aspeed.esp= i", + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->espi), + "aspeed.espi", sc->memmap[ASPEED_DEV_ESPI], 0x800); =20 - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->udc), "aspeed.udc", + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->udc), + "aspeed.udc", sc->memmap[ASPEED_DEV_UDC], 0x1000); - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sgpiom), "aspeed.s= gpiom", + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->sgpiom), + "aspeed.sgpiom", sc->memmap[ASPEED_DEV_SGPIOM], 0x100); =20 - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.= jtag", + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[0]), + "aspeed.jtag", sc->memmap[ASPEED_DEV_JTAG0], 0x20); - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.= jtag", + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[1]), + "aspeed.jtag", sc->memmap[ASPEED_DEV_JTAG1], 0x20); } =20 diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index 669075221581..e0604851a558 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -259,12 +259,14 @@ static void aspeed_ast2400_soc_realize(DeviceState *d= ev, Error **errp) &s->spi_boot_container); =20 /* IO space */ - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io= ", + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem), + "aspeed.io", sc->memmap[ASPEED_DEV_IOMEM], ASPEED_SOC_IOMEM_SIZE); =20 /* Video engine stub */ - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.vi= deo", + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->video), + "aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], 0x1000); =20 /* CPU */ diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index bf0ecde0514b..ed0985a16e08 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -370,16 +370,19 @@ static void aspeed_soc_ast2600_realize(DeviceState *d= ev, Error **errp) &s->spi_boot_container); =20 /* IO space */ - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io= ", + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem), + "aspeed.io", sc->memmap[ASPEED_DEV_IOMEM], ASPEED_SOC_IOMEM_SIZE); =20 /* Video engine stub */ - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.vi= deo", + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->video), + "aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], 0x1000); =20 /* eMMC Boot Controller stub */ - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controll= er), + aspeed_mmio_map_unimplemented(s->memory, + SYS_BUS_DEVICE(&s->emmc_boot_controller), "aspeed.emmc-boot-controller", sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000); =20 @@ -441,7 +444,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) sc->memmap[ASPEED_DEV_SRAM], &s->sram); =20 /* DPMCU */ - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dp= mcu", + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), + "aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], ASPEED_SOC_DPMCU_SIZE); =20 diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 83cf3c14b6c3..99a3de15b56c 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -241,16 +241,16 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState= *dev_soc, Error **errp) return; } =20 - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->timerctrl), + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl), "aspeed.timerctrl", sc->memmap[ASPEED_DEV_TIMER1], 0x200); - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[0]), + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[0]), "aspeed.ipc0", sc->memmap[ASPEED_DEV_IPC0], 0x1000); - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[1]), + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[1]), "aspeed.ipc1", sc->memmap[ASPEED_DEV_IPC1], 0x1000); - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->scuio), + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->scuio), "aspeed.scuio", sc->memmap[ASPEED_DEV_SCUIO], 0x1000); } diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 86aa56560898..568d7555e26e 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -241,16 +241,16 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState= *dev_soc, Error **errp) return; } =20 - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->timerctrl), + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl), "aspeed.timerctrl", sc->memmap[ASPEED_DEV_TIMER1], 0x200); - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[0]), + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[0]), "aspeed.ipc0", sc->memmap[ASPEED_DEV_IPC0], 0x1000); - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[1]), + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[1]), "aspeed.ipc1", sc->memmap[ASPEED_DEV_IPC1], 0x1000); - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->scuio), + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->scuio), "aspeed.scuio", sc->memmap[ASPEED_DEV_SCUIO], 0x1000); } diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 8db67dc806ac..9b645c6c5502 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -1014,23 +1014,23 @@ static void aspeed_soc_ast2700_realize(DeviceState = *dev, Error **errp) return; } =20 - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], AST2700_SOC_DPMCU_SIZE); - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->ltpi), + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->ltpi), "aspeed.ltpi", sc->memmap[ASPEED_DEV_LTPI], AST2700_SOC_LTPI_SIZE); - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", sc->memmap[ASPEED_DEV_IOMEM], AST2700_SOC_IO_SIZE); - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem0), + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem0), "aspeed.iomem0", sc->memmap[ASPEED_DEV_IOMEM0], AST2700_SOC_IOMEM_SIZE); - aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem1), + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem1), "aspeed.iomem1", sc->memmap[ASPEED_DEV_IOMEM1], AST2700_SOC_IOMEM_SIZE); diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index ca4e589dce85..e7d0a9c2909a 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -117,14 +117,14 @@ void aspeed_mmio_map(MemoryRegion *memory, SysBusDevi= ce *dev, int n, memory_region_add_subregion(memory, addr, sysbus_mmio_get_region(dev, = n)); } =20 -void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, +void aspeed_mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev, const char *name, hwaddr addr, uint64_t= size) { qdev_prop_set_string(DEVICE(dev), "name", name); qdev_prop_set_uint64(DEVICE(dev), "size", size); sysbus_realize(dev, &error_abort); =20 - memory_region_add_subregion_overlap(s->memory, addr, + memory_region_add_subregion_overlap(memory, addr, sysbus_mmio_get_region(dev, 0), -1= 000); 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359508; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jdcuTtv3GtelBi1Eyq/x52H6yVAK2KRf0s4RoIRaUOI=; b=felo8vql4GBQDkcoJAYPcj97pZY/vRfvV40Nsq+B6HClrc0Kjr3lBjnHxOoggbT8FAg7NF EZBLuCPrVfCFpSuR5leo62TYTLdgIS4w563DpmWCuiinc0GfeUQXQCyUqooy1qT0NGVIhj 9bZIDq/gtRmhtN8d7SGZBPRY2U/iD4U= X-MC-Unique: tmCOMAeOOP2A9HvjP-UTAw-1 X-Mimecast-MFC-AGG-ID: tmCOMAeOOP2A9HvjP-UTAw_1760359505 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 20/29] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_soc_uart_realize() API Date: Mon, 13 Oct 2025 14:44:11 +0200 Message-ID: <20251013124421.71977-21-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359674344158500 From: Jamin Lin Refactor aspeed_soc_uart_realize() to take MemoryRegion *, SerialMM *, and MMIO base addr instead of AspeedSoCState *, decoupling the helper from SoC state and making it reusable per-UART. The helper now realizes a single UART instance and maps its MMIO. IRQ wiring and iteration over all UARTs are moved to callers. Update call sites in AST1030, AST2400, AST2600, AST27x0 SSP/TSP, and AST2700 to loop over UARTs, call the new helper, and connect IRQ via aspeed_soc_get_irq(). This simplifies the UART realize path and reduces cross-module coupling. No functional change. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-8-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 3 ++- hw/arm/aspeed_ast10x0.c | 10 ++++++++-- hw/arm/aspeed_ast2400.c | 10 ++++++++-- hw/arm/aspeed_ast2600.c | 10 ++++++++-- hw/arm/aspeed_ast27x0-ssp.c | 10 ++++++++-- hw/arm/aspeed_ast27x0-tsp.c | 10 ++++++++-- hw/arm/aspeed_ast27x0.c | 10 ++++++++-- hw/arm/aspeed_soc_common.c | 28 ++++++++++------------------ 8 files changed, 60 insertions(+), 31 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 957362b88d06..47341ea2fdbc 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -304,7 +304,8 @@ enum { =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); -bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); +bool aspeed_soc_uart_realize(MemoryRegion *memory, SerialMM *smm, + const hwaddr addr, Error **errp); void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base, int uarts_num, Chardev *chr); bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index e861b6dad699..ff781379c10e 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -192,6 +192,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); DeviceState *armv7m; Error *err =3D NULL; + int uart; int i; g_autofree char *sram_name =3D NULL; =20 @@ -316,8 +317,13 @@ static void aspeed_soc_ast1030_realize(DeviceState *de= v_soc, Error **errp) sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); =20 /* UART */ - if (!aspeed_soc_uart_realize(s, errp)) { - return; + for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { + if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], + sc->memmap[uart], errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + aspeed_soc_get_irq(s, uart)); } =20 /* Timer */ diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index e0604851a558..8d4d6564c7ad 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -251,6 +251,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) AspeedSoCState *s =3D ASPEED_SOC(dev); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); g_autofree char *sram_name =3D NULL; + int uart; =20 /* Default boot region (SPI memory or ROMs) */ memory_region_init(&s->spi_boot_container, OBJECT(s), @@ -337,8 +338,13 @@ static void aspeed_ast2400_soc_realize(DeviceState *de= v, Error **errp) aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); =20 /* UART */ - if (!aspeed_soc_uart_realize(s, errp)) { - return; + for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { + if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], + sc->memmap[uart], errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + aspeed_soc_get_irq(s, uart)); } =20 /* I2C */ diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index ed0985a16e08..f508bf53e71d 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -362,6 +362,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); qemu_irq irq; g_autofree char *sram_name =3D NULL; + int uart; =20 /* Default boot region (SPI memory or ROMs) */ memory_region_init(&s->spi_boot_container, OBJECT(s), @@ -488,8 +489,13 @@ static void aspeed_soc_ast2600_realize(DeviceState *de= v, Error **errp) aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); =20 /* UART */ - if (!aspeed_soc_uart_realize(s, errp)) { - return; + for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { + if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], + sc->memmap[uart], errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + aspeed_soc_get_irq(s, uart)); } =20 /* I2C */ diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 99a3de15b56c..7420ae04acb5 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -164,6 +164,7 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *= dev_soc, Error **errp) AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); DeviceState *armv7m; g_autofree char *sram_name =3D NULL; + int uart; int i; =20 if (!clock_has_source(s->sysclk)) { @@ -237,8 +238,13 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState = *dev_soc, Error **errp) qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i= )); } /* UART */ - if (!aspeed_soc_uart_realize(s, errp)) { - return; + for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { + if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], + sc->memmap[uart], errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + aspeed_soc_get_irq(s, uart)); } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl), diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 568d7555e26e..b764147a3313 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -164,6 +164,7 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *= dev_soc, Error **errp) AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); DeviceState *armv7m; g_autofree char *sram_name =3D NULL; + int uart; int i; =20 if (!clock_has_source(s->sysclk)) { @@ -237,8 +238,13 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState = *dev_soc, Error **errp) qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i= )); } /* UART */ - if (!aspeed_soc_uart_realize(s, errp)) { - return; + for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { + if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], + sc->memmap[uart], errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + aspeed_soc_get_irq(s, uart)); } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl), diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 9b645c6c5502..96882b875548 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -687,6 +687,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) AspeedINTCClass *icio =3D ASPEED_INTC_GET_CLASS(&a->intc[1]); g_autofree char *name =3D NULL; qemu_irq irq; + int uart; =20 /* Default boot region (SPI memory or ROMs) */ memory_region_init(&s->spi_boot_container, OBJECT(s), @@ -788,8 +789,13 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) sc->memmap[ASPEED_DEV_SCUIO]); =20 /* UART */ - if (!aspeed_soc_uart_realize(s, errp)) { - return; + for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { + if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], + sc->memmap[uart], errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + aspeed_soc_get_irq(s, uart)); } =20 /* FMC, The number of CS is set at the board level */ diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index e7d0a9c2909a..a785a50609e3 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -35,27 +35,19 @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); } =20 -bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp) +bool aspeed_soc_uart_realize(MemoryRegion *memory, SerialMM *smm, + const hwaddr addr, Error **errp) { - AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); - SerialMM *smm; - - for (int i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uar= t++) { - smm =3D &s->uart[i]; - - /* Chardev property is set by the machine. */ - qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); - qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400); - qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2); - qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIA= N); - if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) { - return false; - } - - sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, u= art)); - aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart= ]); + /* Chardev property is set by the machine. */ + qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); + qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400); + qdev_set_legacy_instance_id(DEVICE(smm), addr, 2); + qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); + if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) { + return false; } =20 + aspeed_mmio_map(memory, SYS_BUS_DEVICE(smm), 0, addr); return true; } =20 --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359509; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5o/vJ3ydAkHPLJRbEQZiCg6ffq7ezxLYdoSNJ4rD5GQ=; b=iDLvLHhB3JOGcLJuiZzB23Dv0QFV+KOgVR2gmcqgsyKvFvFTS2WlCoZ+bqfRs+Hs4Y4syX 4sGINe8V09Ctf193hoH+01JCKVTkubQN2HwqlLtO7r2zlS8uX0PZt2efVz5yW30O/+ppFB iWqhUYxH1p6fWYKMikZWWddkBCy0qNc= X-MC-Unique: SihiFNVwMw6CkcYjgCI8oA-1 X-Mimecast-MFC-AGG-ID: SihiFNVwMw6CkcYjgCI8oA_1760359507 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 21/29] hw/arm/aspeed: Remove the aspeed_soc_get_irq and class get_irq hook Date: Mon, 13 Oct 2025 14:44:12 +0200 Message-ID: <20251013124421.71977-22-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359633536154100 From: Jamin Lin Remove the the common aspeed_soc_get_irq. Call sites are updated to use the SoC-specific get_irq helpers directly (aspeed_soc_ast1030_get_irq(), _aspeed2400_get_irq(), _ast2600_get_irq(), _ast27x0ssp_get_irq(), _ast27x0tsp_get_irq(), and _ast2700_get_irq()) This makes the IRQ lookup explicit per-SoC and drops the exported API that depended on AspeedSoCState, reducing cross-module coupling in the common layer. No functional change. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-9-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 2 -- hw/arm/aspeed_ast10x0.c | 17 ++++++++--------- hw/arm/aspeed_ast2400.c | 31 +++++++++++++++---------------- hw/arm/aspeed_ast2600.c | 34 +++++++++++++++++----------------- hw/arm/aspeed_ast27x0-ssp.c | 3 +-- hw/arm/aspeed_ast27x0-tsp.c | 3 +-- hw/arm/aspeed_ast27x0.c | 27 +++++++++++++-------------- hw/arm/aspeed_soc_common.c | 5 ----- 8 files changed, 55 insertions(+), 67 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 47341ea2fdbc..0e07c079f0cf 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -198,7 +198,6 @@ struct AspeedSoCClass { const int *irqmap; const hwaddr *memmap; uint32_t num_cpus; - qemu_irq (*get_irq)(AspeedSoCState *s, int dev); bool (*boot_from_emmc)(AspeedSoCState *s); }; =20 @@ -303,7 +302,6 @@ enum { }; =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); -qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); bool aspeed_soc_uart_realize(MemoryRegion *memory, SerialMM *smm, const hwaddr addr, Error **errp); void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base, diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index ff781379c10e..7f49c13391be 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -284,7 +284,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0, sc->memmap[ASPEED_DEV_PECI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); + aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_PECI)); =20 /* LPC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { @@ -295,7 +295,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) =20 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); + aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_LPC)); =20 /* * On the AST1030 LPC subdevice IRQs are connected straight to the GIC. @@ -323,7 +323,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) return; } sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, - aspeed_soc_get_irq(s, uart)); + aspeed_soc_ast1030_get_irq(s, uart)); } =20 /* Timer */ @@ -335,7 +335,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0, sc->memmap[ASPEED_DEV_TIMER1]); for (i =3D 0; i < ASPEED_TIMER_NR_TIMERS; i++) { - qemu_irq irq =3D aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); + qemu_irq irq =3D aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_TIMER1 += i); sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); } =20 @@ -346,7 +346,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); + aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_ADC)); =20 /* FMC, The number of CS is set at the board level */ object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram), @@ -359,7 +359,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1, ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); + aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_FMC)); =20 /* SPI */ for (i =3D 0; i < sc->spis_num; i++) { @@ -390,7 +390,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); + aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_HACE)); =20 /* Watch dog */ for (i =3D 0; i < sc->wdts_num; i++) { @@ -412,7 +412,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); + aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_GPIO)); =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->pwm), "aspeed.pwm", @@ -463,7 +463,6 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *= klass, const void *data) sc->irqmap =3D aspeed_soc_ast1030_irqmap; sc->memmap =3D aspeed_soc_ast1030_memmap; sc->num_cpus =3D 1; - sc->get_irq =3D aspeed_soc_ast1030_get_irq; } =20 static const TypeInfo aspeed_soc_ast10x0_types[] =3D { diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index 8d4d6564c7ad..b1b826b7e0b1 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -313,7 +313,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); + aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_RTC)); =20 /* Timer */ object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), @@ -324,7 +324,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0, sc->memmap[ASPEED_DEV_TIMER1]); for (i =3D 0; i < ASPEED_TIMER_NR_TIMERS; i++) { - qemu_irq irq =3D aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); + qemu_irq irq =3D aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_TIMER1 += i); sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); } =20 @@ -335,7 +335,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); + aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_ADC)); =20 /* UART */ for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { @@ -344,7 +344,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) return; } sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, - aspeed_soc_get_irq(s, uart)); + aspeed_soc_ast2400_get_irq(s, uart)); } =20 /* I2C */ @@ -356,7 +356,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_I2C)); + aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_I2C)); =20 /* PECI */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { @@ -365,7 +365,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0, sc->memmap[ASPEED_DEV_PECI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); + aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_PECI)); =20 /* FMC, The number of CS is set at the board level */ object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), @@ -378,7 +378,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1, ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); + aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_FMC)); =20 /* Set up an alias on the FMC CE0 region (boot default) */ MemoryRegion *fmc0_mmio =3D &s->fmc.flashes[0].mmio; @@ -405,7 +405,8 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ehci[i]), 0, sc->memmap[ASPEED_DEV_EHCI1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); + aspeed_soc_ast2400_get_irq(s, + ASPEED_DEV_EHCI1 + i= )); } =20 /* SDMC - SDRAM Memory Controller */ @@ -443,7 +444,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, sc->memmap[ASPEED_DEV_ETH1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); + aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_ETH1 += i)); } =20 /* XDMA */ @@ -453,7 +454,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->xdma), 0, sc->memmap[ASPEED_DEV_XDMA]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); + aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_XDMA)); =20 /* GPIO */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { @@ -462,7 +463,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); + aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_GPIO)); =20 /* SDHCI */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { @@ -471,7 +472,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdhci), 0, sc->memmap[ASPEED_DEV_SDHCI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); + aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_SDHCI)); =20 /* LPC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { @@ -482,7 +483,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) =20 /* Connect the LPC IRQ to the VIC */ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); + aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_LPC)); =20 /* * On the AST2400 and AST2500 the one LPC IRQ is shared between all of= the @@ -514,7 +515,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); + aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_HACE)); } =20 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, const void *dat= a) @@ -542,7 +543,6 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *= oc, const void *data) sc->irqmap =3D aspeed_soc_ast2400_irqmap; sc->memmap =3D aspeed_soc_ast2400_memmap; sc->num_cpus =3D 1; - sc->get_irq =3D aspeed_soc_ast2400_get_irq; } =20 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, const void *dat= a) @@ -570,7 +570,6 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *= oc, const void *data) sc->irqmap =3D aspeed_soc_ast2500_irqmap; sc->memmap =3D aspeed_soc_ast2500_memmap; sc->num_cpus =3D 1; - sc->get_irq =3D aspeed_soc_ast2400_get_irq; } =20 static const TypeInfo aspeed_soc_ast2400_types[] =3D { diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index f508bf53e71d..498d1ecc078b 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -464,7 +464,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); + aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_RTC)); =20 /* Timer */ object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), @@ -475,7 +475,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0, sc->memmap[ASPEED_DEV_TIMER1]); for (i =3D 0; i < ASPEED_TIMER_NR_TIMERS; i++) { - irq =3D aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); + irq =3D aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_TIMER1 + i); sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); } =20 @@ -486,7 +486,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); + aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_ADC)); =20 /* UART */ for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { @@ -495,7 +495,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) return; } sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, - aspeed_soc_get_irq(s, uart)); + aspeed_soc_ast2600_get_irq(s, uart)); } =20 /* I2C */ @@ -520,7 +520,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0, sc->memmap[ASPEED_DEV_PECI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); + aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_PECI)); =20 /* PCIe Root Complex (RC) */ if (!aspeed_soc_ast2600_pcie_realize(dev, errp)) { @@ -538,7 +538,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1, ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); + aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_FMC)); =20 /* Set up an alias on the FMC CE0 region (boot default) */ MemoryRegion *fmc0_mmio =3D &s->fmc.flashes[0].mmio; @@ -567,7 +567,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ehci[i]), 0, sc->memmap[ASPEED_DEV_EHCI1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); + aspeed_soc_ast2600_get_irq(s, + ASPEED_DEV_EHCI1 + i= )); } =20 /* SDMC - SDRAM Memory Controller */ @@ -605,7 +606,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, sc->memmap[ASPEED_DEV_ETH1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); + aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_ETH1 += i)); =20 object_property_set_link(OBJECT(&s->mii[i]), "nic", OBJECT(&s->ftgmac100[i]), &error_abort); @@ -624,7 +625,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->xdma), 0, sc->memmap[ASPEED_DEV_XDMA]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); + aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_XDMA)); =20 /* GPIO */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { @@ -633,7 +634,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); + aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_GPIO)); =20 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { return; @@ -641,7 +642,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio_1_8v), 0, sc->memmap[ASPEED_DEV_GPIO_1_8V]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); + aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_GPIO_1_8V)= ); =20 /* SDHCI */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { @@ -650,7 +651,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdhci), 0, sc->memmap[ASPEED_DEV_SDHCI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); + aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_SDHCI)); =20 /* eMMC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { @@ -659,7 +660,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); + aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_EMMC)); =20 /* LPC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { @@ -670,7 +671,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) =20 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); + aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_LPC)); =20 /* * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. @@ -705,7 +706,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); + aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_HACE)); =20 /* I3C */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { @@ -735,7 +736,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fsi[i]), 0, sc->memmap[ASPEED_DEV_FSI1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fsi[i]), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_FSI1 + i)); + aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_FSI1 += i)); } } =20 @@ -771,7 +772,6 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *= oc, const void *data) sc->irqmap =3D aspeed_soc_ast2600_irqmap; sc->memmap =3D aspeed_soc_ast2600_memmap; sc->num_cpus =3D 2; - sc->get_irq =3D aspeed_soc_ast2600_get_irq; sc->boot_from_emmc =3D aspeed_soc_ast2600_boot_from_emmc; } =20 diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 7420ae04acb5..f90d14437291 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -244,7 +244,7 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *= dev_soc, Error **errp) return; } sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, - aspeed_soc_get_irq(s, uart)); + aspeed_soc_ast27x0ssp_get_irq(s, uart)); } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl), @@ -286,7 +286,6 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClas= s *klass, const void *dat sc->irqmap =3D aspeed_soc_ast27x0ssp_irqmap; sc->memmap =3D aspeed_soc_ast27x0ssp_memmap; sc->num_cpus =3D 1; - sc->get_irq =3D aspeed_soc_ast27x0ssp_get_irq; } =20 static const TypeInfo aspeed_soc_ast27x0ssp_types[] =3D { diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index b764147a3313..8643f8268347 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -244,7 +244,7 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *= dev_soc, Error **errp) return; } sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, - aspeed_soc_get_irq(s, uart)); + aspeed_soc_ast27x0tsp_get_irq(s, uart)); } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl), @@ -286,7 +286,6 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClas= s *klass, const void *dat sc->irqmap =3D aspeed_soc_ast27x0tsp_irqmap; sc->memmap =3D aspeed_soc_ast27x0tsp_memmap; sc->num_cpus =3D 1; - sc->get_irq =3D aspeed_soc_ast27x0tsp_get_irq; } =20 static const TypeInfo aspeed_soc_ast27x0tsp_types[] =3D { diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 96882b875548..c484bcd4e22f 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -660,7 +660,7 @@ static bool aspeed_soc_ast2700_pcie_realize(DeviceState= *dev, Error **errp) } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->pcie[i]), 0, sc->memmap[ASPEED_DEV_PCIE0 + i]); - irq =3D aspeed_soc_get_irq(s, ASPEED_DEV_PCIE0 + i); + irq =3D aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_PCIE0 + i); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie[i].rc), 0, irq); =20 mmio_mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pcie[i].rc),= 1); @@ -795,7 +795,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) return; } sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, - aspeed_soc_get_irq(s, uart)); + aspeed_soc_ast2700_get_irq(s, uart)); } =20 /* FMC, The number of CS is set at the board level */ @@ -812,7 +812,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1, ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_FMC)); =20 /* Set up an alias on the FMC CE0 region (boot default) */ MemoryRegion *fmc0_mmio =3D &s->fmc.flashes[0].mmio; @@ -841,7 +841,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ehci[i]), 0, sc->memmap[ASPEED_DEV_EHCI1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); + aspeed_soc_ast2700_get_irq(s, + ASPEED_DEV_EHCI1 + i= )); } =20 /* @@ -876,7 +877,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, sc->memmap[ASPEED_DEV_ETH1 + i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ETH1 += i)); =20 object_property_set_link(OBJECT(&s->mii[i]), "nic", OBJECT(&s->ftgmac100[i]), &error_abort); @@ -921,7 +922,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ADC)); =20 /* I2C */ object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), @@ -962,7 +963,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO)); =20 /* RTC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { @@ -971,7 +972,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_RTC)); =20 /* SDHCI */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { @@ -980,7 +981,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdhci), 0, sc->memmap[ASPEED_DEV_SDHCI]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_SDHCI)); =20 /* eMMC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { @@ -989,7 +990,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_EMMC)); =20 /* Timer */ object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), @@ -1000,7 +1001,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0, sc->memmap[ASPEED_DEV_TIMER1]); for (i =3D 0; i < ASPEED_TIMER_NR_TIMERS; i++) { - irq =3D aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); + irq =3D aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_TIMER1 + i); sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); } =20 @@ -1013,7 +1014,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, - aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_HACE)); =20 /* PCIe Root Complex (RC) */ if (!aspeed_soc_ast2700_pcie_realize(dev, errp)) { @@ -1068,7 +1069,6 @@ static void aspeed_soc_ast2700a0_class_init(ObjectCla= ss *oc, const void *data) sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast2700a0_irqmap; sc->memmap =3D aspeed_soc_ast2700_memmap; - sc->get_irq =3D aspeed_soc_ast2700_get_irq; } =20 static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *d= ata) @@ -1097,7 +1097,6 @@ static void aspeed_soc_ast2700a1_class_init(ObjectCla= ss *oc, const void *data) sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast2700a1_irqmap; sc->memmap =3D aspeed_soc_ast2700_memmap; - sc->get_irq =3D aspeed_soc_ast2700_get_irq; } =20 static const TypeInfo aspeed_soc_ast27x0_types[] =3D { diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index a785a50609e3..78b6ae18f87e 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -30,11 +30,6 @@ const char *aspeed_soc_cpu_type(const char * const *vali= d_cpu_types) return valid_cpu_types[0]; } =20 -qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) -{ - return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); -} - bool aspeed_soc_uart_realize(MemoryRegion *memory, SerialMM *smm, const hwaddr addr, Error **errp) { --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359513; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=H0QrLhBvqbk7rYuSeyggsaT9tykkvaYvB/E9Wk1LPEc=; b=NnsLVatxO0s7sL2VIRZu6RufXXcA2Aikmdil7p3TY+lT0G/a3efDNkxZr1D6+vuOnOxFzC JcIvFCaP42CaVMOOfoCjCHOC30vm7DubrD4IBPBmKf/UxqS4VV/BaXCW/0rZAmo9OoMDDH wfTGCFDqHcg6Io0Hti6Gu+bp4OM7pOk= X-MC-Unique: 5jQPuWBCMnOTVeJfpENnCg-1 X-Mimecast-MFC-AGG-ID: 5jQPuWBCMnOTVeJfpENnCg_1760359508 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 22/29] hw/arm/aspeed: Introduce AspeedCoprocessor class and base implementation Date: Mon, 13 Oct 2025 14:44:13 +0200 Message-ID: <20251013124421.71977-23-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359996039154100 From: Jamin Lin Add a new AspeedCoprocessor class that defines the foundational structure f= or ASPEED coprocessor models. This class encapsulates a base DeviceState with links to system memory, clock, and peripheral components such as SCU, SCUIO, Timer Controller, and UARTs. Introduce the corresponding implementation file aspeed_coprocessor_common.c, which provides the aspeed_coprocessor_realize() method, property registration, and QOM type registration. The class is mark= ed as abstract and intended to serve as a common base for specific coprocessor variants (e.g. SSP/TSP subsystems). This establishes a reusable and extensible framework for modeling ASPEED coprocessor devices. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-10-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_coprocessor.h | 44 ++++++++++++++++++++++++++ hw/arm/aspeed_coprocessor_common.c | 49 +++++++++++++++++++++++++++++ hw/arm/meson.build | 3 +- 3 files changed, 95 insertions(+), 1 deletion(-) create mode 100644 include/hw/arm/aspeed_coprocessor.h create mode 100644 hw/arm/aspeed_coprocessor_common.c diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h new file mode 100644 index 000000000000..793c7b1f8be9 --- /dev/null +++ b/include/hw/arm/aspeed_coprocessor.h @@ -0,0 +1,44 @@ +/* + * ASPEED Coprocessor + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef ASPEED_COPROCESSOR_H +#define ASPEED_COPROCESSOR_H + +#include "qom/object.h" +#include "hw/arm/aspeed_soc.h" + +struct AspeedCoprocessorState { + DeviceState parent; + + MemoryRegion *memory; + MemoryRegion sram; + Clock *sysclk; + + AspeedSCUState scu; + AspeedSCUState scuio; + AspeedTimerCtrlState timerctrl; + SerialMM uart[ASPEED_UARTS_NUM]; +}; + +#define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor" +OBJECT_DECLARE_TYPE(AspeedCoprocessorState, AspeedCoprocessorClass, + ASPEED_COPROCESSOR) + +struct AspeedCoprocessorClass { + DeviceClass parent_class; + + /** valid_cpu_types: NULL terminated array of a single CPU type. */ + const char * const *valid_cpu_types; + uint32_t silicon_rev; + const hwaddr *memmap; + const int *irqmap; + int uarts_base; + int uarts_num; +}; + +#endif /* ASPEED_COPROCESSOR_H */ diff --git a/hw/arm/aspeed_coprocessor_common.c b/hw/arm/aspeed_coprocessor= _common.c new file mode 100644 index 000000000000..8a94b44f07f2 --- /dev/null +++ b/hw/arm/aspeed_coprocessor_common.c @@ -0,0 +1,49 @@ +/* + * ASPEED Coprocessor + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "system/memory.h" +#include "hw/qdev-properties.h" +#include "hw/arm/aspeed_coprocessor.h" + +static void aspeed_coprocessor_realize(DeviceState *dev, Error **errp) +{ + AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(dev); + + if (!s->memory) { + error_setg(errp, "'memory' link is not set"); + return; + } +} + +static const Property aspeed_coprocessor_properties[] =3D { + DEFINE_PROP_LINK("memory", AspeedCoprocessorState, memory, + TYPE_MEMORY_REGION, MemoryRegion *), +}; + +static void aspeed_coprocessor_class_init(ObjectClass *oc, const void *dat= a) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D aspeed_coprocessor_realize; + device_class_set_props(dc, aspeed_coprocessor_properties); +} + +static const TypeInfo aspeed_coprocessor_types[] =3D { + { + .name =3D TYPE_ASPEED_COPROCESSOR, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(AspeedCoprocessorState), + .class_size =3D sizeof(AspeedCoprocessorClass), + .class_init =3D aspeed_coprocessor_class_init, + .abstract =3D true, + }, +}; + +DEFINE_TYPES(aspeed_coprocessor_types) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index dc68391305fe..56bdb88b1175 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -52,7 +52,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'fby35.c')) arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: = files( 'aspeed_ast27x0.c', - 'aspeed_ast27x0-fc.c',)) + 'aspeed_ast27x0-fc.c', + 'aspeed_coprocessor_common.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c')) arm_common_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c')) --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1760359606; cv=none; d=zohomail.com; s=zohoarc; b=B9EhWBlOrh1+Sca3s6VXWYwrTTiGSAvETML5OTvesJqWS7JWVzApKjIjlKJHlBe6U9mlvggnoa7q+dxi0DDY8Saf37Y3lXxVp8O1XV6l8ZPAbAAUeMYRWKKJUN2Xz5w+HGThpnOyS2no/kGW2koWaDHKpmzdIQmkCnGLrwd0U7c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760359606; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=oVAPHq5CeoKAkjbrrNqZPoiL/G46kzVCOd4OTh1ST/o=; b=kjT1UvpS25XVya39ehVwAPzXFlGozaUQuwf+MwtK02G557DGbwmD07dT2Tv+2d0ER9tVxTMJw6+5ZoFMQ1rpvQ5s1f8b8z5G7GkYOObor/CPksyeqY506vMDq9KQR1NmipRGsHwKIODo3bY1gC5Aj2BiLXjbLMzlyQkay0e/Nhg= ARC-Authentication-Results: i=1; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359513; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oVAPHq5CeoKAkjbrrNqZPoiL/G46kzVCOd4OTh1ST/o=; b=Ib8PLcjXBwk6MC/X1ZW4AMM9iiv3AyWSZdcMBpcMqIg0RhIMpq53GbaEWrPXsshizI+FGS YEQm/mkQVWmAPJ2BRws1WcF4Jk8IZ1h+E+PaQhuFhSdf1wWnDg+utBRSzwctj7F1M4cr7x 5E8pmLSUGCGB0cKeLxnfB8yf7vqXMRw= X-MC-Unique: zoWCPJzuOUaep4sK2keV7w-1 X-Mimecast-MFC-AGG-ID: zoWCPJzuOUaep4sK2keV7w_1760359510 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 23/29] hw/arm/aspeed_ast27x0-ssp: Make AST27x0 SSP inherit from AspeedCoprocessor instead of AspeedSoC Date: Mon, 13 Oct 2025 14:44:14 +0200 Message-ID: <20251013124421.71977-24-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359607449154100 From: Jamin Lin Refactor the AST27x0 SSP implementation to derive from the newly introduced AspeedCoprocessor base class rather than AspeedSoC. The AspeedSoC class contains many SoC-level fields and behaviors that are not applicable to coprocessor subsystems like SSP, leading to unnecessary coupling and code s= ize. This change moves the Aspeed27x0SSPSoCState structure definition into aspeed_coprocessor.h and updates related references in aspeed_ast27x0-ssp.c and aspeed_ast27x0-fc.c to use AspeedCoprocessorState and AspeedCoprocessorClass. Key updates include: - Replace inheritance from AspeedSoC -> AspeedCoprocessor. - Replace type casts and class access macros (ASPEED_SOC_*) with ASPEED_COPROCESSOR_*. This refactor improves modularity, reduces memory footprint, and prepares for future coprocessor variants to share a lighter-weight common base. No functional change. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-11-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_coprocessor.h | 12 ++++++++++++ include/hw/arm/aspeed_soc.h | 12 ------------ hw/arm/aspeed_ast27x0-fc.c | 10 +++++----- hw/arm/aspeed_ast27x0-ssp.c | 30 +++++++++++++---------------- hw/arm/meson.build | 2 +- 5 files changed, 31 insertions(+), 35 deletions(-) diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h index 793c7b1f8be9..901b8d8e249d 100644 --- a/include/hw/arm/aspeed_coprocessor.h +++ b/include/hw/arm/aspeed_coprocessor.h @@ -41,4 +41,16 @@ struct AspeedCoprocessorClass { int uarts_num; }; =20 +struct Aspeed27x0SSPSoCState { + AspeedCoprocessorState parent; + AspeedINTCState intc[2]; + UnimplementedDeviceState ipc[2]; + UnimplementedDeviceState scuio; + + ARMv7MState armv7m; +}; + +#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc" +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC) + #endif /* ASPEED_COPROCESSOR_H */ diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 0e07c079f0cf..a34ab986a9da 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -153,18 +153,6 @@ struct Aspeed10x0SoCState { ARMv7MState armv7m; }; =20 -struct Aspeed27x0SSPSoCState { - AspeedSoCState parent; - AspeedINTCState intc[2]; - UnimplementedDeviceState ipc[2]; - UnimplementedDeviceState scuio; - - ARMv7MState armv7m; -}; - -#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc" -OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC) - struct Aspeed27x0TSPSoCState { AspeedSoCState parent; AspeedINTCState intc[2]; diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index e598f57ca228..4315e8da98d2 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -21,7 +21,7 @@ #include "hw/loader.h" #include "hw/arm/boot.h" #include "hw/block/flash.h" - +#include "hw/arm/aspeed_coprocessor.h" =20 #define TYPE_AST2700A1FC MACHINE_TYPE_NAME("ast2700fc") OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700A1FC); @@ -115,8 +115,8 @@ static bool ast2700fc_ca35_init(MachineState *machine, = Error **errp) =20 static bool ast2700fc_ssp_init(MachineState *machine, Error **errp) { - AspeedSoCState *soc; - AspeedSoCClass *sc; + AspeedCoprocessorState *soc; + AspeedCoprocessorClass *sc; Ast2700FCState *s =3D AST2700A1FC(machine); s->ssp_sysclk =3D clock_new(OBJECT(s), "SSP_SYSCLK"); clock_set_hz(s->ssp_sysclk, 200000000ULL); @@ -129,8 +129,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, E= rror **errp) object_property_set_link(OBJECT(&s->ssp), "memory", OBJECT(&s->ssp_memory), &error_abort); =20 - soc =3D ASPEED_SOC(&s->ssp); - sc =3D ASPEED_SOC_GET_CLASS(soc); + soc =3D ASPEED_COPROCESSOR(&s->ssp); + sc =3D ASPEED_COPROCESSOR_GET_CLASS(soc); aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART4, sc->uarts_base, sc->uarts_num, serial_hd(1)); if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) { diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index f90d14437291..1ebf06299ebe 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -14,6 +14,7 @@ #include "hw/qdev-clock.h" #include "hw/misc/unimp.h" #include "hw/arm/aspeed_soc.h" +#include "hw/arm/aspeed_coprocessor.h" =20 #define AST2700_SSP_RAM_SIZE (32 * MiB) =20 @@ -104,10 +105,11 @@ static struct nvic_intc_irq_info ast2700_ssp_intcmap[= ] =3D { {136, 0, 9, NULL}, }; =20 -static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedSoCState *s, int dev) +static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedCoprocessorState *s, + int dev) { Aspeed27x0SSPSoCState *a =3D ASPEED27X0SSP_SOC(s); - AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); =20 int or_idx; int idx; @@ -129,8 +131,8 @@ static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedSoC= State *s, int dev) static void aspeed_soc_ast27x0ssp_init(Object *obj) { Aspeed27x0SSPSoCState *a =3D ASPEED27X0SSP_SOC(obj); - AspeedSoCState *s =3D ASPEED_SOC(obj); - AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(obj); + AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); int i; =20 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); @@ -160,8 +162,8 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj) static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **er= rp) { Aspeed27x0SSPSoCState *a =3D ASPEED27X0SSP_SOC(dev_soc); - AspeedSoCState *s =3D ASPEED_SOC(dev_soc); - AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(dev_soc); + AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); DeviceState *armv7m; g_autofree char *sram_name =3D NULL; int uart; @@ -185,8 +187,8 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *= dev_soc, Error **errp) sram_name =3D g_strdup_printf("aspeed.dram.%d", CPU(a->armv7m.cpu)->cpu_index); =20 - if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_s= ize, - errp)) { + if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, + AST2700_SSP_RAM_SIZE, errp)) { return; } memory_region_add_subregion(s->memory, @@ -268,30 +270,24 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectCl= ass *klass, const void *dat NULL }; DeviceClass *dc =3D DEVICE_CLASS(klass); - AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(dc); + AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_CLASS(dc); =20 - /* Reason: The Aspeed SoC can only be instantiated from a board */ + /* Reason: The Aspeed Coprocessor can only be instantiated from a boar= d */ dc->user_creatable =3D false; dc->realize =3D aspeed_soc_ast27x0ssp_realize; =20 sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2700_A1_SILICON_REV; - sc->sram_size =3D AST2700_SSP_RAM_SIZE; - sc->spis_num =3D 0; - sc->ehcis_num =3D 0; - sc->wdts_num =3D 0; - sc->macs_num =3D 0; sc->uarts_num =3D 13; sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast27x0ssp_irqmap; sc->memmap =3D aspeed_soc_ast27x0ssp_memmap; - sc->num_cpus =3D 1; } =20 static const TypeInfo aspeed_soc_ast27x0ssp_types[] =3D { { .name =3D TYPE_ASPEED27X0SSP_SOC, - .parent =3D TYPE_ASPEED_SOC, + .parent =3D TYPE_ASPEED_COPROCESSOR, .instance_size =3D sizeof(Aspeed27x0SSPSoCState), .instance_init =3D aspeed_soc_ast27x0ssp_init, .class_init =3D aspeed_soc_ast27x0ssp_class_init, diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 56bdb88b1175..b9e02ace7f21 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -45,7 +45,6 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_soc_common.c', 'aspeed_ast2400.c', 'aspeed_ast2600.c', - 'aspeed_ast27x0-ssp.c', 'aspeed_ast27x0-tsp.c', 'aspeed_ast10x0.c', 'aspeed_eeprom.c', @@ -53,6 +52,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: = files( 'aspeed_ast27x0.c', 'aspeed_ast27x0-fc.c', + 'aspeed_ast27x0-ssp.c', 'aspeed_coprocessor_common.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c')) --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359516; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Q0LvuA57nsJx9pozIuJq8uO8/r70MHckSmhaUCVU4Yk=; b=GXNtHvjMPwijmsCtvQYheDil1JZdXNuT1XSZJ7J4InfhiB+UVvz9pDg+IkNC6v1c+wcKX2 Rc5qdBch1tbDJj59J35kDiIy0kk81TDK+DB9bI2D3LnJogqz71+AjszRP3fKO4XcoJ4bg/ /wAcX4iFZKrHEB7waxrTyOrEcvc4p2M= X-MC-Unique: _fUKWa54PPCpkzrTuCjHcA-1 X-Mimecast-MFC-AGG-ID: _fUKWa54PPCpkzrTuCjHcA_1760359512 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 24/29] hw/arm/aspeed_ast27x0-tsp: Make AST27x0 TSP inherit from AspeedCoprocessor instead of AspeedSoC Date: Mon, 13 Oct 2025 14:44:15 +0200 Message-ID: <20251013124421.71977-25-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359741225158500 From: Jamin Lin Refactor the AST27x0 TSP implementation to derive from the newly introduced AspeedCoprocessor base class rather than AspeedSoC. The AspeedSoC class includes SoC-level infrastructure and peripheral definitions that are not applicable to lightweight coprocessor subsystems such as TSP, resulting in unnecessary coupling and complexity. This change moves the Aspeed27x0TSPSoCState structure definition into aspeed_coprocessor.h and updates all related references in aspeed_ast27x0-tsp.c and aspeed_ast27x0-fc.c to use AspeedCoprocessorState and AspeedCoprocessorClass. Key updates include: - Replace inheritance from AspeedSoC -> AspeedCoprocessor. - Update type casts and macros from ASPEED_SOC_* to ASPEED_COPROCESSOR_* This refactor improves modularity, reduces memory footprint, and prepares for future coprocessor variants to share a lighter-weight common base. No functional change. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-12-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_coprocessor.h | 12 ++++++++++++ include/hw/arm/aspeed_soc.h | 12 ------------ hw/arm/aspeed_ast27x0-fc.c | 8 ++++---- hw/arm/aspeed_ast27x0-tsp.c | 30 +++++++++++++---------------- hw/arm/meson.build | 2 +- 5 files changed, 30 insertions(+), 34 deletions(-) diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h index 901b8d8e249d..f09c2ed267b2 100644 --- a/include/hw/arm/aspeed_coprocessor.h +++ b/include/hw/arm/aspeed_coprocessor.h @@ -53,4 +53,16 @@ struct Aspeed27x0SSPSoCState { #define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc" OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC) =20 +struct Aspeed27x0TSPSoCState { + AspeedCoprocessorState parent; + AspeedINTCState intc[2]; + UnimplementedDeviceState ipc[2]; + UnimplementedDeviceState scuio; + + ARMv7MState armv7m; +}; + +#define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc" +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0TSPSoCState, ASPEED27X0TSP_SOC) + #endif /* ASPEED_COPROCESSOR_H */ diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index a34ab986a9da..4b8e599f1a53 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -153,18 +153,6 @@ struct Aspeed10x0SoCState { ARMv7MState armv7m; }; =20 -struct Aspeed27x0TSPSoCState { - AspeedSoCState parent; - AspeedINTCState intc[2]; - UnimplementedDeviceState ipc[2]; - UnimplementedDeviceState scuio; - - ARMv7MState armv7m; -}; - -#define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc" -OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0TSPSoCState, ASPEED27X0TSP_SOC) - #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc" OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC) =20 diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index 4315e8da98d2..b34cd54e4e7f 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -142,8 +142,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, E= rror **errp) =20 static bool ast2700fc_tsp_init(MachineState *machine, Error **errp) { - AspeedSoCState *soc; - AspeedSoCClass *sc; + AspeedCoprocessorState *soc; + AspeedCoprocessorClass *sc; Ast2700FCState *s =3D AST2700A1FC(machine); s->tsp_sysclk =3D clock_new(OBJECT(s), "TSP_SYSCLK"); clock_set_hz(s->tsp_sysclk, 200000000ULL); @@ -156,8 +156,8 @@ static bool ast2700fc_tsp_init(MachineState *machine, E= rror **errp) object_property_set_link(OBJECT(&s->tsp), "memory", OBJECT(&s->tsp_memory), &error_abort); =20 - soc =3D ASPEED_SOC(&s->tsp); - sc =3D ASPEED_SOC_GET_CLASS(soc); + soc =3D ASPEED_COPROCESSOR(&s->tsp); + sc =3D ASPEED_COPROCESSOR_GET_CLASS(soc); aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base, sc->uarts_num, serial_hd(2)); if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) { diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 8643f8268347..b77c5291a6d5 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -14,6 +14,7 @@ #include "hw/qdev-clock.h" #include "hw/misc/unimp.h" #include "hw/arm/aspeed_soc.h" +#include "hw/arm/aspeed_coprocessor.h" =20 #define AST2700_TSP_RAM_SIZE (32 * MiB) =20 @@ -104,10 +105,11 @@ static struct nvic_intc_irq_info ast2700_tsp_intcmap[= ] =3D { {136, 0, 9, NULL}, }; =20 -static qemu_irq aspeed_soc_ast27x0tsp_get_irq(AspeedSoCState *s, int dev) +static qemu_irq aspeed_soc_ast27x0tsp_get_irq(AspeedCoprocessorState *s, + int dev) { Aspeed27x0TSPSoCState *a =3D ASPEED27X0TSP_SOC(s); - AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); =20 int or_idx; int idx; @@ -129,8 +131,8 @@ static qemu_irq aspeed_soc_ast27x0tsp_get_irq(AspeedSoC= State *s, int dev) static void aspeed_soc_ast27x0tsp_init(Object *obj) { Aspeed27x0TSPSoCState *a =3D ASPEED27X0TSP_SOC(obj); - AspeedSoCState *s =3D ASPEED_SOC(obj); - AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(obj); + AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); int i; =20 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); @@ -160,8 +162,8 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj) static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **er= rp) { Aspeed27x0TSPSoCState *a =3D ASPEED27X0TSP_SOC(dev_soc); - AspeedSoCState *s =3D ASPEED_SOC(dev_soc); - AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(dev_soc); + AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); DeviceState *armv7m; g_autofree char *sram_name =3D NULL; int uart; @@ -185,8 +187,8 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *= dev_soc, Error **errp) sram_name =3D g_strdup_printf("aspeed.dram.%d", CPU(a->armv7m.cpu)->cpu_index); =20 - if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_s= ize, - errp)) { + if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, + AST2700_TSP_RAM_SIZE, errp)) { return; } memory_region_add_subregion(s->memory, @@ -268,30 +270,24 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectCl= ass *klass, const void *dat NULL }; DeviceClass *dc =3D DEVICE_CLASS(klass); - AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(dc); + AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_CLASS(dc); =20 - /* Reason: The Aspeed SoC can only be instantiated from a board */ + /* Reason: The Aspeed Coprocessor can only be instantiated from a boar= d */ dc->user_creatable =3D false; dc->realize =3D aspeed_soc_ast27x0tsp_realize; =20 sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2700_A1_SILICON_REV; - sc->sram_size =3D AST2700_TSP_RAM_SIZE; - sc->spis_num =3D 0; - sc->ehcis_num =3D 0; - sc->wdts_num =3D 0; - sc->macs_num =3D 0; sc->uarts_num =3D 13; sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast27x0tsp_irqmap; sc->memmap =3D aspeed_soc_ast27x0tsp_memmap; - sc->num_cpus =3D 1; } =20 static const TypeInfo aspeed_soc_ast27x0tsp_types[] =3D { { .name =3D TYPE_ASPEED27X0TSP_SOC, - .parent =3D TYPE_ASPEED_SOC, + .parent =3D TYPE_ASPEED_COPROCESSOR, .instance_size =3D sizeof(Aspeed27x0TSPSoCState), .instance_init =3D aspeed_soc_ast27x0tsp_init, .class_init =3D aspeed_soc_ast27x0tsp_class_init, diff --git a/hw/arm/meson.build b/hw/arm/meson.build index b9e02ace7f21..b88b5b06d7ed 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -45,7 +45,6 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_soc_common.c', 'aspeed_ast2400.c', 'aspeed_ast2600.c', - 'aspeed_ast27x0-tsp.c', 'aspeed_ast10x0.c', 'aspeed_eeprom.c', 'fby35.c')) @@ -53,6 +52,7 @@ arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AAR= CH64'], if_true: files( 'aspeed_ast27x0.c', 'aspeed_ast27x0-fc.c', 'aspeed_ast27x0-ssp.c', + 'aspeed_ast27x0-tsp.c', 'aspeed_coprocessor_common.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c')) arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c')) --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359520; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dFF38vbJCcqoZ0VZSxZGGvoYn4TrbGzQbFCWQwTPafY=; b=bW/xyD+cshS4u+DXB89x3ftvYh/uryic8RCG/wGU7VrwKQW2w2wr4fcKdj3XQa4RCVU7Uz oBU+pA5Ej5yLNUrwjKzIeUJBdSEyJ9xsOMQLVa6eJUnMlPrpXBc9jgGlp6SQrLLJuyORcD iKm54B41/PGmg4xo3KBLYWPAjoD+3ao= X-MC-Unique: lfSNv7ogMjSCSs_8G8Yxmw-1 X-Mimecast-MFC-AGG-ID: lfSNv7ogMjSCSs_8G8Yxmw_1760359514 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 25/29] hw/arm/aspeed_ast27x0-ssp: Change to use Aspeed27x0CoprocessorState Date: Mon, 13 Oct 2025 14:44:16 +0200 Message-ID: <20251013124421.71977-26-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359942988154100 From: Jamin Lin Refactor the AST27x0 SSP implementation to use the unified Aspeed27x0CoprocessorState structure shared between SSP and TSP. Previously, SSP and TSP each defined separate state structures (Aspeed27x0SSPSoCState and Aspeed27x0TSPSoCState), which contained identical members and caused unnecessary code duplication. This change removes Aspeed27x0SSPSoCState and replaces it with Aspeed27x0CoprocessorState, consolidating shared coprocessor state fields into a single definition in aspeed_coprocessor.h. This refactor unifies SSP and TSP under the same coprocessor state type, improving code maintainability and consistency across Aspeed coprocessor implementations. No functional change. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-13-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_coprocessor.h | 4 ++-- hw/arm/aspeed_ast27x0-fc.c | 2 +- hw/arm/aspeed_ast27x0-ssp.c | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h index f09c2ed267b2..d799726635df 100644 --- a/include/hw/arm/aspeed_coprocessor.h +++ b/include/hw/arm/aspeed_coprocessor.h @@ -41,7 +41,7 @@ struct AspeedCoprocessorClass { int uarts_num; }; =20 -struct Aspeed27x0SSPSoCState { +struct Aspeed27x0CoprocessorState { AspeedCoprocessorState parent; AspeedINTCState intc[2]; UnimplementedDeviceState ipc[2]; @@ -51,7 +51,7 @@ struct Aspeed27x0SSPSoCState { }; =20 #define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc" -OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC) +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0CoprocessorState, ASPEED27X0SSP_SOC) =20 struct Aspeed27x0TSPSoCState { AspeedCoprocessorState parent; diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index b34cd54e4e7f..cd09a2dcf0b9 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -42,7 +42,7 @@ struct Ast2700FCState { Clock *tsp_sysclk; =20 Aspeed27x0SoCState ca35; - Aspeed27x0SSPSoCState ssp; + Aspeed27x0CoprocessorState ssp; Aspeed27x0TSPSoCState tsp; =20 bool mmio_exec; diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 1ebf06299ebe..f8319c95fd41 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -108,7 +108,7 @@ static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = =3D { static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedCoprocessorState *s, int dev) { - Aspeed27x0SSPSoCState *a =3D ASPEED27X0SSP_SOC(s); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0SSP_SOC(s); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); =20 int or_idx; @@ -130,7 +130,7 @@ static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedCop= rocessorState *s, =20 static void aspeed_soc_ast27x0ssp_init(Object *obj) { - Aspeed27x0SSPSoCState *a =3D ASPEED27X0SSP_SOC(obj); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0SSP_SOC(obj); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(obj); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); int i; @@ -161,7 +161,7 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj) =20 static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **er= rp) { - Aspeed27x0SSPSoCState *a =3D ASPEED27X0SSP_SOC(dev_soc); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0SSP_SOC(dev_soc); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(dev_soc); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); DeviceState *armv7m; @@ -288,7 +288,7 @@ static const TypeInfo aspeed_soc_ast27x0ssp_types[] =3D= { { .name =3D TYPE_ASPEED27X0SSP_SOC, .parent =3D TYPE_ASPEED_COPROCESSOR, - .instance_size =3D sizeof(Aspeed27x0SSPSoCState), + .instance_size =3D sizeof(Aspeed27x0CoprocessorState), .instance_init =3D aspeed_soc_ast27x0ssp_init, .class_init =3D aspeed_soc_ast27x0ssp_class_init, }, --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359520; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Or6ZwxCzNCRqQiPHosNcpwXZ04PMuqaCvZzLOBokGJ8=; b=FK5sOYCCEtDy97vWLTxYQ7r7HGPbVbWS5QtQfQsF8ZEfujW0YNVOytb57SFHFBbLWI6IFI Ouq2xJ4fDqktUzmCq6Spk+2I8zl3cmRpNb1Q3MIM39MafzIolXux2EOl9boZqTjKXviEcc d9iSpfNOHCwY1i8M6GBYv4oqnaeDlPk= X-MC-Unique: hjhl3ucfPNWRHP3_WLVZgA-1 X-Mimecast-MFC-AGG-ID: hjhl3ucfPNWRHP3_WLVZgA_1760359516 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 26/29] hw/arm/aspeed_ast27x0-tsp: Change to use Aspeed27x0CoprocessorState Date: Mon, 13 Oct 2025 14:44:17 +0200 Message-ID: <20251013124421.71977-27-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359650108158500 From: Jamin Lin Refactor the AST27x0 TSP implementation to use the unified Aspeed27x0CoprocessorState, matching the prior SSP change and removing the duplicated Aspeed27x0TSPSoCState. Key updates: - Delete Aspeed27x0TSPSoCState and reuse Aspeed27x0CoprocessorState. Update Ast2700FCState to declare tsp as Aspeed27x0CoprocessorState. This aligns TSP with SSP on a single coprocessor state type, reducing code duplication and simplifying maintenance. No functional change. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-14-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_coprocessor.h | 12 ++---------- hw/arm/aspeed_ast27x0-fc.c | 2 +- hw/arm/aspeed_ast27x0-tsp.c | 8 ++++---- 3 files changed, 7 insertions(+), 15 deletions(-) diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h index d799726635df..110e776c6202 100644 --- a/include/hw/arm/aspeed_coprocessor.h +++ b/include/hw/arm/aspeed_coprocessor.h @@ -53,16 +53,8 @@ struct Aspeed27x0CoprocessorState { #define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc" OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0CoprocessorState, ASPEED27X0SSP_SOC) =20 -struct Aspeed27x0TSPSoCState { - AspeedCoprocessorState parent; - AspeedINTCState intc[2]; - UnimplementedDeviceState ipc[2]; - UnimplementedDeviceState scuio; - - ARMv7MState armv7m; -}; - #define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc" -OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0TSPSoCState, ASPEED27X0TSP_SOC) +DECLARE_OBJ_CHECKERS(Aspeed27x0CoprocessorState, AspeedCoprocessorClass, + ASPEED27X0TSP_SOC, TYPE_ASPEED27X0TSP_SOC) =20 #endif /* ASPEED_COPROCESSOR_H */ diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index cd09a2dcf0b9..c2fa8df33ce4 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -43,7 +43,7 @@ struct Ast2700FCState { =20 Aspeed27x0SoCState ca35; Aspeed27x0CoprocessorState ssp; - Aspeed27x0TSPSoCState tsp; + Aspeed27x0CoprocessorState tsp; =20 bool mmio_exec; }; diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index b77c5291a6d5..e18c624361e2 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -108,7 +108,7 @@ static struct nvic_intc_irq_info ast2700_tsp_intcmap[] = =3D { static qemu_irq aspeed_soc_ast27x0tsp_get_irq(AspeedCoprocessorState *s, int dev) { - Aspeed27x0TSPSoCState *a =3D ASPEED27X0TSP_SOC(s); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_SOC(s); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); =20 int or_idx; @@ -130,7 +130,7 @@ static qemu_irq aspeed_soc_ast27x0tsp_get_irq(AspeedCop= rocessorState *s, =20 static void aspeed_soc_ast27x0tsp_init(Object *obj) { - Aspeed27x0TSPSoCState *a =3D ASPEED27X0TSP_SOC(obj); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_SOC(obj); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(obj); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); int i; @@ -161,7 +161,7 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj) =20 static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **er= rp) { - Aspeed27x0TSPSoCState *a =3D ASPEED27X0TSP_SOC(dev_soc); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_SOC(dev_soc); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(dev_soc); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); DeviceState *armv7m; @@ -288,7 +288,7 @@ static const TypeInfo aspeed_soc_ast27x0tsp_types[] =3D= { { .name =3D TYPE_ASPEED27X0TSP_SOC, .parent =3D TYPE_ASPEED_COPROCESSOR, - .instance_size =3D sizeof(Aspeed27x0TSPSoCState), + .instance_size =3D sizeof(Aspeed27x0CoprocessorState), .instance_init =3D aspeed_soc_ast27x0tsp_init, .class_init =3D aspeed_soc_ast27x0tsp_class_init, }, --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=fEUCGx+oUMjLbWrVPKVp1eS5UeVFKTbcYu+ni6eOEf0=; b=K9I5ushiEZp9SCU6lC75DpDlz+DjEbz1dUR2z5QftBfiQVCVJgHlaJL/32VYYCITpVMP34 iDJ7FBG17aNF6D+PPP1RGXxdL+YKltkiuabG/osftzSlwznpqzA0tzPXUI2fJM0IcdKzZe vMX8MPLNuNs61mGCXqz0V368MIKuYzg= X-MC-Unique: Qe660E9VNKKnPgzNox8wqA-1 X-Mimecast-MFC-AGG-ID: Qe660E9VNKKnPgzNox8wqA_1760359518 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 27/29] hw/arm/aspeed_ast27x0-ssp: Rename type to TYPE_ASPEED27X0SSP_COPROCESSOR Date: Mon, 13 Oct 2025 14:44:18 +0200 Message-ID: <20251013124421.71977-28-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359868416154100 From: Jamin Lin Rename the AST27x0 SSP type from TYPE_ASPEED27X0SSP_SOC to TYPE_ASPEED27X0SSP_COPROCESSOR to better reflect its role as a coprocessor rather than a standalone SoC. This aligns naming conventions with the coprocessor-based design introduced in earlier refactors. This change improves naming consistency across SSP and TSP coprocessor implementations and clarifies their relationship to the unified Aspeed27x0CoprocessorState. No functional change. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-15-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_coprocessor.h | 5 +++-- hw/arm/aspeed_ast27x0-fc.c | 3 ++- hw/arm/aspeed_ast27x0-ssp.c | 10 +++++----- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h index 110e776c6202..1c201a15c61c 100644 --- a/include/hw/arm/aspeed_coprocessor.h +++ b/include/hw/arm/aspeed_coprocessor.h @@ -50,8 +50,9 @@ struct Aspeed27x0CoprocessorState { ARMv7MState armv7m; }; =20 -#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc" -OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0CoprocessorState, ASPEED27X0SSP_SOC) +#define TYPE_ASPEED27X0SSP_COPROCESSOR "aspeed27x0ssp-coprocessor" +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0CoprocessorState, + ASPEED27X0SSP_COPROCESSOR) =20 #define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc" DECLARE_OBJ_CHECKERS(Aspeed27x0CoprocessorState, AspeedCoprocessorClass, diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index c2fa8df33ce4..67982d2fa073 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -121,7 +121,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, E= rror **errp) s->ssp_sysclk =3D clock_new(OBJECT(s), "SSP_SYSCLK"); clock_set_hz(s->ssp_sysclk, 200000000ULL); =20 - object_initialize_child(OBJECT(s), "ssp", &s->ssp, TYPE_ASPEED27X0SSP_= SOC); + object_initialize_child(OBJECT(s), "ssp", &s->ssp, + TYPE_ASPEED27X0SSP_COPROCESSOR); memory_region_init(&s->ssp_memory, OBJECT(&s->ssp), "ssp-memory", UINT64_MAX); =20 diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index f8319c95fd41..d27be8b92558 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -1,5 +1,5 @@ /* - * ASPEED Ast27x0 SSP SoC + * ASPEED Ast27x0 SSP Coprocessor * * Copyright (C) 2025 ASPEED Technology Inc. * @@ -108,7 +108,7 @@ static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = =3D { static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedCoprocessorState *s, int dev) { - Aspeed27x0CoprocessorState *a =3D ASPEED27X0SSP_SOC(s); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0SSP_COPROCESSOR(s); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); =20 int or_idx; @@ -130,7 +130,7 @@ static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedCop= rocessorState *s, =20 static void aspeed_soc_ast27x0ssp_init(Object *obj) { - Aspeed27x0CoprocessorState *a =3D ASPEED27X0SSP_SOC(obj); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0SSP_COPROCESSOR(obj); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(obj); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); int i; @@ -161,7 +161,7 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj) =20 static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **er= rp) { - Aspeed27x0CoprocessorState *a =3D ASPEED27X0SSP_SOC(dev_soc); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0SSP_COPROCESSOR(dev_soc); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(dev_soc); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); DeviceState *armv7m; @@ -286,7 +286,7 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClas= s *klass, const void *dat =20 static const TypeInfo aspeed_soc_ast27x0ssp_types[] =3D { { - .name =3D TYPE_ASPEED27X0SSP_SOC, + .name =3D TYPE_ASPEED27X0SSP_COPROCESSOR, .parent =3D TYPE_ASPEED_COPROCESSOR, .instance_size =3D sizeof(Aspeed27x0CoprocessorState), .instance_init =3D aspeed_soc_ast27x0ssp_init, --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359526; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2cu0/up0C34u6VgaT7VD1i2KSTdc2/ZHtKEWT6HqXxQ=; b=eQNunZV5pJCxAM4Z/H5X0kEDGjmsGwYgr1Vg1BjNG8EJGSH3ahqKsihf4NHclpjbdWMeNA dKrnWQHZ7V3G/uzT35T9KTmCuN3HGdN1VSjrFx4YKBLh0dptnWDNQYg3BYTtK4ZmEcZRak LS8uNg4ytkJbvQkKc3wCSb9Dgej1D+I= X-MC-Unique: oRYDNXCfP8at1-oAR7jTBA-1 X-Mimecast-MFC-AGG-ID: oRYDNXCfP8at1-oAR7jTBA_1760359520 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 28/29] hw/arm/aspeed_ast27x0-tsp: Rename type to TYPE_ASPEED27X0TSP_COPROCESSOR Date: Mon, 13 Oct 2025 14:44:19 +0200 Message-ID: <20251013124421.71977-29-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760360072840158500 From: Jamin Lin Rename the AST27x0 TSP type from TYPE_ASPEED27X0TSP_SOC to TYPE_ASPEED27X0TSP_COPROCESSOR to align with the naming convention used for the SSP coprocessor (TYPE_ASPEED27X0SSP_COPROCESSOR). This change clarifies that TSP is implemented as a coprocessor rather than a full SoC. This ensures consistent terminology between SSP and TSP components and improves clarity within the coprocessor subsystem code. No functional change. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-16-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_coprocessor.h | 4 ++-- hw/arm/aspeed_ast27x0-fc.c | 3 ++- hw/arm/aspeed_ast27x0-tsp.c | 10 +++++----- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h index 1c201a15c61c..d77655d65911 100644 --- a/include/hw/arm/aspeed_coprocessor.h +++ b/include/hw/arm/aspeed_coprocessor.h @@ -54,8 +54,8 @@ struct Aspeed27x0CoprocessorState { OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0CoprocessorState, ASPEED27X0SSP_COPROCESSOR) =20 -#define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc" +#define TYPE_ASPEED27X0TSP_COPROCESSOR "aspeed27x0tsp-coprocessor" DECLARE_OBJ_CHECKERS(Aspeed27x0CoprocessorState, AspeedCoprocessorClass, - ASPEED27X0TSP_SOC, TYPE_ASPEED27X0TSP_SOC) + ASPEED27X0TSP_COPROCESSOR, TYPE_ASPEED27X0TSP_COPROCE= SSOR) =20 #endif /* ASPEED_COPROCESSOR_H */ diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index 67982d2fa073..a61ecff3909b 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -149,7 +149,8 @@ static bool ast2700fc_tsp_init(MachineState *machine, E= rror **errp) s->tsp_sysclk =3D clock_new(OBJECT(s), "TSP_SYSCLK"); clock_set_hz(s->tsp_sysclk, 200000000ULL); =20 - object_initialize_child(OBJECT(s), "tsp", &s->tsp, TYPE_ASPEED27X0TSP_= SOC); + object_initialize_child(OBJECT(s), "tsp", &s->tsp, + TYPE_ASPEED27X0TSP_COPROCESSOR); memory_region_init(&s->tsp_memory, OBJECT(&s->tsp), "tsp-memory", UINT64_MAX); =20 diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index e18c624361e2..7f109101fe44 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -1,5 +1,5 @@ /* - * ASPEED Ast27x0 TSP SoC + * ASPEED Ast27x0 TSP Coprocessor * * Copyright (C) 2025 ASPEED Technology Inc. * @@ -108,7 +108,7 @@ static struct nvic_intc_irq_info ast2700_tsp_intcmap[] = =3D { static qemu_irq aspeed_soc_ast27x0tsp_get_irq(AspeedCoprocessorState *s, int dev) { - Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_SOC(s); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_COPROCESSOR(s); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); =20 int or_idx; @@ -130,7 +130,7 @@ static qemu_irq aspeed_soc_ast27x0tsp_get_irq(AspeedCop= rocessorState *s, =20 static void aspeed_soc_ast27x0tsp_init(Object *obj) { - Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_SOC(obj); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_COPROCESSOR(obj); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(obj); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); int i; @@ -161,7 +161,7 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj) =20 static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **er= rp) { - Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_SOC(dev_soc); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_COPROCESSOR(dev_soc); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(dev_soc); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); DeviceState *armv7m; @@ -286,7 +286,7 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClas= s *klass, const void *dat =20 static const TypeInfo aspeed_soc_ast27x0tsp_types[] =3D { { - .name =3D TYPE_ASPEED27X0TSP_SOC, + .name =3D TYPE_ASPEED27X0TSP_COPROCESSOR, .parent =3D TYPE_ASPEED_COPROCESSOR, .instance_size =3D sizeof(Aspeed27x0CoprocessorState), .instance_init =3D aspeed_soc_ast27x0tsp_init, --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1760359525; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eks63TMjKZKNnjepbaN7iti9g+iM+e9hGfP8R2I3juY=; b=cfBm/GdnQhI7iondbnmswDuSxbBLlY5IahowLj9acYGNCMitMjl26aswQcdZ+QcEKWQdXY Fmhp3Vzitxuypv3C36DPcq6AyO/jL+6kRhUaC1JI6ngb9oPeZJWEsTYYt3RDZeEiuvWkCh mxcnCttsbY3aHYiSLR1+XAeSYqiOtLE= X-MC-Unique: UmJ2drRZORiVqPhHhNeLhQ-1 X-Mimecast-MFC-AGG-ID: UmJ2drRZORiVqPhHhNeLhQ_1760359522 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 29/29] hw/arm/aspeed_ast27x0-{ssp,tsp}: Fix coding style Date: Mon, 13 Oct 2025 14:44:20 +0200 Message-ID: <20251013124421.71977-30-clg@redhat.com> In-Reply-To: <20251013124421.71977-1-clg@redhat.com> References: <20251013124421.71977-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1760359692033154100 From: Jamin Lin Fix coding style warnings in aspeed_ast27x0-ssp.c and aspeed_ast27x0-tsp.c reported by checkpatch.pl regarding line length exceeding 80 characters. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-17-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0-ssp.c | 3 ++- hw/arm/aspeed_ast27x0-tsp.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index d27be8b92558..936c7c72e8f7 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -263,7 +263,8 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *= dev_soc, Error **errp) sc->memmap[ASPEED_DEV_SCUIO], 0x1000); } =20 -static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass, const voi= d *data) +static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass, + const void *data) { static const char * const valid_cpu_types[] =3D { ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO: cortex-m4f */ diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 7f109101fe44..9318f8c86c51 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -263,7 +263,8 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *= dev_soc, Error **errp) sc->memmap[ASPEED_DEV_SCUIO], 0x1000); } =20 -static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass, const voi= d *data) +static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass, + const void *data) { static const char * const valid_cpu_types[] =3D { ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */ --=20 2.51.0