From nobody Fri Nov 14 19:47:02 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760282137754248.9313012765558; Sun, 12 Oct 2025 08:15:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v7xn0-0003Mf-Kt; Sun, 12 Oct 2025 11:15:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v7xmz-0003HH-3Q; Sun, 12 Oct 2025 11:15:13 -0400 Received: from sgoci-sdnproxy-4.icoremail.net ([129.150.39.64]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v7xmw-0002kc-IE; Sun, 12 Oct 2025 11:15:12 -0400 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-7 (Coremail) with SMTP id AQAAfwCHjZn5xetotligAA--.81S2; Sun, 12 Oct 2025 23:15:05 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwD3Wef4xetoZnhMAA--.2267S3; Sun, 12 Oct 2025 23:15:04 +0800 (CST) From: Tao Tang To: Eric Auger , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Philippe Brucker , Mostafa Saleh , Tao Tang Subject: [RFC v3 19/21] hw/arm/smmuv3: Use iommu_index to represent the security context Date: Sun, 12 Oct 2025 23:15:01 +0800 Message-Id: <20251012151501.4131026-1-tangtao1634@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251012150701.4127034-1-tangtao1634@phytium.com.cn> References: <20251012150701.4127034-1-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAfwD3Wef4xetoZnhMAA--.2267S3 X-CM-SenderInfo: pwdqw3tdrrljuu6sx5pwlxzhxfrphubq/1tbiAQABBWjqskUBdgAAsH Authentication-Results: hzbj-icmmx-7; spf=neutral smtp.mail=tangtao163 4@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvJXoWxZF1xWryxXr4fAFy3Aw4Utwb_yoW5CFWxpr 4UGa93Kws8GF1fZF1fJa1UZF4a9397GF43XrZ3Kan5Aw18Awn7XFZ2kFyYgryDAFWUAw42 vay0ka9rWa1qyrJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.150.39.64; envelope-from=tangtao1634@phytium.com.cn; helo=sgoci-sdnproxy-4.icoremail.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1760282149212158500 Content-Type: text/plain; charset="utf-8" The Arm SMMUv3 architecture uses a SEC_SID (Secure StreamID) to select the programming interface. To support future extensions like RME, which defines four security states (Non-secure, Secure, Realm, and Root), the QEMU model must cleanly separate these contexts for all operations. This commit leverages the generic iommu_index to represent this security context. The core IOMMU layer now uses the SMMU's .attrs_to_index callback to map a transaction's ARMSecuritySpace attribute to the corresponding iommu_index. This index is then passed down to smmuv3_translate and used throughout the model to select the correct register bank and processing logic. This makes the iommu_index the clear QEMU equivalent of the architectural SEC_SID, cleanly separating the contexts for all subsequent lookups. Signed-off-by: Tao Tang --- hw/arm/smmuv3.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index c9c742c80b..b44859540f 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1080,6 +1080,38 @@ static void smmuv3_fixup_event(SMMUEventInfo *event,= hwaddr iova) } } =20 +static SMMUSecSID smmuv3_attrs_to_sec_sid(MemTxAttrs attrs) +{ + switch (attrs.space) { + case ARMSS_Secure: + return SMMU_SEC_SID_S; + case ARMSS_NonSecure: + default: + return SMMU_SEC_SID_NS; + } +} + +/* + * ARM IOMMU index mapping (implements SEC_SID from ARM SMMU): + * iommu_idx =3D 0: Non-secure transactions + * iommu_idx =3D 1: Secure transactions + * + * The iommu_idx parameter effectively implements the SEC_SID + * (Security Stream ID) attribute from the ARM SMMU architecture specifica= tion, + * which allows the SMMU to differentiate between different security state + * transactions at the hardware level. + */ +static int smmuv3_attrs_to_index(IOMMUMemoryRegion *iommu, MemTxAttrs attr= s) +{ + return (int)smmuv3_attrs_to_sec_sid(attrs); +} + +static int smmuv3_num_indexes(IOMMUMemoryRegion *iommu) +{ + /* Support 2 IOMMU indexes for now: NS/S */ + return SMMU_SEC_SID_NUM; +} + /* Entry point to SMMU, does everything. */ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, IOMMUAccessFlags flag, int iommu_idx) @@ -1087,7 +1119,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegi= on *mr, hwaddr addr, SMMUDevice *sdev =3D container_of(mr, SMMUDevice, iommu); SMMUv3State *s =3D sdev->smmu; uint32_t sid =3D smmu_get_sid(sdev); - SMMUSecSID sec_sid =3D SMMU_SEC_SID_NS; + SMMUSecSID sec_sid =3D iommu_idx; SMMUv3RegBank *bank =3D smmuv3_bank(s, sec_sid); SMMUEventInfo event =3D {.type =3D SMMU_EVT_NONE, .sid =3D sid, @@ -2540,6 +2572,8 @@ static void smmuv3_iommu_memory_region_class_init(Obj= ectClass *klass, =20 imrc->translate =3D smmuv3_translate; imrc->notify_flag_changed =3D smmuv3_notify_flag_changed; + imrc->attrs_to_index =3D smmuv3_attrs_to_index; + imrc->num_indexes =3D smmuv3_num_indexes; } =20 static const TypeInfo smmuv3_type_info =3D { --=20 2.34.1