From nobody Fri Nov 14 19:47:01 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760281784864196.47435955882895; Sun, 12 Oct 2025 08:09:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v7xfm-0001kY-Nt; Sun, 12 Oct 2025 11:07:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v7xfR-0001eA-2I; Sun, 12 Oct 2025 11:07:25 -0400 Received: from sgoci-sdnproxy-4.icoremail.net ([129.150.39.64]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v7xfL-0001cp-Am; Sun, 12 Oct 2025 11:07:24 -0400 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-6 (Coremail) with SMTP id AQAAfwD31yQexOtocicrAA--.35250S2; Sun, 12 Oct 2025 23:07:10 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwDXPOoXxOto33dMAA--.3068S10; Sun, 12 Oct 2025 23:07:08 +0800 (CST) From: Tao Tang To: Eric Auger , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Philippe Brucker , Mostafa Saleh , Tao Tang Subject: [RFC v3 07/21] hw/arm/smmuv3: Track SEC_SID in configs and events Date: Sun, 12 Oct 2025 23:06:47 +0800 Message-Id: <20251012150701.4127034-8-tangtao1634@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251012150701.4127034-1-tangtao1634@phytium.com.cn> References: <20251012150701.4127034-1-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAfwDXPOoXxOto33dMAA--.3068S10 X-CM-SenderInfo: pwdqw3tdrrljuu6sx5pwlxzhxfrphubq/1tbiAQABBWjqskUBYAAAsR Authentication-Results: hzbj-icmmx-6; spf=neutral smtp.mail=tangtao163 4@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvJXoW3XrWkuF45tw1fAF18XrW3Awb_yoW7AFW7pw 1DGrn8Krn5ta4SvFy3XF4UZa13J3ykKrn8Kr9Fgr95Aws5urW7XF4DGa45ur98uryrtrW2 v3yIgFW5uFyjv3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.150.39.64; envelope-from=tangtao1634@phytium.com.cn; helo=sgoci-sdnproxy-4.icoremail.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1760281789303158500 Content-Type: text/plain; charset="utf-8" Cache the SEC_SID inside SMMUTransCfg to keep configuration lookups tied to the correct register bank. Plumb the SEC_SID through tracepoints and queue helpers so diagnostics and event logs always show which security interface emitted the record. To support this, the SEC_SID is placed in SMMUEventInfo so the bank is identified as soon as an event record is built. Signed-off-by: Tao Tang --- hw/arm/smmuv3-internal.h | 1 + hw/arm/smmuv3.c | 22 +++++++++++++++------- hw/arm/trace-events | 2 +- include/hw/arm/smmu-common.h | 1 + 4 files changed, 18 insertions(+), 8 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index af0e0b32b3..99fdbcf3f5 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -512,6 +512,7 @@ static inline const char *smmu_event_string(SMMUEventTy= pe type) =20 /* Encode an event record */ typedef struct SMMUEventInfo { + SMMUSecSID sec_sid; SMMUEventType type; uint32_t sid; bool recorded; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 6d05bb1310..a87ae36e8b 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -146,9 +146,9 @@ static MemTxResult queue_write(SMMUQueue *q, Evt *evt_i= n) return MEMTX_OK; } =20 -static MemTxResult smmuv3_write_eventq(SMMUv3State *s, Evt *evt) +static MemTxResult smmuv3_write_eventq(SMMUv3State *s, SMMUSecSID sec_sid, + Evt *evt) { - SMMUSecSID sec_sid =3D SMMU_SEC_SID_NS; SMMUv3RegBank *bank =3D smmuv3_bank(s, sec_sid); SMMUQueue *q =3D &bank->eventq; MemTxResult r; @@ -176,7 +176,10 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo= *info) { Evt evt =3D {}; MemTxResult r; - SMMUSecSID sec_sid =3D SMMU_SEC_SID_NS; + SMMUSecSID sec_sid =3D info->sec_sid; + if (sec_sid >=3D SMMU_SEC_SID_NUM) { + g_assert_not_reached(); + } =20 if (!smmuv3_eventq_enabled(s, sec_sid)) { return; @@ -256,8 +259,9 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo = *info) g_assert_not_reached(); } =20 - trace_smmuv3_record_event(smmu_event_string(info->type), info->sid); - r =3D smmuv3_write_eventq(s, &evt); + trace_smmuv3_record_event(sec_sid, smmu_event_string(info->type), + info->sid); + r =3D smmuv3_write_eventq(s, sec_sid, &evt); if (r !=3D MEMTX_OK) { smmuv3_trigger_irq(s, SMMU_IRQ_GERROR, R_GERROR_EVENTQ_ABT_ERR_MAS= K); } @@ -900,6 +904,7 @@ static SMMUTransCfg *smmuv3_get_config(SMMUDevice *sdev= , SMMUEventInfo *event) 100 * sdev->cfg_cache_hits / (sdev->cfg_cache_hits + sdev->cfg_cache_misses= )); cfg =3D g_new0(SMMUTransCfg, 1); + cfg->sec_sid =3D SMMU_SEC_SID_NS; =20 if (!smmuv3_decode_config(&sdev->iommu, cfg, event)) { g_hash_table_insert(bc->configs, sdev, cfg); @@ -1057,7 +1062,8 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegi= on *mr, hwaddr addr, SMMUv3RegBank *bank =3D smmuv3_bank(s, sec_sid); SMMUEventInfo event =3D {.type =3D SMMU_EVT_NONE, .sid =3D sid, - .inval_ste_allowed =3D false}; + .inval_ste_allowed =3D false, + .sec_sid =3D sec_sid}; SMMUTranslationStatus status; SMMUTransCfg *cfg =3D NULL; IOMMUTLBEntry entry =3D { @@ -1159,7 +1165,9 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, uint64_t num_pages, int stage) { SMMUDevice *sdev =3D container_of(mr, SMMUDevice, iommu); - SMMUEventInfo eventinfo =3D {.inval_ste_allowed =3D true}; + SMMUSecSID sec_sid =3D SMMU_SEC_SID_NS; + SMMUEventInfo eventinfo =3D {.sec_sid =3D sec_sid, + .inval_ste_allowed =3D true}; SMMUTransCfg *cfg =3D smmuv3_get_config(sdev, &eventinfo); IOMMUTLBEvent event; uint8_t granule; diff --git a/hw/arm/trace-events b/hw/arm/trace-events index f3386bd7ae..96ebd1b11b 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -40,7 +40,7 @@ smmuv3_cmdq_opcode(const char *opcode) "<--- %s" smmuv3_cmdq_consume_out(uint32_t prod, uint32_t cons, uint8_t prod_wrap, u= int8_t cons_wrap) "prod:%d, cons:%d, prod_wrap:%d, cons_wrap:%d " smmuv3_cmdq_consume_error(const char *cmd_name, uint8_t cmd_error) "Error = on %s command execution: %d" smmuv3_write_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) = "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" -smmuv3_record_event(const char *type, uint32_t sid) "%s sid=3D0x%x" +smmuv3_record_event(int sec_sid, const char *type, uint32_t sid) "sec_sid= =3D%d %s sid=3D0x%x" smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) "sid= =3D0x%x features:0x%x, sid_split:0x%x" smmuv3_find_ste_2lvl(uint64_t strtab_base, uint64_t l1ptr, int l1_ste_offs= et, uint64_t l2ptr, int l2_ste_offset, int max_l2_ste) "strtab_base:0x%"PRI= x64" l1ptr:0x%"PRIx64" l1_off:0x%x, l2ptr:0x%"PRIx64" l2_off:0x%x max_l2_st= e:%d" smmuv3_get_ste(uint64_t addr) "STE addr: 0x%"PRIx64 diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 2dd6cfa895..b0dae18a62 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -107,6 +107,7 @@ typedef struct SMMUS2Cfg { typedef struct SMMUTransCfg { /* Shared fields between stage-1 and stage-2. */ SMMUStage stage; /* translation stage */ + SMMUSecSID sec_sid; /* cached sec sid */ bool disabled; /* smmu is disabled */ bool bypassed; /* translation is bypassed */ bool aborted; /* translation is aborted */ --=20 2.34.1