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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46fb55ac08dsm45452255e9.13.2025.10.10.08.50.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Oct 2025 08:50:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1760111452; x=1760716252; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PbZf/4lXCFUtVLVqfehR/2skaY6PUFbfsiZG7sUkFCE=; b=OI55x86LqEo74Lu/CE1hVZ51R54tFwIUBxO+GMplWQHwoCrrJ7iPtT4i2DHSKWEN7W k1BzY0YHf5oDV4UcEtnJBUb+d8GCRDrNeHq8Khg0Z/uUo7GTnCBJ9gGcvt/RiZL89RBi 9C9WbaG6mhDXq+pznqj3+13GQeGO+X+C+8FFckx/6iiRT4/JNkxbrjZ34R9M3sb/91R1 aXZR5mEOqb1EKVmQmFISWZPn1/um30aSwrwpzdE3OnDVyzyaQA59oEdaaAjzAyj6SGFC 8xiXZtJhwwlk4odO1qSqcMLEzSegeEjKSmKPe6MVFTDS6j8r0sBGVsS/NPXpIwDfcvLj S2bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760111452; x=1760716252; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PbZf/4lXCFUtVLVqfehR/2skaY6PUFbfsiZG7sUkFCE=; b=AtcVeRKkE8BsJhRDSt30FAzHqJV/nR7pJTRINykeHc3SUWFa6pg0Ok3UKXoAoONX/x Ncts6isTy8/QRD5u2DUb0P31cp8qpeUr9NBELTGZ+k2eDYuj8EOguw8IjoIvJIw3oBTL 177v16UgVbDC1vIO/VPIwPQNO7DjrQzO2qaL9jYBZMgLyKxnSCvzc/144sp6Vp9j9Knm XtV4FhZqVJNya5pOhet2TmWEnMvWzXfHTzg+xRp7GfA+3b6calJPvFY4pDh/jQdidssD tTmDlBb0odFxU/o0Vlexj40DPzSx2XNZc9qsX58LI9JLfKDpEhQ+pBigU/aZWT+7b/IM AJYQ== X-Gm-Message-State: AOJu0Yz58aIJcVofbTrhfuQu2A4SKVLiNja5OXwE6R5BQitbLG7a2AOV 2fvTJDwUl0aPQsVbZ+/jwZfvBBZigqKPMCZFJ5D1IMNRwlKWuf2lwAoOV/tJ/YJHoFaxL4i4kXF 7knlK7HXqig== X-Gm-Gg: ASbGnctgBwTotjyUcfkTG+NRVg1cSIHBZIQTb5ES1M+wUKdTVE2YWabti254jbpV/cS JgWXbqIe+AEJMToyJjQGLaqSmVLhGJ00RgngEJ0A4QiTzFzAxR7184q1xgmvbLWZINw4j26VZA7 Ial0gG/tpoWAR7TgJ7By0h6AjX11r2lgWyoTDZJ0hvbwIysvDb8eoZJASYFrpel6tJvo/Qw0gBj lScVND8L5GLEQbHV9QlEB6tlvUjcvmnqlIhT9EkAsim2CqlcKQGet5CvRcXor86dmcq5FUkoIE2 RR53XvrQd8UtsHkeYiTUQeTtUPV0QBRBnybMGGfV9RWGSOO2LW0Ht9nSRRLVIfVbe2L8L0onahS 12+WRZvgfCF89Z412EMZ6crFcxx5utjlEB885qcUrOJN112J/UJT9y2mxeLHbl5/Szj3fgkAyOd AmHB4P2wEwTKDlkUop0BQ= X-Google-Smtp-Source: AGHT+IFec6tJzjkxLlLlFEt9D93P56h780sUOKmKiYIRaBVsCLtJOjjOVVGcddk5slz4ufCRS09q2Q== X-Received: by 2002:a5d:588c:0:b0:3f4:5bda:2710 with SMTP id ffacd0b85a97d-425829b0578mr10312452f8f.9.1760111452485; Fri, 10 Oct 2025 08:50:52 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Christoph Muellner , Heinrich Schuchardt , Palmer Dabbelt , Alistair Francis , Liu Zhiwei , Anton Johansson , Richard Henderson , Valentin Haudiquet , Weiwei Li , qemu-riscv@nongnu.org, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Fabien Portas , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= Subject: [PATCH 01/13] target/riscv: Really use little endianness for 128-bit loads/stores Date: Fri, 10 Oct 2025 17:50:32 +0200 Message-ID: <20251010155045.78220-2-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251010155045.78220-1-philmd@linaro.org> References: <20251010155045.78220-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760111676336158500 Per commit a2f827ff4f4 ("target/riscv: accessors to registers upper part and 128-bit load/store") description: > The 128-bit ISA adds ldu, lq and sq. We provide support for these > instructions. Note that (a) we compute only 64-bit addresses to > actually access memory, cowardly utilizing the existing address > translation mechanism of QEMU, and (b) we assume for now > little-endian memory accesses. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ However this commit used MO_TE (target endianness) for the gen_load_i128() and gen_store_i128() helpers. Likely it was unnoticed because current targets are only built using little endianness: $ git grep -L TARGET_BIG_ENDIAN=3Dy configs/targets/riscv* configs/targets/riscv32-linux-user.mak configs/targets/riscv32-softmmu.mak configs/targets/riscv64-bsd-user.mak configs/targets/riscv64-linux-user.mak configs/targets/riscv64-softmmu.mak Replace by MO_TE -> MO_LE to really use little endianness. Cc: Fabien Portas Cc: Fr=C3=A9d=C3=A9ric P=C3=A9trot Fixes: a2f827ff4f4 ("target/riscv: accessors to registers upper part and 12= 8-bit load/store") Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/insn_trans/trans_rvi.c.inc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index b9c71604687..df0b555176a 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -389,9 +389,11 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a= , MemOp memop) } } else { /* assume little-endian memory access for now */ - tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, MO_TEUQ); + MemOp memop =3D MO_LEUQ; + + tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, memop); tcg_gen_addi_tl(addrl, addrl, 8); - tcg_gen_qemu_ld_tl(desth, addrl, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_tl(desth, addrl, ctx->mem_idx, memop); } =20 gen_set_gpr128(ctx, a->rd, destl, desth); @@ -494,9 +496,11 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *= a, MemOp memop) tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop); } else { /* little-endian memory access assumed for now */ - tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, MO_TEUQ); + MemOp memop =3D MO_LEUQ; + + tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop); tcg_gen_addi_tl(addrl, addrl, 8); - tcg_gen_qemu_st_tl(src2h, addrl, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_st_tl(src2h, addrl, ctx->mem_idx, memop); } return true; } --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760111688; cv=none; d=zohomail.com; s=zohoarc; b=E5oiGyRuOU9mq4TsuSA+Mt2cfki/aVcp75t33oa8lIjB+NAiQk44zCcGHSJ0dV6qobiN43cTUkg41EKc42jFFSte7Dmh7f13SOFlUK68dIZ1DssM0Yr5hn9RCcMynDwBiQsnmDNNG19nW72LFADuLBKSwDPRs32hyByPXEAt93w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760111688; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=UD/RljEDGvX064KJHaXcd7tzn4JOZR8scnlJyrbWUko=; b=Ux/a/SKY7J5rfI0HZMbmjJ3d9vcbGmKqxF6gQ1HKJ+PkGyb1a9gpa+w8y5JOKFusN0XYv/SiuiHmWIFkQKffZ3tU5k9xG+GhkR3nILDOa8GJGPkU1pFq09FGmOJ29hm0o3cyEcaR6SP3W2dYdDEzF+PQAXDM7KH8rqS4cST23AE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760111688431374.73793205344305; Fri, 10 Oct 2025 08:54:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v7FOl-0003wc-9z; Fri, 10 Oct 2025 11:51:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v7FOg-0003w7-68 for qemu-devel@nongnu.org; Fri, 10 Oct 2025 11:51:11 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v7FOa-0002IJ-Ow for qemu-devel@nongnu.org; Fri, 10 Oct 2025 11:51:09 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-46e47cca387so21997185e9.3 for ; Fri, 10 Oct 2025 08:51:00 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/hexagon); \ done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/op_helper.c | 16 ++-- target/riscv/insn_trans/trans_rva.c.inc | 44 ++++----- target/riscv/insn_trans/trans_rvd.c.inc | 4 +- target/riscv/insn_trans/trans_rvf.c.inc | 4 +- target/riscv/insn_trans/trans_rvi.c.inc | 22 ++--- target/riscv/insn_trans/trans_rvzabha.c.inc | 20 ++--- target/riscv/insn_trans/trans_rvzacas.c.inc | 8 +- target/riscv/insn_trans/trans_rvzce.c.inc | 10 +-- target/riscv/insn_trans/trans_rvzfh.c.inc | 4 +- target/riscv/insn_trans/trans_rvzicfiss.c.inc | 4 +- target/riscv/insn_trans/trans_xthead.c.inc | 90 +++++++++---------- 11 files changed, 113 insertions(+), 113 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 8382aa94cb2..c486f771d35 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -633,7 +633,7 @@ target_ulong helper_hyp_hlv_hu(CPURISCVState *env, targ= et_ulong addr) { uintptr_t ra =3D GETPC(); int mmu_idx =3D check_access_hlsv(env, false, ra); - MemOpIdx oi =3D make_memop_idx(MO_TEUW, mmu_idx); + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UW, mmu_idx); =20 return cpu_ldw_mmu(env, adjust_addr_virt(env, addr), oi, ra); } @@ -642,7 +642,7 @@ target_ulong helper_hyp_hlv_wu(CPURISCVState *env, targ= et_ulong addr) { uintptr_t ra =3D GETPC(); int mmu_idx =3D check_access_hlsv(env, false, ra); - MemOpIdx oi =3D make_memop_idx(MO_TEUL, mmu_idx); + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL, mmu_idx); =20 return cpu_ldl_mmu(env, adjust_addr_virt(env, addr), oi, ra); } @@ -651,7 +651,7 @@ target_ulong helper_hyp_hlv_d(CPURISCVState *env, targe= t_ulong addr) { uintptr_t ra =3D GETPC(); int mmu_idx =3D check_access_hlsv(env, false, ra); - MemOpIdx oi =3D make_memop_idx(MO_TEUQ, mmu_idx); + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UQ, mmu_idx); =20 return cpu_ldq_mmu(env, adjust_addr_virt(env, addr), oi, ra); } @@ -669,7 +669,7 @@ void helper_hyp_hsv_h(CPURISCVState *env, target_ulong = addr, target_ulong val) { uintptr_t ra =3D GETPC(); int mmu_idx =3D check_access_hlsv(env, false, ra); - MemOpIdx oi =3D make_memop_idx(MO_TEUW, mmu_idx); + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UW, mmu_idx); =20 cpu_stw_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); } @@ -678,7 +678,7 @@ void helper_hyp_hsv_w(CPURISCVState *env, target_ulong = addr, target_ulong val) { uintptr_t ra =3D GETPC(); int mmu_idx =3D check_access_hlsv(env, false, ra); - MemOpIdx oi =3D make_memop_idx(MO_TEUL, mmu_idx); + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL, mmu_idx); =20 cpu_stl_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); } @@ -687,7 +687,7 @@ void helper_hyp_hsv_d(CPURISCVState *env, target_ulong = addr, target_ulong val) { uintptr_t ra =3D GETPC(); int mmu_idx =3D check_access_hlsv(env, false, ra); - MemOpIdx oi =3D make_memop_idx(MO_TEUQ, mmu_idx); + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UQ, mmu_idx); =20 cpu_stq_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); } @@ -703,7 +703,7 @@ target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, tar= get_ulong addr) { uintptr_t ra =3D GETPC(); int mmu_idx =3D check_access_hlsv(env, true, ra); - MemOpIdx oi =3D make_memop_idx(MO_TEUW, mmu_idx); + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UW, mmu_idx); =20 return cpu_ldw_code_mmu(env, addr, oi, GETPC()); } @@ -712,7 +712,7 @@ target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, tar= get_ulong addr) { uintptr_t ra =3D GETPC(); int mmu_idx =3D check_access_hlsv(env, true, ra); - MemOpIdx oi =3D make_memop_idx(MO_TEUL, mmu_idx); + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL, mmu_idx); =20 return cpu_ldl_code_mmu(env, addr, oi, ra); } diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index 9cf3ae8019b..10e4c55efda 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -99,142 +99,142 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, = MemOp mop) static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a) { REQUIRE_A_OR_ZALRSC(ctx); - return gen_lr(ctx, a, (MO_ALIGN | MO_TESL)); + return gen_lr(ctx, a, (MO_ALIGN | MO_TE | MO_SL)); } =20 static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a) { REQUIRE_A_OR_ZALRSC(ctx); - return gen_sc(ctx, a, (MO_ALIGN | MO_TESL)); + return gen_sc(ctx, a, (MO_ALIGN | MO_TE | MO_SL)); } =20 static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TESL); + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TE | MO_SL); } =20 static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TESL); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TE | MO_SL); } =20 static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TESL); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TE | MO_SL); } =20 static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TESL); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TE | MO_SL); } =20 static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TESL); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TE | MO_SL); } =20 static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TESL); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TE | MO_SL); } =20 static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TESL); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TE | MO_SL); } =20 static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TESL); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TE | MO_SL); } =20 static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TESL); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TE | MO_SL); } =20 static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZALRSC(ctx); - return gen_lr(ctx, a, MO_ALIGN | MO_TEUQ); + return gen_lr(ctx, a, MO_ALIGN | MO_TE | MO_UQ); } =20 static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZALRSC(ctx); - return gen_sc(ctx, a, (MO_ALIGN | MO_TEUQ)); + return gen_sc(ctx, a, (MO_ALIGN | MO_TE | MO_UQ)); } =20 static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TEUQ); + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TE | MO_UQ); } =20 static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TEUQ); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TE | MO_UQ); } =20 static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TEUQ); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TE | MO_UQ); } =20 static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TEUQ); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TE | MO_UQ); } =20 static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TEUQ); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TE | MO_UQ); } =20 static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TEUQ); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TE | MO_UQ); } =20 static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TEUQ); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TE | MO_UQ); } =20 static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TEUQ); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TE | MO_UQ); } =20 static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TEUQ); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TE | MO_UQ); } diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 30883ea37c8..33858206788 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -42,7 +42,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) { TCGv addr; - MemOp memop =3D MO_TEUQ; + MemOp memop =3D MO_TE | MO_UQ; =20 REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); @@ -72,7 +72,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) static bool trans_fsd(DisasContext *ctx, arg_fsd *a) { TCGv addr; - MemOp memop =3D MO_TEUQ; + MemOp memop =3D MO_TE | MO_UQ; =20 REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index ed73afe0894..150e2b9a7d4 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -43,7 +43,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) { TCGv_i64 dest; TCGv addr; - MemOp memop =3D MO_TEUL; + MemOp memop =3D MO_TE | MO_UL; =20 REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); @@ -65,7 +65,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) static bool trans_fsw(DisasContext *ctx, arg_fsw *a) { TCGv addr; - MemOp memop =3D MO_TEUL; + MemOp memop =3D MO_TE | MO_UL; =20 REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index df0b555176a..8194ea5073e 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -428,24 +428,24 @@ static bool trans_lb(DisasContext *ctx, arg_lb *a) =20 static bool trans_lh(DisasContext *ctx, arg_lh *a) { - return gen_load(ctx, a, MO_TESW); + return gen_load(ctx, a, MO_TE | MO_SW); } =20 static bool trans_lw(DisasContext *ctx, arg_lw *a) { - return gen_load(ctx, a, MO_TESL); + return gen_load(ctx, a, MO_TE | MO_SL); } =20 static bool trans_ld(DisasContext *ctx, arg_ld *a) { REQUIRE_64_OR_128BIT(ctx); - return gen_load(ctx, a, MO_TESQ); + return gen_load(ctx, a, MO_TE | MO_SQ); } =20 static bool trans_lq(DisasContext *ctx, arg_lq *a) { REQUIRE_128BIT(ctx); - return gen_load(ctx, a, MO_TEUO); + return gen_load(ctx, a, MO_TE | MO_UO); } =20 static bool trans_lbu(DisasContext *ctx, arg_lbu *a) @@ -455,19 +455,19 @@ static bool trans_lbu(DisasContext *ctx, arg_lbu *a) =20 static bool trans_lhu(DisasContext *ctx, arg_lhu *a) { - return gen_load(ctx, a, MO_TEUW); + return gen_load(ctx, a, MO_TE | MO_UW); } =20 static bool trans_lwu(DisasContext *ctx, arg_lwu *a) { REQUIRE_64_OR_128BIT(ctx); - return gen_load(ctx, a, MO_TEUL); + return gen_load(ctx, a, MO_TE | MO_UL); } =20 static bool trans_ldu(DisasContext *ctx, arg_ldu *a) { REQUIRE_128BIT(ctx); - return gen_load(ctx, a, MO_TEUQ); + return gen_load(ctx, a, MO_TE | MO_UQ); } =20 static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop) @@ -525,24 +525,24 @@ static bool trans_sb(DisasContext *ctx, arg_sb *a) =20 static bool trans_sh(DisasContext *ctx, arg_sh *a) { - return gen_store(ctx, a, MO_TESW); + return gen_store(ctx, a, MO_TE | MO_SW); } =20 static bool trans_sw(DisasContext *ctx, arg_sw *a) { - return gen_store(ctx, a, MO_TESL); + return gen_store(ctx, a, MO_TE | MO_SL); } =20 static bool trans_sd(DisasContext *ctx, arg_sd *a) { REQUIRE_64_OR_128BIT(ctx); - return gen_store(ctx, a, MO_TEUQ); + return gen_store(ctx, a, MO_TE | MO_UQ); } =20 static bool trans_sq(DisasContext *ctx, arg_sq *a) { REQUIRE_128BIT(ctx); - return gen_store(ctx, a, MO_TEUO); + return gen_store(ctx, a, MO_TE | MO_UO); } =20 static bool trans_addd(DisasContext *ctx, arg_addd *a) diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc b/target/riscv/ins= n_trans/trans_rvzabha.c.inc index ce8edcba62a..25db42d24cd 100644 --- a/target/riscv/insn_trans/trans_rvzabha.c.inc +++ b/target/riscv/insn_trans/trans_rvzabha.c.inc @@ -79,55 +79,55 @@ static bool trans_amomaxu_b(DisasContext *ctx, arg_amom= axu_b *a) static bool trans_amoswap_h(DisasContext *ctx, arg_amoswap_h *a) { REQUIRE_ZABHA(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TESW); + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TE | MO_SW); } =20 static bool trans_amoadd_h(DisasContext *ctx, arg_amoadd_h *a) { REQUIRE_ZABHA(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TESW); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TE | MO_SW); } =20 static bool trans_amoxor_h(DisasContext *ctx, arg_amoxor_h *a) { REQUIRE_ZABHA(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TESW); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TE | MO_SW); } =20 static bool trans_amoand_h(DisasContext *ctx, arg_amoand_h *a) { REQUIRE_ZABHA(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TESW); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TE | MO_SW); } =20 static bool trans_amoor_h(DisasContext *ctx, arg_amoor_h *a) { REQUIRE_ZABHA(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TESW); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TE | MO_SW); } =20 static bool trans_amomin_h(DisasContext *ctx, arg_amomin_h *a) { REQUIRE_ZABHA(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TESW); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TE | MO_SW); } =20 static bool trans_amomax_h(DisasContext *ctx, arg_amomax_h *a) { REQUIRE_ZABHA(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TESW); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TE | MO_SW); } =20 static bool trans_amominu_h(DisasContext *ctx, arg_amominu_h *a) { REQUIRE_ZABHA(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TESW); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TE | MO_SW); } =20 static bool trans_amomaxu_h(DisasContext *ctx, arg_amomaxu_h *a) { REQUIRE_ZABHA(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TESW); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TE | MO_SW); } =20 static bool trans_amocas_b(DisasContext *ctx, arg_amocas_b *a) @@ -141,5 +141,5 @@ static bool trans_amocas_h(DisasContext *ctx, arg_amoca= s_h *a) { REQUIRE_ZACAS(ctx); REQUIRE_ZABHA(ctx); - return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TESW); + return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TE | MO_SW); } diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/ins= n_trans/trans_rvzacas.c.inc index 15e688a0331..5e7c7c92b72 100644 --- a/target/riscv/insn_trans/trans_rvzacas.c.inc +++ b/target/riscv/insn_trans/trans_rvzacas.c.inc @@ -25,7 +25,7 @@ static bool trans_amocas_w(DisasContext *ctx, arg_amocas_w *a) { REQUIRE_ZACAS(ctx); - return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TESL); + return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TE | MO_SL); } =20 static TCGv_i64 get_gpr_pair(DisasContext *ctx, int reg_num) @@ -88,10 +88,10 @@ static bool trans_amocas_d(DisasContext *ctx, arg_amoca= s_d *a) REQUIRE_ZACAS(ctx); switch (get_ol(ctx)) { case MXL_RV32: - return gen_cmpxchg64(ctx, a, MO_ALIGN | MO_TEUQ); + return gen_cmpxchg64(ctx, a, MO_ALIGN | MO_TE | MO_UQ); case MXL_RV64: case MXL_RV128: - return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TEUQ); + return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TE | MO_UQ); default: g_assert_not_reached(); } @@ -123,7 +123,7 @@ static bool trans_amocas_q(DisasContext *ctx, arg_amoca= s_q *a) tcg_gen_concat_i64_i128(dest, destl, desth); decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); tcg_gen_atomic_cmpxchg_i128(dest, src1, dest, src2, ctx->mem_idx, - (MO_ALIGN | MO_TEUO)); + (MO_ALIGN | MO_TE | MO_UO)); =20 tcg_gen_extr_i128_i64(destl, desth, dest); =20 diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_= trans/trans_rvzce.c.inc index dd15af0f54b..d1301794324 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -88,13 +88,13 @@ static bool trans_c_lbu(DisasContext *ctx, arg_c_lbu *a) static bool trans_c_lhu(DisasContext *ctx, arg_c_lhu *a) { REQUIRE_ZCB(ctx); - return gen_load(ctx, a, MO_TEUW); + return gen_load(ctx, a, MO_TE | MO_UW); } =20 static bool trans_c_lh(DisasContext *ctx, arg_c_lh *a) { REQUIRE_ZCB(ctx); - return gen_load(ctx, a, MO_TESW); + return gen_load(ctx, a, MO_TE | MO_SW); } =20 static bool trans_c_sb(DisasContext *ctx, arg_c_sb *a) @@ -106,7 +106,7 @@ static bool trans_c_sb(DisasContext *ctx, arg_c_sb *a) static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a) { REQUIRE_ZCB(ctx); - return gen_store(ctx, a, MO_TEUW); + return gen_store(ctx, a, MO_TE | MO_UW); } =20 #define X_S0 8 @@ -175,7 +175,7 @@ static bool gen_pop(DisasContext *ctx, arg_cmpp *a, boo= l ret, bool ret_val) return false; } =20 - MemOp memop =3D get_ol(ctx) =3D=3D MXL_RV32 ? MO_TEUL : MO_TEUQ; + MemOp memop =3D get_ol(ctx) =3D=3D MXL_RV32 ? MO_TE | MO_UL : MO_TE | = MO_UQ; int reg_size =3D memop_size(memop); target_ulong stack_adj =3D ROUND_UP(ctpop32(reg_bitmap) * reg_size, 16= ) + a->spimm; @@ -228,7 +228,7 @@ static bool trans_cm_push(DisasContext *ctx, arg_cm_pus= h *a) return false; } =20 - MemOp memop =3D get_ol(ctx) =3D=3D MXL_RV32 ? MO_TEUL : MO_TEUQ; + MemOp memop =3D get_ol(ctx) =3D=3D MXL_RV32 ? MO_TE | MO_UL : MO_TE | = MO_UQ; int reg_size =3D memop_size(memop); target_ulong stack_adj =3D ROUND_UP(ctpop32(reg_bitmap) * reg_size, 16= ) + a->spimm; diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_= trans/trans_rvzfh.c.inc index bece48e6009..eec478afcb0 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -57,7 +57,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) } =20 dest =3D cpu_fpr[a->rd]; - tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, MO_TEUW); + tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, MO_TE | MO_UW); gen_nanbox_h(dest, dest); =20 mark_fs_dirty(ctx); @@ -79,7 +79,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) t0 =3D temp; } =20 - tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUW); + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TE | MO_UW); =20 return true; } diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/i= nsn_trans/trans_rvzicfiss.c.inc index f4a1c12ca0b..c5555966175 100644 --- a/target/riscv/insn_trans/trans_rvzicfiss.c.inc +++ b/target/riscv/insn_trans/trans_rvzicfiss.c.inc @@ -105,7 +105,7 @@ static bool trans_ssamoswap_w(DisasContext *ctx, arg_am= oswap_w *a) src1 =3D get_address(ctx, a->rs1, 0); =20 tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), - (MO_ALIGN | MO_TESL)); + (MO_ALIGN | MO_TE | MO_SL)); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -134,7 +134,7 @@ static bool trans_ssamoswap_d(DisasContext *ctx, arg_am= oswap_w *a) src1 =3D get_address(ctx, a->rs1, 0); =20 tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), - (MO_ALIGN | MO_TESQ)); + (MO_ALIGN | MO_TE | MO_SQ)); gen_set_gpr(ctx, a->rd, dest); return true; } diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 22488412d4d..754cb80e221 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -379,7 +379,7 @@ static bool trans_th_flrd(DisasContext *ctx, arg_th_mem= idx *a) REQUIRE_XTHEADFMEMIDX(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - return gen_fload_idx(ctx, a, MO_TEUQ, false); + return gen_fload_idx(ctx, a, MO_TE | MO_UQ, false); } =20 static bool trans_th_flrw(DisasContext *ctx, arg_th_memidx *a) @@ -387,7 +387,7 @@ static bool trans_th_flrw(DisasContext *ctx, arg_th_mem= idx *a) REQUIRE_XTHEADFMEMIDX(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - return gen_fload_idx(ctx, a, MO_TEUL, false); + return gen_fload_idx(ctx, a, MO_TE | MO_UL, false); } =20 static bool trans_th_flurd(DisasContext *ctx, arg_th_memidx *a) @@ -395,7 +395,7 @@ static bool trans_th_flurd(DisasContext *ctx, arg_th_me= midx *a) REQUIRE_XTHEADFMEMIDX(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - return gen_fload_idx(ctx, a, MO_TEUQ, true); + return gen_fload_idx(ctx, a, MO_TE | MO_UQ, true); } =20 static bool trans_th_flurw(DisasContext *ctx, arg_th_memidx *a) @@ -403,7 +403,7 @@ static bool trans_th_flurw(DisasContext *ctx, arg_th_me= midx *a) REQUIRE_XTHEADFMEMIDX(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - return gen_fload_idx(ctx, a, MO_TEUL, true); + return gen_fload_idx(ctx, a, MO_TE | MO_UL, true); } =20 static bool trans_th_fsrd(DisasContext *ctx, arg_th_memidx *a) @@ -411,7 +411,7 @@ static bool trans_th_fsrd(DisasContext *ctx, arg_th_mem= idx *a) REQUIRE_XTHEADFMEMIDX(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - return gen_fstore_idx(ctx, a, MO_TEUQ, false); + return gen_fstore_idx(ctx, a, MO_TE | MO_UQ, false); } =20 static bool trans_th_fsrw(DisasContext *ctx, arg_th_memidx *a) @@ -419,7 +419,7 @@ static bool trans_th_fsrw(DisasContext *ctx, arg_th_mem= idx *a) REQUIRE_XTHEADFMEMIDX(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - return gen_fstore_idx(ctx, a, MO_TEUL, false); + return gen_fstore_idx(ctx, a, MO_TE | MO_UL, false); } =20 static bool trans_th_fsurd(DisasContext *ctx, arg_th_memidx *a) @@ -427,7 +427,7 @@ static bool trans_th_fsurd(DisasContext *ctx, arg_th_me= midx *a) REQUIRE_XTHEADFMEMIDX(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - return gen_fstore_idx(ctx, a, MO_TEUQ, true); + return gen_fstore_idx(ctx, a, MO_TE | MO_UQ, true); } =20 static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a) @@ -435,7 +435,7 @@ static bool trans_th_fsurw(DisasContext *ctx, arg_th_me= midx *a) REQUIRE_XTHEADFMEMIDX(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - return gen_fstore_idx(ctx, a, MO_TEUL, true); + return gen_fstore_idx(ctx, a, MO_TE | MO_UL, true); } =20 /* XTheadFmv */ @@ -598,64 +598,64 @@ static bool trans_th_ldia(DisasContext *ctx, arg_th_m= eminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_inc(ctx, a, MO_TESQ, false); + return gen_load_inc(ctx, a, MO_TE | MO_SQ, false); } =20 static bool trans_th_ldib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_inc(ctx, a, MO_TESQ, true); + return gen_load_inc(ctx, a, MO_TE | MO_SQ, true); } =20 static bool trans_th_lwia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TESL, false); + return gen_load_inc(ctx, a, MO_TE | MO_SL, false); } =20 static bool trans_th_lwib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TESL, true); + return gen_load_inc(ctx, a, MO_TE | MO_SL, true); } =20 static bool trans_th_lwuia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_inc(ctx, a, MO_TEUL, false); + return gen_load_inc(ctx, a, MO_TE | MO_UL, false); } =20 static bool trans_th_lwuib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_inc(ctx, a, MO_TEUL, true); + return gen_load_inc(ctx, a, MO_TE | MO_UL, true); } =20 static bool trans_th_lhia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TESW, false); + return gen_load_inc(ctx, a, MO_TE | MO_SW, false); } =20 static bool trans_th_lhib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TESW, true); + return gen_load_inc(ctx, a, MO_TE | MO_SW, true); } =20 static bool trans_th_lhuia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TEUW, false); + return gen_load_inc(ctx, a, MO_TE | MO_UW, false); } =20 static bool trans_th_lhuib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TEUW, true); + return gen_load_inc(ctx, a, MO_TE | MO_UW, true); } =20 static bool trans_th_lbia(DisasContext *ctx, arg_th_meminc *a) @@ -686,38 +686,38 @@ static bool trans_th_sdia(DisasContext *ctx, arg_th_m= eminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_store_inc(ctx, a, MO_TESQ, false); + return gen_store_inc(ctx, a, MO_TE | MO_SQ, false); } =20 static bool trans_th_sdib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_store_inc(ctx, a, MO_TESQ, true); + return gen_store_inc(ctx, a, MO_TE | MO_SQ, true); } =20 static bool trans_th_swia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_inc(ctx, a, MO_TESL, false); + return gen_store_inc(ctx, a, MO_TE | MO_SL, false); } =20 static bool trans_th_swib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_inc(ctx, a, MO_TESL, true); + return gen_store_inc(ctx, a, MO_TE | MO_SL, true); } =20 static bool trans_th_shia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_inc(ctx, a, MO_TESW, false); + return gen_store_inc(ctx, a, MO_TE | MO_SW, false); } =20 static bool trans_th_shib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_inc(ctx, a, MO_TESW, true); + return gen_store_inc(ctx, a, MO_TE | MO_SW, true); } =20 static bool trans_th_sbia(DisasContext *ctx, arg_th_meminc *a) @@ -769,32 +769,32 @@ static bool trans_th_lrd(DisasContext *ctx, arg_th_me= midx *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_idx(ctx, a, MO_TESQ, false); + return gen_load_idx(ctx, a, MO_TE | MO_SQ, false); } =20 static bool trans_th_lrw(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_idx(ctx, a, MO_TESL, false); + return gen_load_idx(ctx, a, MO_TE | MO_SL, false); } =20 static bool trans_th_lrwu(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_idx(ctx, a, MO_TEUL, false); + return gen_load_idx(ctx, a, MO_TE | MO_UL, false); } =20 static bool trans_th_lrh(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_idx(ctx, a, MO_TESW, false); + return gen_load_idx(ctx, a, MO_TE | MO_SW, false); } =20 static bool trans_th_lrhu(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_idx(ctx, a, MO_TEUW, false); + return gen_load_idx(ctx, a, MO_TE | MO_UW, false); } =20 static bool trans_th_lrb(DisasContext *ctx, arg_th_memidx *a) @@ -813,19 +813,19 @@ static bool trans_th_srd(DisasContext *ctx, arg_th_me= midx *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_store_idx(ctx, a, MO_TESQ, false); + return gen_store_idx(ctx, a, MO_TE | MO_SQ, false); } =20 static bool trans_th_srw(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_idx(ctx, a, MO_TESL, false); + return gen_store_idx(ctx, a, MO_TE | MO_SL, false); } =20 static bool trans_th_srh(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_idx(ctx, a, MO_TESW, false); + return gen_store_idx(ctx, a, MO_TE | MO_SW, false); } =20 static bool trans_th_srb(DisasContext *ctx, arg_th_memidx *a) @@ -837,32 +837,32 @@ static bool trans_th_lurd(DisasContext *ctx, arg_th_m= emidx *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_idx(ctx, a, MO_TESQ, true); + return gen_load_idx(ctx, a, MO_TE | MO_SQ, true); } =20 static bool trans_th_lurw(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_idx(ctx, a, MO_TESL, true); + return gen_load_idx(ctx, a, MO_TE | MO_SL, true); } =20 static bool trans_th_lurwu(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_idx(ctx, a, MO_TEUL, true); + return gen_load_idx(ctx, a, MO_TE | MO_UL, true); } =20 static bool trans_th_lurh(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_idx(ctx, a, MO_TESW, true); + return gen_load_idx(ctx, a, MO_TE | MO_SW, true); } =20 static bool trans_th_lurhu(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_idx(ctx, a, MO_TEUW, true); + return gen_load_idx(ctx, a, MO_TE | MO_UW, true); } =20 static bool trans_th_lurb(DisasContext *ctx, arg_th_memidx *a) @@ -881,19 +881,19 @@ static bool trans_th_surd(DisasContext *ctx, arg_th_m= emidx *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_store_idx(ctx, a, MO_TESQ, true); + return gen_store_idx(ctx, a, MO_TE | MO_SQ, true); } =20 static bool trans_th_surw(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_idx(ctx, a, MO_TESL, true); + return gen_store_idx(ctx, a, MO_TE | MO_SL, true); } =20 static bool trans_th_surh(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_idx(ctx, a, MO_TESW, true); + return gen_store_idx(ctx, a, MO_TE | MO_SW, true); } =20 static bool trans_th_surb(DisasContext *ctx, arg_th_memidx *a) @@ -931,19 +931,19 @@ static bool trans_th_ldd(DisasContext *ctx, arg_th_pa= ir *a) { REQUIRE_XTHEADMEMPAIR(ctx); REQUIRE_64BIT(ctx); - return gen_loadpair_tl(ctx, a, MO_TESQ, 4); + return gen_loadpair_tl(ctx, a, MO_TE | MO_SQ, 4); } =20 static bool trans_th_lwd(DisasContext *ctx, arg_th_pair *a) { REQUIRE_XTHEADMEMPAIR(ctx); - return gen_loadpair_tl(ctx, a, MO_TESL, 3); + return gen_loadpair_tl(ctx, a, MO_TE | MO_SL, 3); } =20 static bool trans_th_lwud(DisasContext *ctx, arg_th_pair *a) { REQUIRE_XTHEADMEMPAIR(ctx); - return gen_loadpair_tl(ctx, a, MO_TEUL, 3); + return gen_loadpair_tl(ctx, a, MO_TE | MO_UL, 3); } =20 static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memo= p, @@ -967,13 +967,13 @@ static bool trans_th_sdd(DisasContext *ctx, arg_th_pa= ir *a) { REQUIRE_XTHEADMEMPAIR(ctx); REQUIRE_64BIT(ctx); - return gen_storepair_tl(ctx, a, MO_TESQ, 4); + return gen_storepair_tl(ctx, a, MO_TE | MO_SQ, 4); } =20 static bool trans_th_swd(DisasContext *ctx, arg_th_pair *a) { REQUIRE_XTHEADMEMPAIR(ctx); - return gen_storepair_tl(ctx, a, MO_TESL, 3); + return gen_storepair_tl(ctx, a, MO_TE | MO_SL, 3); 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Set it once in the callee. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/translate.c | 1 + target/riscv/insn_trans/trans_rva.c.inc | 36 ++++++++++----------- target/riscv/insn_trans/trans_rvzabha.c.inc | 18 +++++------ 3 files changed, 28 insertions(+), 27 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9a53aecbfe9..94af9853cfe 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1135,6 +1135,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, TCGv src1, src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); MemOp size =3D mop & MO_SIZE; =20 + mop |=3D MO_TE; if (ctx->cfg_ptr->ext_zama16b && size >=3D MO_32) { mop |=3D MO_ATOM_WITHIN16; } else { diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index 10e4c55efda..e0fbfafdde4 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -111,55 +111,55 @@ static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a) static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TE | MO_SL); + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_SL); } =20 static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TE | MO_SL); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_SL); } =20 static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TE | MO_SL); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_SL); } =20 static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TE | MO_SL); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_SL); } =20 static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TE | MO_SL); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_SL); } =20 static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TE | MO_SL); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_SL); } =20 static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TE | MO_SL); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_SL); } =20 static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TE | MO_SL); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_SL); } =20 static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a) { REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TE | MO_SL); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_SL); } =20 static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a) @@ -180,61 +180,61 @@ static bool trans_amoswap_d(DisasContext *ctx, arg_am= oswap_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TE | MO_UQ); + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_UQ); } =20 static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TE | MO_UQ); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_UQ); } =20 static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TE | MO_UQ); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_UQ); } =20 static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TE | MO_UQ); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_UQ); } =20 static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TE | MO_UQ); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_UQ); } =20 static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TE | MO_UQ); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_UQ); } =20 static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TE | MO_UQ); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_UQ); } =20 static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TE | MO_UQ); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_UQ); } =20 static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZAAMO(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TE | MO_UQ); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_UQ); } diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc b/target/riscv/ins= n_trans/trans_rvzabha.c.inc index 25db42d24cd..c1f99b65f09 100644 --- a/target/riscv/insn_trans/trans_rvzabha.c.inc +++ b/target/riscv/insn_trans/trans_rvzabha.c.inc @@ -79,55 +79,55 @@ static bool trans_amomaxu_b(DisasContext *ctx, arg_amom= axu_b *a) static bool trans_amoswap_h(DisasContext *ctx, arg_amoswap_h *a) { REQUIRE_ZABHA(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TE | MO_SW); + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_SW); } =20 static bool trans_amoadd_h(DisasContext *ctx, arg_amoadd_h *a) { REQUIRE_ZABHA(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TE | MO_SW); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_SW); } =20 static bool trans_amoxor_h(DisasContext *ctx, arg_amoxor_h *a) { REQUIRE_ZABHA(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TE | MO_SW); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_SW); } =20 static bool trans_amoand_h(DisasContext *ctx, arg_amoand_h *a) { REQUIRE_ZABHA(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TE | MO_SW); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_SW); } =20 static bool trans_amoor_h(DisasContext *ctx, arg_amoor_h *a) { REQUIRE_ZABHA(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TE | MO_SW); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_SW); } =20 static bool trans_amomin_h(DisasContext *ctx, arg_amomin_h *a) { REQUIRE_ZABHA(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TE | MO_SW); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_SW); } =20 static bool trans_amomax_h(DisasContext *ctx, arg_amomax_h *a) { REQUIRE_ZABHA(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TE | MO_SW); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_SW); } =20 static bool trans_amominu_h(DisasContext *ctx, arg_amominu_h *a) { REQUIRE_ZABHA(ctx); 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Set it once in the callee. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_xthead.c.inc | 34 ++++++++++++---------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 754cb80e221..7e69906e5bf 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -568,6 +568,7 @@ static bool gen_load_inc(DisasContext *ctx, arg_th_memi= nc *a, MemOp memop, TCGv rd =3D dest_gpr(ctx, a->rd); TCGv rs1 =3D get_gpr(ctx, a->rs1, EXT_NONE); =20 + memop |=3D MO_TE; tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); tcg_gen_addi_tl(rs1, rs1, imm); gen_set_gpr(ctx, a->rd, rd); @@ -588,6 +589,7 @@ static bool gen_store_inc(DisasContext *ctx, arg_th_mem= inc *a, MemOp memop, TCGv data =3D get_gpr(ctx, a->rd, EXT_NONE); TCGv rs1 =3D get_gpr(ctx, a->rs1, EXT_NONE); =20 + memop |=3D MO_TE; tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); tcg_gen_addi_tl(rs1, rs1, imm); gen_set_gpr(ctx, a->rs1, rs1); @@ -598,64 +600,64 @@ static bool trans_th_ldia(DisasContext *ctx, arg_th_m= eminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SQ, false); + return gen_load_inc(ctx, a, MO_SQ, false); } =20 static bool trans_th_ldib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SQ, true); + return gen_load_inc(ctx, a, MO_SQ, true); } =20 static bool trans_th_lwia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SL, false); + return gen_load_inc(ctx, a, MO_SL, false); } =20 static bool trans_th_lwib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SL, true); + return gen_load_inc(ctx, a, MO_SL, true); } =20 static bool trans_th_lwuia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_UL, false); + return gen_load_inc(ctx, a, MO_UL, false); } =20 static bool trans_th_lwuib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_UL, true); + return gen_load_inc(ctx, a, MO_UL, true); } =20 static bool trans_th_lhia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SW, false); + return gen_load_inc(ctx, a, MO_SW, false); } =20 static bool trans_th_lhib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SW, true); + return gen_load_inc(ctx, a, MO_SW, true); } =20 static bool trans_th_lhuia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_UW, false); + return gen_load_inc(ctx, a, MO_UW, false); } =20 static bool trans_th_lhuib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_UW, true); + return gen_load_inc(ctx, a, MO_UW, true); } =20 static bool trans_th_lbia(DisasContext *ctx, arg_th_meminc *a) @@ -686,38 +688,38 @@ static bool trans_th_sdia(DisasContext *ctx, arg_th_m= eminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SQ, false); + return gen_store_inc(ctx, a, MO_SQ, false); } =20 static bool trans_th_sdib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SQ, true); + return gen_store_inc(ctx, a, MO_SQ, true); } =20 static bool trans_th_swia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SL, false); + return gen_store_inc(ctx, a, MO_SL, false); } =20 static bool trans_th_swib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SL, true); + return gen_store_inc(ctx, a, MO_SL, true); } =20 static bool trans_th_shia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SW, false); + return gen_store_inc(ctx, a, MO_SW, false); } =20 static bool trans_th_shib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SW, true); + return gen_store_inc(ctx, a, MO_SW, true); } =20 static bool trans_th_sbia(DisasContext *ctx, arg_th_meminc *a) --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760111799; cv=none; d=zohomail.com; s=zohoarc; b=XE5UOzLHj0cjLWXdeCwFfWb/CPfaSpIBAKkDKFDb+vmMqhhVX47UkHpMnuXfCpbcwkyH4VwjIJay2uXEptiibL1s1mypzdeA5kK83EnNBiMwdb9P8bFeBuqICGK3HZiHSY2tFjI4pMFzd6YIgjfL4PAWc9w3mHUyBNvvb5YyIAM= ARC-Message-Signature: i=1; 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Set it once in the callees. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvi.c.inc | 24 ++++++++++++----------- target/riscv/insn_trans/trans_rvzce.c.inc | 6 +++--- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 8194ea5073e..8db3e78baab 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -404,6 +404,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemO= p memop) { bool out; =20 + memop |=3D MO_TE; if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } @@ -428,24 +429,24 @@ static bool trans_lb(DisasContext *ctx, arg_lb *a) =20 static bool trans_lh(DisasContext *ctx, arg_lh *a) { - return gen_load(ctx, a, MO_TE | MO_SW); + return gen_load(ctx, a, MO_SW); } =20 static bool trans_lw(DisasContext *ctx, arg_lw *a) { - return gen_load(ctx, a, MO_TE | MO_SL); + return gen_load(ctx, a, MO_SL); } =20 static bool trans_ld(DisasContext *ctx, arg_ld *a) { REQUIRE_64_OR_128BIT(ctx); - return gen_load(ctx, a, MO_TE | MO_SQ); + return gen_load(ctx, a, MO_SQ); } =20 static bool trans_lq(DisasContext *ctx, arg_lq *a) { REQUIRE_128BIT(ctx); - return gen_load(ctx, a, MO_TE | MO_UO); + return gen_load(ctx, a, MO_UO); } =20 static bool trans_lbu(DisasContext *ctx, arg_lbu *a) @@ -455,19 +456,19 @@ static bool trans_lbu(DisasContext *ctx, arg_lbu *a) =20 static bool trans_lhu(DisasContext *ctx, arg_lhu *a) { - return gen_load(ctx, a, MO_TE | MO_UW); + return gen_load(ctx, a, MO_UW); } =20 static bool trans_lwu(DisasContext *ctx, arg_lwu *a) { REQUIRE_64_OR_128BIT(ctx); - return gen_load(ctx, a, MO_TE | MO_UL); + return gen_load(ctx, a, MO_UL); } =20 static bool trans_ldu(DisasContext *ctx, arg_ldu *a) { REQUIRE_128BIT(ctx); - return gen_load(ctx, a, MO_TE | MO_UQ); + return gen_load(ctx, a, MO_UQ); } =20 static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop) @@ -507,6 +508,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a= , MemOp memop) =20 static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) { + memop |=3D MO_TE; if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } @@ -525,24 +527,24 @@ static bool trans_sb(DisasContext *ctx, arg_sb *a) =20 static bool trans_sh(DisasContext *ctx, arg_sh *a) { - return gen_store(ctx, a, MO_TE | MO_SW); + return gen_store(ctx, a, MO_SW); } =20 static bool trans_sw(DisasContext *ctx, arg_sw *a) { - return gen_store(ctx, a, MO_TE | MO_SL); + return gen_store(ctx, a, MO_SL); } =20 static bool trans_sd(DisasContext *ctx, arg_sd *a) { REQUIRE_64_OR_128BIT(ctx); - return gen_store(ctx, a, MO_TE | MO_UQ); + return gen_store(ctx, a, MO_UQ); } =20 static bool trans_sq(DisasContext *ctx, arg_sq *a) { REQUIRE_128BIT(ctx); - return gen_store(ctx, a, MO_TE | MO_UO); + return gen_store(ctx, a, MO_UO); } =20 static bool trans_addd(DisasContext *ctx, arg_addd *a) diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_= trans/trans_rvzce.c.inc index d1301794324..c8dc102c8e3 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -88,13 +88,13 @@ static bool trans_c_lbu(DisasContext *ctx, arg_c_lbu *a) static bool trans_c_lhu(DisasContext *ctx, arg_c_lhu *a) { REQUIRE_ZCB(ctx); - return gen_load(ctx, a, MO_TE | MO_UW); + return gen_load(ctx, a, MO_UW); } =20 static bool trans_c_lh(DisasContext *ctx, arg_c_lh *a) { REQUIRE_ZCB(ctx); - return gen_load(ctx, a, MO_TE | MO_SW); + return gen_load(ctx, a, MO_SW); } =20 static bool trans_c_sb(DisasContext *ctx, arg_c_sb *a) @@ -106,7 +106,7 @@ static bool trans_c_sb(DisasContext *ctx, arg_c_sb *a) static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a) { REQUIRE_ZCB(ctx); - return gen_store(ctx, a, MO_TE | MO_UW); + return gen_store(ctx, a, MO_UW); } =20 #define X_S0 8 --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760111573; cv=none; d=zohomail.com; s=zohoarc; b=ktIsI4pylmATLfQz7y+vpMmwoAK05O7lY5kngVeSaULjhHUMmJZ1mjkGDfkGQP+//NX2Xpyat/nFqNxRz38vcDsi9ecuYwxWbipL/dDIsmtM7gxb8f4/WPP3iihTzs6Lrjst876X2hIQdAfb942Fm9Vi2uYUXAyk6M7N4ynffu8= ARC-Message-Signature: i=1; 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Set it once in the callees. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_xthead.c.inc | 34 ++++++++++++---------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 7e69906e5bf..70c563664ab 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -745,6 +745,7 @@ static bool gen_load_idx(DisasContext *ctx, arg_th_memi= dx *a, MemOp memop, TCGv rd =3D dest_gpr(ctx, a->rd); TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); =20 + memop |=3D MO_TE; tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); gen_set_gpr(ctx, a->rd, rd); =20 @@ -762,6 +763,7 @@ static bool gen_store_idx(DisasContext *ctx, arg_th_mem= idx *a, MemOp memop, TCGv data =3D get_gpr(ctx, a->rd, EXT_NONE); TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); =20 + memop |=3D MO_TE; tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); =20 return true; @@ -771,32 +773,32 @@ static bool trans_th_lrd(DisasContext *ctx, arg_th_me= midx *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_idx(ctx, a, MO_TE | MO_SQ, false); + return gen_load_idx(ctx, a, MO_SQ, false); } =20 static bool trans_th_lrw(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_idx(ctx, a, MO_TE | MO_SL, false); + return gen_load_idx(ctx, a, MO_SL, false); } =20 static bool trans_th_lrwu(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_idx(ctx, a, MO_TE | MO_UL, false); + return gen_load_idx(ctx, a, MO_UL, false); } =20 static bool trans_th_lrh(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_idx(ctx, a, MO_TE | MO_SW, false); + return gen_load_idx(ctx, a, MO_SW, false); } =20 static bool trans_th_lrhu(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_idx(ctx, a, MO_TE | MO_UW, false); + return gen_load_idx(ctx, a, MO_UW, false); } =20 static bool trans_th_lrb(DisasContext *ctx, arg_th_memidx *a) @@ -815,19 +817,19 @@ static bool trans_th_srd(DisasContext *ctx, arg_th_me= midx *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_store_idx(ctx, a, MO_TE | MO_SQ, false); + return gen_store_idx(ctx, a, MO_SQ, false); } =20 static bool trans_th_srw(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_idx(ctx, a, MO_TE | MO_SL, false); + return gen_store_idx(ctx, a, MO_SL, false); } =20 static bool trans_th_srh(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_idx(ctx, a, MO_TE | MO_SW, false); + return gen_store_idx(ctx, a, MO_SW, false); } =20 static bool trans_th_srb(DisasContext *ctx, arg_th_memidx *a) @@ -839,32 +841,32 @@ static bool trans_th_lurd(DisasContext *ctx, arg_th_m= emidx *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_idx(ctx, a, MO_TE | MO_SQ, true); + return gen_load_idx(ctx, a, MO_SQ, true); } =20 static bool trans_th_lurw(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_idx(ctx, a, MO_TE | MO_SL, true); + return gen_load_idx(ctx, a, MO_SL, true); } =20 static bool trans_th_lurwu(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_idx(ctx, a, MO_TE | MO_UL, true); + return gen_load_idx(ctx, a, MO_UL, true); } =20 static bool trans_th_lurh(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_idx(ctx, a, MO_TE | MO_SW, true); + return gen_load_idx(ctx, a, MO_SW, true); } =20 static bool trans_th_lurhu(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_idx(ctx, a, MO_TE | MO_UW, true); + return gen_load_idx(ctx, a, MO_UW, true); } =20 static bool trans_th_lurb(DisasContext *ctx, arg_th_memidx *a) @@ -883,19 +885,19 @@ static bool trans_th_surd(DisasContext *ctx, arg_th_m= emidx *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_store_idx(ctx, a, MO_TE | MO_SQ, true); + return gen_store_idx(ctx, a, MO_SQ, true); } =20 static bool trans_th_surw(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_idx(ctx, a, MO_TE | MO_SL, true); + return gen_store_idx(ctx, a, MO_SL, true); } =20 static bool trans_th_surh(DisasContext *ctx, arg_th_memidx *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_idx(ctx, a, MO_TE | MO_SW, true); + return gen_store_idx(ctx, a, MO_SW, true); } =20 static bool trans_th_surb(DisasContext *ctx, arg_th_memidx *a) --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760111670; cv=none; d=zohomail.com; s=zohoarc; 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Set it once in the callees. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_xthead.c.inc | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 70c563664ab..859cbc26cb2 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -349,6 +349,7 @@ static bool gen_fload_idx(DisasContext *ctx, arg_th_mem= idx *a, MemOp memop, TCGv_i64 rd =3D cpu_fpr[a->rd]; TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); =20 + memop |=3D MO_TE; tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop); if ((memop & MO_SIZE) =3D=3D MO_32) { gen_nanbox_s(rd, rd); @@ -369,6 +370,7 @@ static bool gen_fstore_idx(DisasContext *ctx, arg_th_me= midx *a, MemOp memop, TCGv_i64 rd =3D cpu_fpr[a->rd]; TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); =20 + memop |=3D MO_TE; tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop); =20 return true; @@ -379,7 +381,7 @@ static bool trans_th_flrd(DisasContext *ctx, arg_th_mem= idx *a) REQUIRE_XTHEADFMEMIDX(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - return gen_fload_idx(ctx, a, MO_TE | MO_UQ, false); + return gen_fload_idx(ctx, a, MO_UQ, false); } =20 static bool trans_th_flrw(DisasContext *ctx, arg_th_memidx *a) @@ -387,7 +389,7 @@ static bool trans_th_flrw(DisasContext *ctx, arg_th_mem= idx *a) REQUIRE_XTHEADFMEMIDX(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - return gen_fload_idx(ctx, a, MO_TE | MO_UL, false); + return gen_fload_idx(ctx, a, MO_UL, false); } =20 static bool trans_th_flurd(DisasContext *ctx, arg_th_memidx *a) @@ -395,7 +397,7 @@ static bool trans_th_flurd(DisasContext *ctx, arg_th_me= midx *a) REQUIRE_XTHEADFMEMIDX(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - return gen_fload_idx(ctx, a, MO_TE | MO_UQ, true); + return gen_fload_idx(ctx, a, MO_UQ, true); } =20 static bool trans_th_flurw(DisasContext *ctx, arg_th_memidx *a) @@ -403,7 +405,7 @@ static bool trans_th_flurw(DisasContext *ctx, arg_th_me= midx *a) REQUIRE_XTHEADFMEMIDX(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - return gen_fload_idx(ctx, a, MO_TE | MO_UL, true); + return gen_fload_idx(ctx, a, MO_UL, true); } =20 static bool trans_th_fsrd(DisasContext *ctx, arg_th_memidx *a) @@ -411,7 +413,7 @@ static bool trans_th_fsrd(DisasContext *ctx, arg_th_mem= idx *a) REQUIRE_XTHEADFMEMIDX(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - return gen_fstore_idx(ctx, a, MO_TE | MO_UQ, false); + return gen_fstore_idx(ctx, a, MO_UQ, false); } =20 static bool trans_th_fsrw(DisasContext *ctx, arg_th_memidx *a) @@ -419,7 +421,7 @@ static bool trans_th_fsrw(DisasContext *ctx, arg_th_mem= idx *a) REQUIRE_XTHEADFMEMIDX(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - return gen_fstore_idx(ctx, a, MO_TE | MO_UL, false); + return gen_fstore_idx(ctx, a, MO_UL, false); } =20 static bool trans_th_fsurd(DisasContext *ctx, arg_th_memidx *a) @@ -427,7 +429,7 @@ static bool trans_th_fsurd(DisasContext *ctx, arg_th_me= midx *a) REQUIRE_XTHEADFMEMIDX(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - return gen_fstore_idx(ctx, a, MO_TE | MO_UQ, true); + return gen_fstore_idx(ctx, a, MO_UQ, true); } =20 static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a) @@ -435,7 +437,7 @@ static bool trans_th_fsurw(DisasContext *ctx, arg_th_me= midx *a) REQUIRE_XTHEADFMEMIDX(ctx); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - return gen_fstore_idx(ctx, a, MO_TE | MO_UL, true); + return gen_fstore_idx(ctx, a, MO_UL, true); } =20 /* XTheadFmv */ --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760111622; cv=none; d=zohomail.com; s=zohoarc; b=ebuE0HCsQVzvZ0ZAhmiaYjeCwtoIvP/WgQFO+fH4vZYHvxDFUs53tisIjGabrLUpDDf/hmDn4GOLTxOmVp0XMsLNuI+CggZblshIMC8UwelBY6M/Bz/LNpe0fMh1Eo2GTr2zWsWQirZbIMJRt9JDSSUPiEADm8bYgJSctiTl1EM= ARC-Message-Signature: i=1; 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Set it once in the callee. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_xthead.c.inc | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 859cbc26cb2..2f31842791e 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -926,6 +926,7 @@ static bool gen_loadpair_tl(DisasContext *ctx, arg_th_p= air *a, MemOp memop, addr1 =3D get_address(ctx, a->rs, imm); addr2 =3D get_address(ctx, a->rs, memop_size(memop) + imm); =20 + memop |=3D MO_TE; tcg_gen_qemu_ld_tl(t1, addr1, ctx->mem_idx, memop); tcg_gen_qemu_ld_tl(t2, addr2, ctx->mem_idx, memop); gen_set_gpr(ctx, a->rd1, t1); @@ -937,19 +938,19 @@ static bool trans_th_ldd(DisasContext *ctx, arg_th_pa= ir *a) { REQUIRE_XTHEADMEMPAIR(ctx); REQUIRE_64BIT(ctx); - return gen_loadpair_tl(ctx, a, MO_TE | MO_SQ, 4); + return gen_loadpair_tl(ctx, a, MO_SQ, 4); } =20 static bool trans_th_lwd(DisasContext *ctx, arg_th_pair *a) { REQUIRE_XTHEADMEMPAIR(ctx); - return gen_loadpair_tl(ctx, a, MO_TE | MO_SL, 3); + return gen_loadpair_tl(ctx, a, MO_SL, 3); } =20 static bool trans_th_lwud(DisasContext *ctx, arg_th_pair *a) { REQUIRE_XTHEADMEMPAIR(ctx); - return gen_loadpair_tl(ctx, a, MO_TE | MO_UL, 3); + return gen_loadpair_tl(ctx, a, MO_UL, 3); } =20 static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memo= p, @@ -964,6 +965,7 @@ static bool gen_storepair_tl(DisasContext *ctx, arg_th_= pair *a, MemOp memop, addr1 =3D get_address(ctx, a->rs, imm); addr2 =3D get_address(ctx, a->rs, memop_size(memop) + imm); =20 + memop |=3D MO_TE; tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop); tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop); return true; @@ -973,13 +975,13 @@ static bool trans_th_sdd(DisasContext *ctx, arg_th_pa= ir *a) { REQUIRE_XTHEADMEMPAIR(ctx); REQUIRE_64BIT(ctx); - return gen_storepair_tl(ctx, a, MO_TE | MO_SQ, 4); + return gen_storepair_tl(ctx, a, MO_SQ, 4); } =20 static bool trans_th_swd(DisasContext *ctx, arg_th_pair *a) { REQUIRE_XTHEADMEMPAIR(ctx); - return gen_storepair_tl(ctx, a, MO_TE | MO_SL, 3); + return gen_storepair_tl(ctx, a, MO_SL, 3); } =20 /* XTheadSync */ --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760111732; cv=none; d=zohomail.com; s=zohoarc; b=Jco6X+BHZrHchdaeJ5qz+k+Hz6yDRVfvQe3VAnn96lhz2Q2jRWd87ACxyrvc6F3rqAygEOiWNRYKdGwFJ9HTeYjGGEJ0cHSyU9fbgY3QgLZ+kuVcsw2WdJg13oe6JUSGkIL11Qu4OLud3n76Q9ACxLMXL9+f0q36tm38m+wt6RU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760111732; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/UOAMuWHFSXqGALj87y4eMXTkQjeecfZopjSv8ekkA0=; b=Vqynwx52HhT2lFS7j3sEz8imZxXOV5mSONWmPOjijs6RR3+4zq3zM+E5KCwDwzJcTYcsIT5dsr0d+UP3RLIp9moWiT90pkYRkn6WomjAIIx2qxTqtkvM0RPh+VtxUX4DVt3RFB/Fj8srsqWK2gKHvG18sA1G6I0FhB4CMM/q2cQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760111732440914.9383581514527; Fri, 10 Oct 2025 08:55:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v7FPM-0004EH-VQ; Fri, 10 Oct 2025 11:51:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v7FPK-0004DY-E5 for qemu-devel@nongnu.org; Fri, 10 Oct 2025 11:51:50 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v7FP8-0002c6-0w for qemu-devel@nongnu.org; Fri, 10 Oct 2025 11:51:50 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-46b303f7469so14163285e9.1 for ; Fri, 10 Oct 2025 08:51:35 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Set it once in the callees. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/translate.c | 1 + target/riscv/insn_trans/trans_rvzabha.c.inc | 2 +- target/riscv/insn_trans/trans_rvzacas.c.inc | 7 ++++--- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 94af9853cfe..2e6f39aa02d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1156,6 +1156,7 @@ static bool gen_cmpxchg(DisasContext *ctx, arg_atomic= *a, MemOp mop) TCGv src1 =3D get_address(ctx, a->rs1, 0); TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 + mop |=3D MO_TE; decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop); =20 diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc b/target/riscv/ins= n_trans/trans_rvzabha.c.inc index c1f99b65f09..302c63f2a3d 100644 --- a/target/riscv/insn_trans/trans_rvzabha.c.inc +++ b/target/riscv/insn_trans/trans_rvzabha.c.inc @@ -141,5 +141,5 @@ static bool trans_amocas_h(DisasContext *ctx, arg_amoca= s_h *a) { REQUIRE_ZACAS(ctx); REQUIRE_ZABHA(ctx); - return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TE | MO_SW); + return gen_cmpxchg(ctx, a, MO_ALIGN | MO_SW); } diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/ins= n_trans/trans_rvzacas.c.inc index 5e7c7c92b72..d850b142642 100644 --- a/target/riscv/insn_trans/trans_rvzacas.c.inc +++ b/target/riscv/insn_trans/trans_rvzacas.c.inc @@ -25,7 +25,7 @@ static bool trans_amocas_w(DisasContext *ctx, arg_amocas_w *a) { REQUIRE_ZACAS(ctx); - return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TE | MO_SL); + return gen_cmpxchg(ctx, a, MO_ALIGN | MO_SL); } =20 static TCGv_i64 get_gpr_pair(DisasContext *ctx, int reg_num) @@ -76,6 +76,7 @@ static bool gen_cmpxchg64(DisasContext *ctx, arg_atomic *= a, MemOp mop) TCGv src1 =3D get_address(ctx, a->rs1, 0); TCGv_i64 src2 =3D get_gpr_pair(ctx, a->rs2); =20 + mop |=3D MO_TE; decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); tcg_gen_atomic_cmpxchg_i64(dest, src1, dest, src2, ctx->mem_idx, mop); =20 @@ -88,10 +89,10 @@ static bool trans_amocas_d(DisasContext *ctx, arg_amoca= s_d *a) REQUIRE_ZACAS(ctx); switch (get_ol(ctx)) { case MXL_RV32: - return gen_cmpxchg64(ctx, a, MO_ALIGN | MO_TE | MO_UQ); + return gen_cmpxchg64(ctx, a, MO_ALIGN | MO_UQ); case MXL_RV64: case MXL_RV128: - return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TE | MO_UQ); + return gen_cmpxchg(ctx, a, MO_ALIGN | MO_UQ); default: g_assert_not_reached(); } --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760111752; cv=none; d=zohomail.com; s=zohoarc; b=QHB8JNzti9eGmI2Ggp9OU9q0yjMRFPgWQ36CoYCfowxQ79O8xoHn45q5xZ9eHCzlC25JPbMBe8K+UfcG8fIa3rRZMzNHkai6EHZDNx/bznP6+8YSRmvy8hjyKq4wShscrb755Kd02ty339blQzY4SQZ+QeJ4C1LPuQkL2xLNBGA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760111752; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=O+LjuonxLSezOOPsBu7D5T1RerWloURfdVhjBPrGFuk=; b=jteiOhjT4eWLb8nlPZPfrTXzR+jMN12GyzL75Ccl2hBRCVuZdmB7AgJlzQ6d8LnIAhgijYOlvCDzhWVWBRqiqZ7TcjHp1Zv5C+z2R9x9FkpETbEc8imHD4yYhE1WkoXfqb/oHfzxepBkEulzwtwR9B0+zFZpI5bPJngJXTQDDuY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760111752765667.8405777690148; Fri, 10 Oct 2025 08:55:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v7FPN-0004EJ-7X; Fri, 10 Oct 2025 11:51:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v7FPL-0004DQ-Fr for qemu-devel@nongnu.org; Fri, 10 Oct 2025 11:51:51 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v7FPE-0002d6-BS for qemu-devel@nongnu.org; Fri, 10 Oct 2025 11:51:49 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-46e2e363118so18674225e9.0 for ; Fri, 10 Oct 2025 08:51:40 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Set them once in the callees. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rva.c.inc | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index e0fbfafdde4..8737e8d60d1 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -34,6 +34,9 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemO= p mop) { TCGv src1; =20 + mop |=3D MO_ALIGN; + mop |=3D MO_TE; + decode_save_opc(ctx, 0); src1 =3D get_address(ctx, a->rs1, 0); if (a->rl) { @@ -61,6 +64,9 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemO= p mop) TCGLabel *l1 =3D gen_new_label(); TCGLabel *l2 =3D gen_new_label(); =20 + mop |=3D MO_ALIGN; + mop |=3D MO_TE; + decode_save_opc(ctx, 0); src1 =3D get_address(ctx, a->rs1, 0); tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); @@ -99,13 +105,13 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, M= emOp mop) static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a) { REQUIRE_A_OR_ZALRSC(ctx); - return gen_lr(ctx, a, (MO_ALIGN | MO_TE | MO_SL)); + return gen_lr(ctx, a, MO_SL); } =20 static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a) { REQUIRE_A_OR_ZALRSC(ctx); - return gen_sc(ctx, a, (MO_ALIGN | MO_TE | MO_SL)); + return gen_sc(ctx, a, MO_SL); } =20 static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a) @@ -166,14 +172,14 @@ static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZALRSC(ctx); - return gen_lr(ctx, a, MO_ALIGN | MO_TE | MO_UQ); + return gen_lr(ctx, a, MO_UQ); } =20 static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a) { REQUIRE_64BIT(ctx); REQUIRE_A_OR_ZALRSC(ctx); - return gen_sc(ctx, a, (MO_ALIGN | MO_TE | MO_UQ)); + return gen_sc(ctx, a, MO_UQ); } =20 static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a) --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760111622; cv=none; d=zohomail.com; s=zohoarc; b=MtpIlAamng9shhWz/WRP7qdoMt/wQ6f6dVUd7HVfkWciBdRdihhuFWkh9tUjdhB6NhGnUkfpwYHRJ0k0Scgsmmypm8JpRq3yHiZGuzKXVTVLObZ2JX/euk5U9OQY9bOTAIqWKWhKSTF2ZGm8gKh8D6dajrjOF87ZxJnLjuH9auA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760111622; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7nRDMITnOJutiilVWlAwBIw5yUEex1aWcchZayOCLRA=; b=OvXrQKuOV8daclep8bsjGPdZzoKj2Q6MCnj7ZlJhsYOdGFr3/KJDXn5pJ8F1AexIMHUhlQexa5QARB0IukIqCevgqyRoqoHt8m9WQ4R9SnaNGb1J66qzNeGnO2nV51dXxA2gyX8iTGRbPXIqy6ZFMVVwl2VnglI4XJaYfoaiwEM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760111622358493.9667704124954; Fri, 10 Oct 2025 08:53:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v7FPT-0004H1-Eo; Fri, 10 Oct 2025 11:51:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v7FPP-0004F5-1W for qemu-devel@nongnu.org; Fri, 10 Oct 2025 11:51:55 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v7FPH-0002hv-FL for qemu-devel@nongnu.org; Fri, 10 Oct 2025 11:51:53 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-3ee15b5435bso1359708f8f.0 for ; Fri, 10 Oct 2025 08:51:44 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvd.c.inc | 6 ++++-- target/riscv/insn_trans/trans_rvf.c.inc | 6 ++++-- target/riscv/insn_trans/trans_rvzacas.c.inc | 5 +++-- target/riscv/insn_trans/trans_rvzce.c.inc | 6 ++++-- target/riscv/insn_trans/trans_rvzfh.c.inc | 8 ++++++-- target/riscv/insn_trans/trans_rvzicfiss.c.inc | 10 ++++++---- 6 files changed, 27 insertions(+), 14 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 33858206788..62b75358158 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -42,7 +42,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) { TCGv addr; - MemOp memop =3D MO_TE | MO_UQ; + MemOp memop =3D MO_UQ; =20 REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); @@ -60,6 +60,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) } else { memop |=3D MO_ATOM_IFALIGN; } + memop |=3D MO_TE; =20 decode_save_opc(ctx, 0); addr =3D get_address(ctx, a->rs1, a->imm); @@ -72,7 +73,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) static bool trans_fsd(DisasContext *ctx, arg_fsd *a) { TCGv addr; - MemOp memop =3D MO_TE | MO_UQ; + MemOp memop =3D MO_UQ; =20 REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); @@ -84,6 +85,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) } else { memop |=3D MO_ATOM_IFALIGN; } + memop |=3D MO_TE; =20 decode_save_opc(ctx, 0); addr =3D get_address(ctx, a->rs1, a->imm); diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index 150e2b9a7d4..878417eae92 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -43,11 +43,12 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) { TCGv_i64 dest; TCGv addr; - MemOp memop =3D MO_TE | MO_UL; + MemOp memop =3D MO_UL; =20 REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 + memop |=3D MO_TE; if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } @@ -65,11 +66,12 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) static bool trans_fsw(DisasContext *ctx, arg_fsw *a) { TCGv addr; - MemOp memop =3D MO_TE | MO_UL; + MemOp memop =3D MO_UL; =20 REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 + memop |=3D MO_TE; if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/ins= n_trans/trans_rvzacas.c.inc index d850b142642..6458ac4f241 100644 --- a/target/riscv/insn_trans/trans_rvzacas.c.inc +++ b/target/riscv/insn_trans/trans_rvzacas.c.inc @@ -119,12 +119,13 @@ static bool trans_amocas_q(DisasContext *ctx, arg_amo= cas_q *a) TCGv_i64 src2h =3D get_gpr(ctx, a->rs2 =3D=3D 0 ? 0 : a->rs2 + 1, EXT_= NONE); TCGv_i64 destl =3D get_gpr(ctx, a->rd, EXT_NONE); TCGv_i64 desth =3D get_gpr(ctx, a->rd =3D=3D 0 ? 0 : a->rd + 1, EXT_NO= NE); + MemOp memop =3D MO_ALIGN | MO_UO; =20 + memop |=3D MO_TE; tcg_gen_concat_i64_i128(src2, src2l, src2h); tcg_gen_concat_i64_i128(dest, destl, desth); decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); - tcg_gen_atomic_cmpxchg_i128(dest, src1, dest, src2, ctx->mem_idx, - (MO_ALIGN | MO_TE | MO_UO)); + tcg_gen_atomic_cmpxchg_i128(dest, src1, dest, src2, ctx->mem_idx, memo= p); =20 tcg_gen_extr_i128_i64(destl, desth, dest); =20 diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_= trans/trans_rvzce.c.inc index c8dc102c8e3..172c2c19c17 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -175,7 +175,7 @@ static bool gen_pop(DisasContext *ctx, arg_cmpp *a, boo= l ret, bool ret_val) return false; } =20 - MemOp memop =3D get_ol(ctx) =3D=3D MXL_RV32 ? MO_TE | MO_UL : MO_TE | = MO_UQ; + MemOp memop =3D get_ol(ctx) =3D=3D MXL_RV32 ? MO_UL : MO_UQ; int reg_size =3D memop_size(memop); target_ulong stack_adj =3D ROUND_UP(ctpop32(reg_bitmap) * reg_size, 16= ) + a->spimm; @@ -185,6 +185,7 @@ static bool gen_pop(DisasContext *ctx, arg_cmpp *a, boo= l ret, bool ret_val) =20 tcg_gen_addi_tl(addr, sp, stack_adj - reg_size); =20 + memop |=3D MO_TE; for (i =3D X_Sn + 11; i >=3D 0; i--) { if (reg_bitmap & (1 << i)) { TCGv dest =3D dest_gpr(ctx, i); @@ -228,7 +229,7 @@ static bool trans_cm_push(DisasContext *ctx, arg_cm_pus= h *a) return false; } =20 - MemOp memop =3D get_ol(ctx) =3D=3D MXL_RV32 ? MO_TE | MO_UL : MO_TE | = MO_UQ; + MemOp memop =3D get_ol(ctx) =3D=3D MXL_RV32 ? MO_UL : MO_UQ; int reg_size =3D memop_size(memop); target_ulong stack_adj =3D ROUND_UP(ctpop32(reg_bitmap) * reg_size, 16= ) + a->spimm; @@ -238,6 +239,7 @@ static bool trans_cm_push(DisasContext *ctx, arg_cm_pus= h *a) =20 tcg_gen_subi_tl(addr, sp, reg_size); =20 + memop |=3D MO_TE; for (i =3D X_Sn + 11; i >=3D 0; i--) { if (reg_bitmap & (1 << i)) { TCGv val =3D get_gpr(ctx, i, EXT_NONE); diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_= trans/trans_rvzfh.c.inc index eec478afcb0..5355cd46c3d 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -42,12 +42,14 @@ =20 static bool trans_flh(DisasContext *ctx, arg_flh *a) { + MemOp memop =3D MO_UW; TCGv_i64 dest; TCGv t0; =20 REQUIRE_FPU; REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); =20 + memop |=3D MO_TE; decode_save_opc(ctx, 0); t0 =3D get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { @@ -57,7 +59,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) } =20 dest =3D cpu_fpr[a->rd]; - tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, MO_TE | MO_UW); + tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, memop); gen_nanbox_h(dest, dest); =20 mark_fs_dirty(ctx); @@ -66,11 +68,13 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) =20 static bool trans_fsh(DisasContext *ctx, arg_fsh *a) { + MemOp memop =3D MO_UW; TCGv t0; =20 REQUIRE_FPU; REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); =20 + memop |=3D MO_TE; decode_save_opc(ctx, 0); t0 =3D get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { @@ -79,7 +83,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) t0 =3D temp; } =20 - tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TE | MO_UW); + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, memop); =20 return true; } diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/i= nsn_trans/trans_rvzicfiss.c.inc index c5555966175..89eed007587 100644 --- a/target/riscv/insn_trans/trans_rvzicfiss.c.inc +++ b/target/riscv/insn_trans/trans_rvzicfiss.c.inc @@ -100,12 +100,13 @@ static bool trans_ssamoswap_w(DisasContext *ctx, arg_= amoswap_w *a) =20 TCGv dest =3D dest_gpr(ctx, a->rd); TCGv src1, src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); + MemOp memop =3D MO_ALIGN | MO_SL; =20 decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); src1 =3D get_address(ctx, a->rs1, 0); =20 - tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), - (MO_ALIGN | MO_TE | MO_SL)); + memop |=3D MO_TE; + tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), memop); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -129,12 +130,13 @@ static bool trans_ssamoswap_d(DisasContext *ctx, arg_= amoswap_w *a) =20 TCGv dest =3D dest_gpr(ctx, a->rd); TCGv src1, src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); + MemOp memop =3D MO_ALIGN | MO_SQ; =20 decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); src1 =3D get_address(ctx, a->rs1, 0); =20 - tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), - (MO_ALIGN | MO_TE | MO_SQ)); + memop |=3D MO_TE; + tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), memop); gen_set_gpr(ctx, a->rd, dest); return true; } --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Heinrich Schuchardt Reviewed-by: Richard Henderson --- target/riscv/translate.c | 18 +++++++++++++++--- target/riscv/insn_trans/trans_rva.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvd.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvf.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvzacas.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvzce.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvzfh.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvzicfiss.c.inc | 4 ++-- target/riscv/insn_trans/trans_xthead.c.inc | 16 ++++++++-------- 10 files changed, 39 insertions(+), 27 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2e6f39aa02d..e1f4dc5ffd0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -126,6 +126,18 @@ static inline bool has_ext(DisasContext *ctx, uint32_t= ext) return ctx->misa_ext & ext; } =20 +static inline MemOp mo_endian(DisasContext *ctx) +{ + /* + * A couple of bits in MSTATUS set the endianness: + * - MSTATUS_UBE (User-mode), + * - MSTATUS_SBE (Supervisor-mode), + * - MSTATUS_MBE (Machine-mode) + * but we don't implement that yet. + */ + return MO_TE; +} + #ifdef TARGET_RISCV32 #define get_xl(ctx) MXL_RV32 #elif defined(CONFIG_USER_ONLY) @@ -142,7 +154,7 @@ static inline bool has_ext(DisasContext *ctx, uint32_t = ext) #define get_address_xl(ctx) ((ctx)->address_xl) #endif =20 -#define mxl_memop(ctx) ((get_xl(ctx) + 1) | MO_TE) +#define mxl_memop(ctx) ((get_xl(ctx) + 1) | mo_endian(ctx)) =20 /* The word size for this machine mode. */ static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) @@ -1135,7 +1147,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, TCGv src1, src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); MemOp size =3D mop & MO_SIZE; =20 - mop |=3D MO_TE; + mop |=3D mo_endian(ctx); if (ctx->cfg_ptr->ext_zama16b && size >=3D MO_32) { mop |=3D MO_ATOM_WITHIN16; } else { @@ -1156,7 +1168,7 @@ static bool gen_cmpxchg(DisasContext *ctx, arg_atomic= *a, MemOp mop) TCGv src1 =3D get_address(ctx, a->rs1, 0); TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 - mop |=3D MO_TE; + mop |=3D mo_endian(ctx); decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop); =20 diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index 8737e8d60d1..a7a3278d242 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -35,7 +35,7 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemO= p mop) TCGv src1; =20 mop |=3D MO_ALIGN; - mop |=3D MO_TE; + mop |=3D mo_endian(ctx); =20 decode_save_opc(ctx, 0); src1 =3D get_address(ctx, a->rs1, 0); @@ -65,7 +65,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemO= p mop) TCGLabel *l2 =3D gen_new_label(); =20 mop |=3D MO_ALIGN; - mop |=3D MO_TE; + mop |=3D mo_endian(ctx); =20 decode_save_opc(ctx, 0); src1 =3D get_address(ctx, a->rs1, 0); diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 62b75358158..ffea0c2a1f9 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -60,7 +60,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) } else { memop |=3D MO_ATOM_IFALIGN; } - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); =20 decode_save_opc(ctx, 0); addr =3D get_address(ctx, a->rs1, a->imm); @@ -85,7 +85,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) } else { memop |=3D MO_ATOM_IFALIGN; } - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); =20 decode_save_opc(ctx, 0); addr =3D get_address(ctx, a->rs1, a->imm); diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index 878417eae92..89fb0f604ad 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -48,7 +48,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } @@ -71,7 +71,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 8db3e78baab..a6fe912b30c 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -404,7 +404,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemO= p memop) { bool out; =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } @@ -508,7 +508,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a= , MemOp memop) =20 static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) { - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/ins= n_trans/trans_rvzacas.c.inc index 6458ac4f241..8d94b83ce94 100644 --- a/target/riscv/insn_trans/trans_rvzacas.c.inc +++ b/target/riscv/insn_trans/trans_rvzacas.c.inc @@ -76,7 +76,7 @@ static bool gen_cmpxchg64(DisasContext *ctx, arg_atomic *= a, MemOp mop) TCGv src1 =3D get_address(ctx, a->rs1, 0); TCGv_i64 src2 =3D get_gpr_pair(ctx, a->rs2); =20 - mop |=3D MO_TE; + mop |=3D mo_endian(ctx); decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); tcg_gen_atomic_cmpxchg_i64(dest, src1, dest, src2, ctx->mem_idx, mop); =20 @@ -121,7 +121,7 @@ static bool trans_amocas_q(DisasContext *ctx, arg_amoca= s_q *a) TCGv_i64 desth =3D get_gpr(ctx, a->rd =3D=3D 0 ? 0 : a->rd + 1, EXT_NO= NE); MemOp memop =3D MO_ALIGN | MO_UO; =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); tcg_gen_concat_i64_i128(src2, src2l, src2h); tcg_gen_concat_i64_i128(dest, destl, desth); decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_= trans/trans_rvzce.c.inc index 172c2c19c17..0d3ba40e52a 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -185,7 +185,7 @@ static bool gen_pop(DisasContext *ctx, arg_cmpp *a, boo= l ret, bool ret_val) =20 tcg_gen_addi_tl(addr, sp, stack_adj - reg_size); =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); for (i =3D X_Sn + 11; i >=3D 0; i--) { if (reg_bitmap & (1 << i)) { TCGv dest =3D dest_gpr(ctx, i); @@ -239,7 +239,7 @@ static bool trans_cm_push(DisasContext *ctx, arg_cm_pus= h *a) =20 tcg_gen_subi_tl(addr, sp, reg_size); =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); for (i =3D X_Sn + 11; i >=3D 0; i--) { if (reg_bitmap & (1 << i)) { TCGv val =3D get_gpr(ctx, i, EXT_NONE); diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_= trans/trans_rvzfh.c.inc index 5355cd46c3d..791ee51f652 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -49,7 +49,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) REQUIRE_FPU; REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); decode_save_opc(ctx, 0); t0 =3D get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { @@ -74,7 +74,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) REQUIRE_FPU; REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); decode_save_opc(ctx, 0); t0 =3D get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/i= nsn_trans/trans_rvzicfiss.c.inc index 89eed007587..0b6ad57965c 100644 --- a/target/riscv/insn_trans/trans_rvzicfiss.c.inc +++ b/target/riscv/insn_trans/trans_rvzicfiss.c.inc @@ -105,7 +105,7 @@ static bool trans_ssamoswap_w(DisasContext *ctx, arg_am= oswap_w *a) decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); src1 =3D get_address(ctx, a->rs1, 0); =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), memop); gen_set_gpr(ctx, a->rd, dest); return true; @@ -135,7 +135,7 @@ static bool trans_ssamoswap_d(DisasContext *ctx, arg_am= oswap_w *a) decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); src1 =3D get_address(ctx, a->rs1, 0); =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), memop); gen_set_gpr(ctx, a->rd, dest); return true; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index 2f31842791e..f8b95c6498b 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -349,7 +349,7 @@ static bool gen_fload_idx(DisasContext *ctx, arg_th_mem= idx *a, MemOp memop, TCGv_i64 rd =3D cpu_fpr[a->rd]; TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop); if ((memop & MO_SIZE) =3D=3D MO_32) { gen_nanbox_s(rd, rd); @@ -370,7 +370,7 @@ static bool gen_fstore_idx(DisasContext *ctx, arg_th_me= midx *a, MemOp memop, TCGv_i64 rd =3D cpu_fpr[a->rd]; TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop); =20 return true; @@ -570,7 +570,7 @@ static bool gen_load_inc(DisasContext *ctx, arg_th_memi= nc *a, MemOp memop, TCGv rd =3D dest_gpr(ctx, a->rd); TCGv rs1 =3D get_gpr(ctx, a->rs1, EXT_NONE); =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); tcg_gen_addi_tl(rs1, rs1, imm); gen_set_gpr(ctx, a->rd, rd); @@ -591,7 +591,7 @@ static bool gen_store_inc(DisasContext *ctx, arg_th_mem= inc *a, MemOp memop, TCGv data =3D get_gpr(ctx, a->rd, EXT_NONE); TCGv rs1 =3D get_gpr(ctx, a->rs1, EXT_NONE); =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); tcg_gen_addi_tl(rs1, rs1, imm); gen_set_gpr(ctx, a->rs1, rs1); @@ -747,7 +747,7 @@ static bool gen_load_idx(DisasContext *ctx, arg_th_memi= dx *a, MemOp memop, TCGv rd =3D dest_gpr(ctx, a->rd); TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); gen_set_gpr(ctx, a->rd, rd); =20 @@ -765,7 +765,7 @@ static bool gen_store_idx(DisasContext *ctx, arg_th_mem= idx *a, MemOp memop, TCGv data =3D get_gpr(ctx, a->rd, EXT_NONE); TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); =20 return true; @@ -926,7 +926,7 @@ static bool gen_loadpair_tl(DisasContext *ctx, arg_th_p= air *a, MemOp memop, addr1 =3D get_address(ctx, a->rs, imm); addr2 =3D get_address(ctx, a->rs, memop_size(memop) + imm); =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); tcg_gen_qemu_ld_tl(t1, addr1, ctx->mem_idx, memop); tcg_gen_qemu_ld_tl(t2, addr2, ctx->mem_idx, memop); gen_set_gpr(ctx, a->rd1, t1); @@ -965,7 +965,7 @@ static bool gen_storepair_tl(DisasContext *ctx, arg_th_= pair *a, MemOp memop, addr1 =3D get_address(ctx, a->rs, imm); addr2 =3D get_address(ctx, a->rs, memop_size(memop) + imm); =20 - memop |=3D MO_TE; + memop |=3D mo_endian(ctx); tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop); tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop); return true; --=20 2.51.0 From nobody Fri Nov 14 18:17:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Heinrich Schuchardt --- target/riscv/op_helper.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index c486f771d35..9d048089e2a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -28,6 +28,18 @@ #include "exec/tlb-flags.h" #include "trace.h" =20 +static inline MemOp mo_endian_env(CPURISCVState *env) +{ + /* + * A couple of bits in MSTATUS set the endianness: + * - MSTATUS_UBE (User-mode), + * - MSTATUS_SBE (Supervisor-mode), + * - MSTATUS_MBE (Machine-mode) + * but we don't implement that yet. + */ + return MO_TE; +} + /* Exceptions processing helpers */ G_NORETURN void riscv_raise_exception(CPURISCVState *env, RISCVException exception, @@ -633,7 +645,7 @@ target_ulong helper_hyp_hlv_hu(CPURISCVState *env, targ= et_ulong addr) { uintptr_t ra =3D GETPC(); int mmu_idx =3D check_access_hlsv(env, false, ra); - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UW, mmu_idx); + MemOpIdx oi =3D make_memop_idx(mo_endian_env(env) | MO_UW, mmu_idx); =20 return cpu_ldw_mmu(env, adjust_addr_virt(env, addr), oi, ra); } @@ -642,7 +654,7 @@ target_ulong helper_hyp_hlv_wu(CPURISCVState *env, targ= et_ulong addr) { uintptr_t ra =3D GETPC(); int mmu_idx =3D check_access_hlsv(env, false, ra); - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL, mmu_idx); + MemOpIdx oi =3D make_memop_idx(mo_endian_env(env) | MO_UL, mmu_idx); =20 return cpu_ldl_mmu(env, adjust_addr_virt(env, addr), oi, ra); } @@ -651,7 +663,7 @@ target_ulong helper_hyp_hlv_d(CPURISCVState *env, targe= t_ulong addr) { uintptr_t ra =3D GETPC(); int mmu_idx =3D check_access_hlsv(env, false, ra); - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UQ, mmu_idx); + MemOpIdx oi =3D make_memop_idx(mo_endian_env(env) | MO_UQ, mmu_idx); =20 return cpu_ldq_mmu(env, adjust_addr_virt(env, addr), oi, ra); } @@ -669,7 +681,7 @@ void helper_hyp_hsv_h(CPURISCVState *env, target_ulong = addr, target_ulong val) { uintptr_t ra =3D GETPC(); int mmu_idx =3D check_access_hlsv(env, false, ra); - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UW, mmu_idx); + MemOpIdx oi =3D make_memop_idx(mo_endian_env(env) | MO_UW, mmu_idx); =20 cpu_stw_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); } @@ -678,7 +690,7 @@ void helper_hyp_hsv_w(CPURISCVState *env, target_ulong = addr, target_ulong val) { uintptr_t ra =3D GETPC(); int mmu_idx =3D check_access_hlsv(env, false, ra); - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL, mmu_idx); + MemOpIdx oi =3D make_memop_idx(mo_endian_env(env) | MO_UL, mmu_idx); =20 cpu_stl_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); } @@ -687,7 +699,7 @@ void helper_hyp_hsv_d(CPURISCVState *env, target_ulong = addr, target_ulong val) { uintptr_t ra =3D GETPC(); int mmu_idx =3D check_access_hlsv(env, false, ra); - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UQ, mmu_idx); + MemOpIdx oi =3D make_memop_idx(mo_endian_env(env) | MO_UQ, mmu_idx); =20 cpu_stq_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); } @@ -703,7 +715,7 @@ target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, tar= get_ulong addr) { uintptr_t ra =3D GETPC(); int mmu_idx =3D check_access_hlsv(env, true, ra); - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UW, mmu_idx); + MemOpIdx oi =3D make_memop_idx(mo_endian_env(env) | MO_UW, mmu_idx); =20 return cpu_ldw_code_mmu(env, addr, oi, GETPC()); } @@ -712,7 +724,7 @@ target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, tar= get_ulong addr) { uintptr_t ra =3D GETPC(); int mmu_idx =3D check_access_hlsv(env, true, ra); - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL, mmu_idx); + MemOpIdx oi =3D make_memop_idx(mo_endian_env(env) | MO_UL, mmu_idx); =20 return cpu_ldl_code_mmu(env, addr, oi, ra); } --=20 2.51.0