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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-426ce583316sm4221657f8f.20.2025.10.10.06.06.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Oct 2025 06:06:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1760101606; x=1760706406; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=j0iNpEPyOXoxR+HD7jDgER++00Zbwcp5HlXjOGIfHEU=; b=iBBjw/HTOpymW8i9dXCoiHNpdYOu9UkNHnYEejd8HDvCgRfkJfOmFZ4mEcsqVj8+Tf oAt+jDeExpcvTDdu760Lfsn02BNvbVoBjbGv8wtmvFZKy3izrfdOsmLQJW4tJoSOEFLL SKNf70Lv6UXKKuEZ0XjW6c4pl/A7qhdfeqI62Gl8ntlEJpY8H6hj1eCLi/IgLwGrZqeh hKZt5Udt3SzCRohd1qTLOXI8bvcjvNsk4/gasNexPbRUXT+dgHxFsBIg771SDlN7Xs7r hDeYkzYtEeOWV33pItrTPpyGOj/eR4uwvNTWOIZn5EfLODTbLgQGVMLjyWhY1U/n2b2d gxbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760101606; x=1760706406; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j0iNpEPyOXoxR+HD7jDgER++00Zbwcp5HlXjOGIfHEU=; b=wyzLqea4v/8fksPddyoJz1APzUb7fsrgUvt4H2u0/j4mtdbbUxOXspg2OjRJjPYACX 3KtdJ+pwdw7A8ylL3JbmD4TwzM0V34tvH7QJ7KkKl/iwM8585/hH9BYOOLGAMDXOstfN qbE5EfUQ3XKWteBfheXT7w7NrGIzz78ZRCQB9SnFPDr2HfLMoRYTvQOpppnNeBtV78ld GQgo2CL5FfULvz1dwrFzXvf2FvOVqB01PQoHvCPRrGyuRmNRxLRTfZZ6qAhLRvUTOps9 J6vUWQEYICr0QB3FLsxJQLt6D0XY/4yxLSnpLiISBQWMb+eM4Ih1nCCZdkDPeN63G4Rl 3L7g== X-Gm-Message-State: AOJu0Ywo2tkRbHUdvZaCKJRxxN64ZQ/PfnZZJrscfgRqRCgPSlnoAq5+ LnqKmWzXHQfQwxNaxdj9yYodqC4+XgBF24NOZVYLmQsTURPFzCKqtYhJDvyj9caxf0gYgrVQPjW FtQIl X-Gm-Gg: ASbGnctMohOkU+qCc6q8SNQMztAzwuzPUI5aaduOa/anYIi447ZGEbtFylOf/W++hBa WD/EMqtfacI7VVuHYw5x5YsQKgBwqaNgmeJY1dNwlNs7WCuR/CRrXxU+eO35Ah7ZzJVi5HJyOv9 VD18lcwX/Hkl63/CnXvqkXvIQxtALNHEhMOADSsJt0A6BJa6Ubf3IAKSO7J3PdUiyTz8xmcai2D wikxpaJ1hYyLL7FTVUUd5OlQt22swOQbRa7Zdi0xVOEi2gZiIVXcUgmysCrvH5k2TKYTipJbrJT sc1zMd3iRGhhbnuuLu9I3s1GKSd75ZN5DCeRGWeCERpGc1j7Z1h3HfYzYF8eF60xTrntI8qjAmB Xe2WZPw3K8G+ro1vwMqnNWEL0wv5XhlmDurFSAr7fN23pSapebnM= X-Google-Smtp-Source: AGHT+IHouSz6WizVy+7+iM0oXDtlpmujPA+EG7ZiKu0LB1y3O8T9A5WHtKMRDFv78HqVYJUJyqUh9g== X-Received: by 2002:a05:6000:2305:b0:3e9:9f7f:6c36 with SMTP id ffacd0b85a97d-4266e8db5f6mr6843595f8f.54.1760101605967; Fri, 10 Oct 2025 06:06:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 69/76] linux-user/aarch64: Generate GCS signal records Date: Fri, 10 Oct 2025 14:05:20 +0100 Message-ID: <20251010130527.3921602-70-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251010130527.3921602-1-peter.maydell@linaro.org> References: <20251010130527.3921602-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760102815276154100 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Here we must push and pop a cap on the GCS stack as well as the gcs record on the normal stack. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20251008215613.300150-70-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/aarch64/signal.c | 138 ++++++++++++++++++++++++++++++++++-- 1 file changed, 132 insertions(+), 6 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index ef97be3ac7b..f7edfa249e5 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -22,6 +22,7 @@ #include "signal-common.h" #include "linux-user/trace.h" #include "target/arm/cpu-features.h" +#include "gcs-internal.h" =20 struct target_sigcontext { uint64_t fault_address; @@ -152,6 +153,16 @@ struct target_zt_context { QEMU_BUILD_BUG_ON(TARGET_ZT_SIG_REG_BYTES !=3D \ sizeof_field(CPUARMState, za_state.zt0)); =20 +#define TARGET_GCS_MAGIC 0x47435300 +#define GCS_SIGNAL_CAP(X) ((X) & TARGET_PAGE_MASK) + +struct target_gcs_context { + struct target_aarch64_ctx head; + uint64_t gcspr; + uint64_t features_enabled; + uint64_t reserved; +}; + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -322,6 +333,35 @@ static void target_setup_zt_record(struct target_zt_co= ntext *zt, } } =20 +static bool target_setup_gcs_record(struct target_gcs_context *ctx, + CPUARMState *env, uint64_t return_addr) +{ + uint64_t mode =3D gcs_get_el0_mode(env); + uint64_t gcspr =3D env->cp15.gcspr_el[0]; + + if (mode & PR_SHADOW_STACK_ENABLE) { + /* Push a cap for the signal frame. */ + gcspr -=3D 8; + if (put_user_u64(GCS_SIGNAL_CAP(gcspr), gcspr)) { + return false; + } + + /* Push a gcs entry for the trampoline. */ + if (put_user_u64(return_addr, gcspr - 8)) { + return false; + } + env->cp15.gcspr_el[0] =3D gcspr - 8; + } + + __put_user(TARGET_GCS_MAGIC, &ctx->head.magic); + __put_user(sizeof(*ctx), &ctx->head.size); + __put_user(gcspr, &ctx->gcspr); + __put_user(mode, &ctx->features_enabled); + __put_user(0, &ctx->reserved); + + return true; +} + static void target_restore_general_frame(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -502,6 +542,64 @@ static bool target_restore_zt_record(CPUARMState *env, return true; } =20 +static bool target_restore_gcs_record(CPUARMState *env, + struct target_gcs_context *ctx, + bool *rebuild_hflags) +{ + TaskState *ts =3D get_task_state(env_cpu(env)); + uint64_t cur_mode =3D gcs_get_el0_mode(env); + uint64_t new_mode, gcspr; + + __get_user(new_mode, &ctx->features_enabled); + __get_user(gcspr, &ctx->gcspr); + + /* + * The kernel pushes the value through the hw register: + * write_sysreg_s(gcspr, SYS_GCSPR_EL0) in restore_gcs_context, + * then read_sysreg_s(SYS_GCSPR_EL0) in gcs_restore_signal. + * Since the bottom 3 bits are RES0, this can (CONSTRAINED UNPREDICTAB= LE) + * force align the value. Mirror the choice from gcspr_write(). + */ + gcspr &=3D ~7; + + if (new_mode & ~(PR_SHADOW_STACK_ENABLE | + PR_SHADOW_STACK_WRITE | + PR_SHADOW_STACK_PUSH)) { + return false; + } + if ((new_mode ^ cur_mode) & ts->gcs_el0_locked) { + return false; + } + if (new_mode & ~cur_mode & PR_SHADOW_STACK_ENABLE) { + return false; + } + + if (new_mode & PR_SHADOW_STACK_ENABLE) { + uint64_t cap; + + /* Pop and clear the signal cap. */ + if (get_user_u64(cap, gcspr)) { + return false; + } + if (cap !=3D GCS_SIGNAL_CAP(gcspr)) { + return false; + } + if (put_user_u64(0, gcspr)) { + return false; + } + gcspr +=3D 8; + } else { + new_mode =3D 0; + } + + env->cp15.gcspr_el[0] =3D gcspr; + if (new_mode !=3D cur_mode) { + *rebuild_hflags =3D true; + gcs_set_el0_mode(env, new_mode); + } + return true; +} + static int target_restore_sigframe(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -511,8 +609,10 @@ static int target_restore_sigframe(CPUARMState *env, struct target_za_context *za =3D NULL; struct target_tpidr2_context *tpidr2 =3D NULL; struct target_zt_context *zt =3D NULL; + struct target_gcs_context *gcs =3D NULL; uint64_t extra_datap =3D 0; bool used_extra =3D false; + bool rebuild_hflags =3D false; int sve_size =3D 0; int za_size =3D 0; int zt_size =3D 0; @@ -582,6 +682,15 @@ static int target_restore_sigframe(CPUARMState *env, zt_size =3D size; break; =20 + case TARGET_GCS_MAGIC: + if (gcs + || size !=3D sizeof(struct target_gcs_context) + || !cpu_isar_feature(aa64_gcs, env_archcpu(env))) { + goto err; + } + gcs =3D (struct target_gcs_context *)ctx; + break; + case TARGET_EXTRA_MAGIC: if (extra || size !=3D sizeof(struct target_extra_context)) { goto err; @@ -612,6 +721,10 @@ static int target_restore_sigframe(CPUARMState *env, goto err; } =20 + if (gcs && !target_restore_gcs_record(env, gcs, &rebuild_hflags)) { + goto err; + } + /* SVE data, if present, overwrites FPSIMD data. */ if (sve && !target_restore_sve_record(env, sve, sve_size, &svcr)) { goto err; @@ -631,6 +744,9 @@ static int target_restore_sigframe(CPUARMState *env, } if (env->svcr !=3D svcr) { env->svcr =3D svcr; + rebuild_hflags =3D true; + } + if (rebuild_hflags) { arm_rebuild_hflags(env); } unlock_user(extra, extra_datap, 0); @@ -701,7 +817,7 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, uc.tuc_mcontext.__reserved), }; int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0, tpidr2_ofs =3D 0; - int zt_ofs =3D 0, esr_ofs =3D 0; + int zt_ofs =3D 0, esr_ofs =3D 0, gcs_ofs =3D 0; int sve_size =3D 0, za_size =3D 0, tpidr2_size =3D 0, zt_size =3D 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; @@ -720,6 +836,11 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, &layout); } =20 + if (env->cp15.gcspr_el[0]) { + gcs_ofs =3D alloc_sigframe_space(sizeof(struct target_gcs_context), + &layout); + } + /* SVE state needs saving only if it exists. */ if (cpu_isar_feature(aa64_sve, env_archcpu(env)) || cpu_isar_feature(aa64_sme, env_archcpu(env))) { @@ -779,6 +900,12 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, goto give_sigsegv; } =20 + if (ka->sa_flags & TARGET_SA_RESTORER) { + return_addr =3D ka->sa_restorer; + } else { + return_addr =3D default_rt_sigreturn; + } + target_setup_general_frame(frame, env, set); target_setup_fpsimd_record((void *)frame + fpsimd_ofs, env); if (esr_ofs) { @@ -786,6 +913,10 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, /* Leave ESR_EL1 clear while it's not relevant. */ env->cp15.esr_el[1] =3D 0; } + if (gcs_ofs && + !target_setup_gcs_record((void *)frame + gcs_ofs, env, return_addr= )) { + goto give_sigsegv; + } target_setup_end_record((void *)frame + layout.std_end_ofs); if (layout.extra_ofs) { target_setup_extra_record((void *)frame + layout.extra_ofs, @@ -811,11 +942,6 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, __put_user(env->xregs[29], &fr->fp); __put_user(env->xregs[30], &fr->lr); =20 - if (ka->sa_flags & TARGET_SA_RESTORER) { - return_addr =3D ka->sa_restorer; - } else { - return_addr =3D default_rt_sigreturn; - } env->xregs[0] =3D usig; env->xregs[29] =3D frame_addr + fr_ofs; env->xregs[30] =3D return_addr; --=20 2.43.0