From nobody Fri Nov 14 20:45:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760102167; cv=none; d=zohomail.com; s=zohoarc; b=Lc4opPhbbBlnb4UrsSnWK1NXuqNVIbkAemOhdyArmVgCnIzetjgA4sS6XCOkPRZyyH+E48IHfnzEtQmrasP/SJnm76zRVaJi7mpM9N9xD2lR+cL0fBKDY/spFgBIpdAgjYIvv3bUqeylGK+YV/TWlFIHXE7ZfcHwQF9WLXpMzeg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760102167; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=fy6Nmaf+Hy4K6iUgM9jgvpsvnnLpWkOyEh230NdUHFE=; b=X59LBxKwrStFnIANRgpjiaa4eELXc07kbTG1EI5HEr0Hv/BGB4qO1TwD14YXjzB61OEKuSUCZwW8ig9qILQkLBIrKP2gTOHveXd7cwJ2syu2FSmgAMaWUzanxN6C2hTGyX8I8ArePkhcqwauP3Zxv6c7giLn1zKczAJ7EjX8t1w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760102167236642.6504973087405; Fri, 10 Oct 2025 06:16:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v7Cpp-0006Uw-KG; Fri, 10 Oct 2025 09:07:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v7Cpc-0006Px-7G for qemu-devel@nongnu.org; Fri, 10 Oct 2025 09:06:50 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v7Cp0-0003ux-JX for qemu-devel@nongnu.org; Fri, 10 Oct 2025 09:06:46 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-46e42deffa8so18560315e9.0 for ; Fri, 10 Oct 2025 06:06:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-426ce583316sm4221657f8f.20.2025.10.10.06.06.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Oct 2025 06:06:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1760101565; x=1760706365; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fy6Nmaf+Hy4K6iUgM9jgvpsvnnLpWkOyEh230NdUHFE=; b=SZqouwzz4HAGXcTOA5O6eXhlZ3S9uhB6TwN2hXr49HA++qZ7CthInFtdUJFCJIARqi N/MUbR88SzwJA/h3PRKADgSyCTKr1jT66v/aGpV52PKEFakmGqmXAtYAjITQPArqew17 9Ce0b1ecXuOmF0cr8sq7Y3ZNV2qI3SMu8owZSBd1RhW3OE/SyfLSSpJi/Gw7l50ohmNK z6ZOsyK+MaJmwGgGBegBsLox6xUAjcx+XedjXNSaSTbmGeGE9649uoqMbyX+pZ+n4BLY 9GbN1dAQng2lo2EGiDHVuPmAmVoXKhiYnKoL5XVZXiM9gpJTpuLiEOKBNMiNczKhhzBW vmsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760101565; x=1760706365; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fy6Nmaf+Hy4K6iUgM9jgvpsvnnLpWkOyEh230NdUHFE=; b=FixXD2du7w74Vv+xZhp3hGLbpPoTBatKolsK+BFP4OQEiCTzh24r4fHV/6prJtBe+E W0IwRgGgl/xEmewpTDjmpOoArvRV+XMmaa95Nxb9AJLNzNrf54HcPBpm+00NlOXA2ctW dzfUwwiBJutxSSiqMBQVE9cwIiUZMW92kei6zfBBo3beyLPIjTp8HhhoYop/wrgNvrQu pQPCSaefCpSKAs7WDZPW5EE7a1YZ3mRt8qBaGnlJXHGQElq/T5/eoaKVNAtdGF37IaWK 61CLL58B5FyLyXRKHgeNe1p/3/gLt92S1vVRm98qhlhCNQrpMbi0hNv5LTlN+u859LRD 9S4w== X-Gm-Message-State: AOJu0YxGELgYp1wJ0WkxMaVS1VhyuM9BXclkftQzRZE2UM0WqHNmv64Z 1krfDIAYhW3a8nvqo+koaLu1UY87TJiyUSzkprvNVtOXoO2vJsM6cKi5pvqNsXzel/zQkOdjmgB nzL+K X-Gm-Gg: ASbGncuhKSwbwn2+Ic0bn9u7LR0M15UqbA8lrXKIuMPcBtRgaGgFlPWJ9LB29lepqms qOMiUYfgQByHmeN2JeqlMYzlZKbK7usMwKVtICdYXZyKqsE0KqcLo3hwMXL2mpwKJDJbXWTSzzh O8Myr3leSyhkdgP7hSr5+z8Hzo4J/W3ZuhrvUW6em8hhDN5lmexOg2ViRMIqrHf23ozmzc7dL4S XnnyfoaKx3G1oihdbO2KbQjohvuVwNCTCrAA/2j6rycSlxtNuT6Kl9OlBp06mKQBUMoxDoIbt7i t13CicZBGFY4Ut2axwuE748HyeI0Q1MqfyOXBjBQVD0raL8bQTItU+c459//0sKpnNRvla60Sdi 6HPtEgW0rFBIawMkZwHiMcAeKIuKRsuKvwYfm8COmzUXlLbJC/4w= X-Google-Smtp-Source: AGHT+IGzKAyQpF8E2ijgeCDW/gqTOidGQXx8RIxSPsNA+UXsz2aXCcujDESoYyLzD63reLg2sgdX0Q== X-Received: by 2002:a05:600c:4e47:b0:46e:652e:16a1 with SMTP id 5b1f17b1804b1-46fa9a8b482mr78530415e9.7.1760101565052; Fri, 10 Oct 2025 06:06:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/76] target/arm: Add GCS cpregs Date: Fri, 10 Oct 2025 14:04:42 +0100 Message-ID: <20251010130527.3921602-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251010130527.3921602-1-peter.maydell@linaro.org> References: <20251010130527.3921602-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760102169534158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Add isar_feature_aa64_gcs. Enable SCR_GCSEN in scr_write. Enable HCRX_GCSEN in hcrx_write. Default HCRX_GCSEN on if EL2 disabled. Add the GCSCR* and GCSPR* registers. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20251008215613.300150-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 2 + target/arm/cpu-features.h | 5 +++ target/arm/cpu.h | 12 +++++ target/arm/internals.h | 3 ++ target/arm/cpregs-gcs.c | 95 +++++++++++++++++++++++++++++++++++++++ target/arm/cpu.c | 3 ++ target/arm/helper.c | 10 +++++ target/arm/meson.build | 2 + 8 files changed, 132 insertions(+) create mode 100644 target/arm/cpregs-gcs.c diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index f48c4df30fb..bd2121a336e 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -779,6 +779,8 @@ typedef enum FGTBit { DO_BIT(HFGRTR, VBAR_EL1), DO_BIT(HFGRTR, ICC_IGRPENN_EL1), DO_BIT(HFGRTR, ERRIDR_EL1), + DO_REV_BIT(HFGRTR, NGCS_EL0), + DO_REV_BIT(HFGRTR, NGCS_EL1), DO_REV_BIT(HFGRTR, NSMPRI_EL1), DO_REV_BIT(HFGRTR, NTPIDR2_EL0), DO_REV_BIT(HFGRTR, NPIRE0_EL1), diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index f3e90408f7b..0f0a112c213 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1149,6 +1149,11 @@ static inline bool isar_feature_aa64_nmi(const ARMIS= ARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64PFR1, NMI) !=3D 0; } =20 +static inline bool isar_feature_aa64_gcs(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64PFR1, GCS) !=3D 0; +} + static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) { return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >=3D 1; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6773676973c..e55524ae107 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -580,6 +580,9 @@ typedef struct CPUArchState { =20 /* NV2 register */ uint64_t vncr_el2; + + uint64_t gcscr_el[4]; /* GCSCRE0_EL1, GCSCR_EL[123] */ + uint64_t gcspr_el[4]; /* GCSPR_EL[0123] */ } cp15; =20 struct { @@ -1717,6 +1720,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_ENAS0 (1ULL << 36) #define SCR_ADEN (1ULL << 37) #define SCR_HXEN (1ULL << 38) +#define SCR_GCSEN (1ULL << 39) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) #define SCR_TCR2EN (1ULL << 43) @@ -1725,6 +1729,14 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) #define SCR_GPF (1ULL << 48) #define SCR_NSE (1ULL << 62) =20 +/* GCSCR_ELx fields */ +#define GCSCR_PCRSEL (1ULL << 0) +#define GCSCR_RVCHKEN (1ULL << 5) +#define GCSCR_EXLOCKEN (1ULL << 6) +#define GCSCR_PUSHMEN (1ULL << 8) +#define GCSCR_STREN (1ULL << 9) +#define GCSCRE0_NTR (1ULL << 10) + /* Return the current FPSCR value. */ uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); diff --git a/target/arm/internals.h b/target/arm/internals.h index 591b509e68b..109aa104bfe 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -251,6 +251,7 @@ FIELD(VSTCR, SA, 30, 1) #define HCRX_MSCEN (1ULL << 11) #define HCRX_TCR2EN (1ULL << 14) #define HCRX_SCTLR2EN (1ULL << 15) +#define HCRX_GCSEN (1ULL << 22) =20 #define HPFAR_NS (1ULL << 63) =20 @@ -1783,6 +1784,8 @@ void define_tlb_insn_regs(ARMCPU *cpu); void define_at_insn_regs(ARMCPU *cpu); /* Add the cpreg definitions for PM cpregs */ void define_pm_cpregs(ARMCPU *cpu); +/* Add the cpreg definitions for GCS cpregs */ +void define_gcs_cpregs(ARMCPU *cpu); =20 /* Effective value of MDCR_EL2 */ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env) diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c new file mode 100644 index 00000000000..1ff041811d2 --- /dev/null +++ b/target/arm/cpregs-gcs.c @@ -0,0 +1,95 @@ +/* + * QEMU ARM CP Register GCS regiters and instructions + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/timer.h" +#include "exec/icount.h" +#include "hw/irq.h" +#include "cpu.h" +#include "cpu-features.h" +#include "cpregs.h" +#include "internals.h" + + +static CPAccessResult access_gcs(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_GCSEN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult access_gcs_el0(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 0 && !(env->cp15.gcscr_el[0] & GCSCRE0_= NTR)) { + return CP_ACCESS_TRAP_EL1; + } + return access_gcs(env, ri, isread); +} + +static void gcspr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Bits [2:0] are RES0, so we might as well clear them now, + * rather than upon each usage a-la GetCurrentGCSPointer. + */ + raw_write(env, ri, value & ~7); +} + +static const ARMCPRegInfo gcs_reginfo[] =3D { + { .name =3D "GCSCRE0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 5, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_gcs, .fgt =3D FGT_NGCS_EL0, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[0]) }, + { .name =3D "GCSCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 5, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_gcs, .fgt =3D FGT_NGCS_EL1, + .nv2_redirect_offset =3D 0x8d0 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 2, 5, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 2, 5, 0), + .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[1]) }, + { .name =3D "GCSCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 5, .opc2 =3D 0, + .access =3D PL2_RW, .accessfn =3D access_gcs, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[2]) }, + { .name =3D "GCSCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 5, .opc2 =3D 0, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[3]) }, + + { .name =3D "GCSPR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, + .access =3D PL0_R | PL1_W, .accessfn =3D access_gcs_el0, + .fgt =3D FGT_NGCS_EL0, .writefn =3D gcspr_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[0]) }, + { .name =3D "GCSPR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_gcs, + .fgt =3D FGT_NGCS_EL1, .writefn =3D gcspr_write, + .nv2_redirect_offset =3D 0x8c0 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 2, 5, 1), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 2, 5, 1), + .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[1]) }, + { .name =3D "GCSPR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, + .access =3D PL2_RW, .accessfn =3D access_gcs, .writefn =3D gcspr_wri= te, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[2]) }, + { .name =3D "GCSPR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, + .access =3D PL3_RW, .writefn =3D gcspr_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[2]) }, +}; + +void define_gcs_cpregs(ARMCPU *cpu) +{ + if (cpu_isar_feature(aa64_gcs, cpu)) { + define_arm_cp_regs(cpu, gcs_reginfo); + } +} diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9bca1b8eae5..192acac1f5a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -635,6 +635,9 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int= target_el) if (cpu_isar_feature(aa64_fgt, cpu)) { env->cp15.scr_el3 |=3D SCR_FGTEN; } + if (cpu_isar_feature(aa64_gcs, cpu)) { + env->cp15.scr_el3 |=3D SCR_GCSEN; + } if (cpu_isar_feature(aa64_tcr2, cpu)) { env->cp15.scr_el3 |=3D SCR_TCR2EN; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 6642cae0cc4..64b6c21aef7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -766,6 +766,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegI= nfo *ri, uint64_t value) if (cpu_isar_feature(aa64_ecv, cpu)) { valid_mask |=3D SCR_ECVEN; } + if (cpu_isar_feature(aa64_gcs, cpu)) { + valid_mask |=3D SCR_GCSEN; + } if (cpu_isar_feature(aa64_tcr2, cpu)) { valid_mask |=3D SCR_TCR2EN; } @@ -3953,6 +3956,9 @@ static void hcrx_write(CPUARMState *env, const ARMCPR= egInfo *ri, if (cpu_isar_feature(aa64_sctlr2, cpu)) { valid_mask |=3D HCRX_SCTLR2EN; } + if (cpu_isar_feature(aa64_gcs, cpu)) { + valid_mask |=3D HCRX_GCSEN; + } =20 /* Clear RES0 bits. */ env->cp15.hcrx_el2 =3D value & valid_mask; @@ -4023,6 +4029,9 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env) if (cpu_isar_feature(aa64_sctlr2, cpu)) { hcrx |=3D HCRX_SCTLR2EN; } + if (cpu_isar_feature(aa64_gcs, cpu)) { + hcrx |=3D HCRX_GCSEN; + } return hcrx; } if (arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXE= N)) { @@ -7260,6 +7269,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 define_pm_cpregs(cpu); + define_gcs_cpregs(cpu); } =20 /* diff --git a/target/arm/meson.build b/target/arm/meson.build index f9f0beef05e..3df7e03654e 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -27,6 +27,7 @@ arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c', )) arm_user_ss.add(files( + 'cpregs-gcs.c', 'cpregs-pmu.c', 'debug_helper.c', 'helper.c', @@ -47,6 +48,7 @@ arm_common_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', 'cortex-regs.c', + 'cpregs-gcs.c', 'cpregs-pmu.c', 'cpu-irq.c', 'debug_helper.c', --=20 2.43.0