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Re-order the fsr member to eliminate two structure holes. Drop the comment about "if we implement EL2" since we have already done so. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-id: 20251008215613.300150-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 7 ++----- target/arm/helper.c | 2 +- target/arm/machine.c | 32 +++++++++++++++++++++++++++++++- 3 files changed, 34 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c9ea160d035..04b57f1dc5a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -633,13 +633,10 @@ typedef struct CPUArchState { * entry process. */ struct { - uint32_t syndrome; /* AArch64 format syndrome register */ - uint32_t fsr; /* AArch32 format fault status register info */ + uint64_t syndrome; /* AArch64 format syndrome register */ uint64_t vaddress; /* virtual addr associated with exception, if a= ny */ + uint32_t fsr; /* AArch32 format fault status register info */ uint32_t target_el; /* EL the exception should be targeted for */ - /* If we implement EL2 we will also need to store information - * about the intermediate physical address for stage 2 faults. - */ } exception; =20 /* Information associated with an SError */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 37865bf70eb..bd5321348ac 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9196,7 +9196,7 @@ void arm_cpu_do_interrupt(CPUState *cs) new_el); if (qemu_loglevel_mask(CPU_LOG_INT) && !excp_is_internal(cs->exception_index)) { - qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", + qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx64 "\n", syn_get_ec(env->exception.syndrome), env->exception.syndrome); } diff --git a/target/arm/machine.c b/target/arm/machine.c index 6666a0c50c4..ce20b46f50f 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -848,6 +848,23 @@ static const VMStateInfo vmstate_powered_off =3D { .put =3D put_power, }; =20 +static bool syndrome64_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + return cpu->env.exception.syndrome > UINT32_MAX; +} + +static const VMStateDescription vmstate_syndrome64 =3D { + .name =3D "cpu/syndrome64", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D syndrome64_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT64(env.exception.syndrome, ARMCPU), + VMSTATE_END_OF_LIST() + }, +}; + static int cpu_pre_save(void *opaque) { ARMCPU *cpu =3D opaque; @@ -1065,7 +1082,19 @@ const VMStateDescription vmstate_arm_cpu =3D { VMSTATE_UINT64(env.exclusive_val, ARMCPU), VMSTATE_UINT64(env.exclusive_high, ARMCPU), VMSTATE_UNUSED(sizeof(uint64_t)), - VMSTATE_UINT32(env.exception.syndrome, ARMCPU), + /* + * If any bits are set in the upper 32 bits of syndrome, + * then the cpu/syndrome64 subsection will override this + * with the full 64 bit state. + */ + { + .name =3D "env.exception.syndrome", + .version_id =3D 0, + .size =3D sizeof(uint32_t), + .info =3D &vmstate_info_uint32, + .flags =3D VMS_SINGLE, + .offset =3D offsetoflow32(ARMCPU, env.exception.syndrome), + }, VMSTATE_UINT32(env.exception.fsr, ARMCPU), VMSTATE_UINT64(env.exception.vaddress, ARMCPU), VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), @@ -1098,6 +1127,7 @@ const VMStateDescription vmstate_arm_cpu =3D { &vmstate_serror, &vmstate_irq_line_state, &vmstate_wfxt_timer, + &vmstate_syndrome64, NULL } }; --=20 2.43.0