From nobody Fri Nov 14 19:47:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760084940986780.3483876190385; Fri, 10 Oct 2025 01:29:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78TV-0007CS-AR; Fri, 10 Oct 2025 04:27:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v78TU-0007BU-9N for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:40 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78TL-0004T0-D4 for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:40 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxP_Bqw+hoApsUAA--.43910S3; Fri, 10 Oct 2025 16:27:22 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxzsFpw+hos0LYAA--.56940S3; Fri, 10 Oct 2025 16:27:21 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 1/8] target/loongarch: Add phys_bits in CPULoongArchState Date: Fri, 10 Oct 2025 16:27:13 +0800 Message-Id: <20251010082720.3943996-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251010082720.3943996-1-maobibo@loongson.cn> References: <20251010082720.3943996-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxzsFpw+hos0LYAA--.56940S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1760084944293154100 Content-Type: text/plain; charset="utf-8" Add field phys_bits in structure CPULoongArchState, to record supported physical address width. Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 13 +++++++------ target/loongarch/cpu.h | 2 ++ 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 86490e0f72..810f8f36af 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -248,7 +248,7 @@ static void loongarch_la464_initfn(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); CPULoongArchState *env =3D &cpu->env; - uint32_t data =3D 0, field; + uint32_t data =3D 0; int i; =20 for (i =3D 0; i < 21; i++) { @@ -262,12 +262,12 @@ static void loongarch_la464_initfn(Object *obj) data =3D FIELD_DP32(data, CPUCFG1, PGMMU, 1); data =3D FIELD_DP32(data, CPUCFG1, IOCSR, 1); if (kvm_enabled()) { - /* GPA address width of VM is 47, field value is 47 - 1 */ - field =3D 0x2e; + /* GPA address width of VM is 47 */ + env->phys_bits =3D 47; } else { - field =3D 0x2f; /* 48 bit - 1 */ + env->phys_bits =3D 48; } - data =3D FIELD_DP32(data, CPUCFG1, PALEN, field); + data =3D FIELD_DP32(data, CPUCFG1, PALEN, env->phys_bits - 1); data =3D FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); data =3D FIELD_DP32(data, CPUCFG1, UAL, 1); data =3D FIELD_DP32(data, CPUCFG1, RI, 1); @@ -364,10 +364,11 @@ static void loongarch_la132_initfn(Object *obj) cpu->dtb_compatible =3D "loongarch,Loongson-1C103"; env->cpucfg[0] =3D 0x148042; /* PRID */ =20 + env->phys_bits =3D 32; data =3D FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ data =3D FIELD_DP32(data, CPUCFG1, PGMMU, 1); data =3D FIELD_DP32(data, CPUCFG1, IOCSR, 1); - data =3D FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ + data =3D FIELD_DP32(data, CPUCFG1, PALEN, env->phys_bits - 1); /* 32 b= its */ data =3D FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ data =3D FIELD_DP32(data, CPUCFG1, UAL, 1); data =3D FIELD_DP32(data, CPUCFG1, RI, 0); diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index b8e3b46c3a..85dcbb7433 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -379,6 +379,8 @@ typedef struct CPUArchState { =20 AddressSpace *address_space_iocsr; uint32_t mp_state; + /* Supported physical address width */ + uint32_t phys_bits; #endif } CPULoongArchState; =20 --=20 2.39.3