From nobody Fri Nov 14 18:24:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760084940986780.3483876190385; Fri, 10 Oct 2025 01:29:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78TV-0007CS-AR; Fri, 10 Oct 2025 04:27:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v78TU-0007BU-9N for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:40 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78TL-0004T0-D4 for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:40 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxP_Bqw+hoApsUAA--.43910S3; Fri, 10 Oct 2025 16:27:22 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxzsFpw+hos0LYAA--.56940S3; Fri, 10 Oct 2025 16:27:21 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 1/8] target/loongarch: Add phys_bits in CPULoongArchState Date: Fri, 10 Oct 2025 16:27:13 +0800 Message-Id: <20251010082720.3943996-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251010082720.3943996-1-maobibo@loongson.cn> References: <20251010082720.3943996-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxzsFpw+hos0LYAA--.56940S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1760084944293154100 Content-Type: text/plain; charset="utf-8" Add field phys_bits in structure CPULoongArchState, to record supported physical address width. Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 13 +++++++------ target/loongarch/cpu.h | 2 ++ 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 86490e0f72..810f8f36af 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -248,7 +248,7 @@ static void loongarch_la464_initfn(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); CPULoongArchState *env =3D &cpu->env; - uint32_t data =3D 0, field; + uint32_t data =3D 0; int i; =20 for (i =3D 0; i < 21; i++) { @@ -262,12 +262,12 @@ static void loongarch_la464_initfn(Object *obj) data =3D FIELD_DP32(data, CPUCFG1, PGMMU, 1); data =3D FIELD_DP32(data, CPUCFG1, IOCSR, 1); if (kvm_enabled()) { - /* GPA address width of VM is 47, field value is 47 - 1 */ - field =3D 0x2e; + /* GPA address width of VM is 47 */ + env->phys_bits =3D 47; } else { - field =3D 0x2f; /* 48 bit - 1 */ + env->phys_bits =3D 48; } - data =3D FIELD_DP32(data, CPUCFG1, PALEN, field); + data =3D FIELD_DP32(data, CPUCFG1, PALEN, env->phys_bits - 1); data =3D FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); data =3D FIELD_DP32(data, CPUCFG1, UAL, 1); data =3D FIELD_DP32(data, CPUCFG1, RI, 1); @@ -364,10 +364,11 @@ static void loongarch_la132_initfn(Object *obj) cpu->dtb_compatible =3D "loongarch,Loongson-1C103"; env->cpucfg[0] =3D 0x148042; /* PRID */ =20 + env->phys_bits =3D 32; data =3D FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ data =3D FIELD_DP32(data, CPUCFG1, PGMMU, 1); data =3D FIELD_DP32(data, CPUCFG1, IOCSR, 1); - data =3D FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ + data =3D FIELD_DP32(data, CPUCFG1, PALEN, env->phys_bits - 1); /* 32 b= its */ data =3D FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ data =3D FIELD_DP32(data, CPUCFG1, UAL, 1); data =3D FIELD_DP32(data, CPUCFG1, RI, 0); diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index b8e3b46c3a..85dcbb7433 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -379,6 +379,8 @@ typedef struct CPUArchState { =20 AddressSpace *address_space_iocsr; uint32_t mp_state; + /* Supported physical address width */ + uint32_t phys_bits; #endif } CPULoongArchState; =20 --=20 2.39.3 From nobody Fri Nov 14 18:24:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176008492206378.09828825942486; Fri, 10 Oct 2025 01:28:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78TR-0007A5-LS; Fri, 10 Oct 2025 04:27:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v78TN-00079K-Lh for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:33 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78TK-0004TA-9i for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:33 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxndJqw+hoBZsUAA--.43501S3; Fri, 10 Oct 2025 16:27:22 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxzsFpw+hos0LYAA--.56940S4; Fri, 10 Oct 2025 16:27:21 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 2/8] hw/loongarch/virt: Add field ram_end in LoongArchVirtMachineState Date: Fri, 10 Oct 2025 16:27:14 +0800 Message-Id: <20251010082720.3943996-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251010082720.3943996-1-maobibo@loongson.cn> References: <20251010082720.3943996-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxzsFpw+hos0LYAA--.56940S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1760084928445158500 Content-Type: text/plain; charset="utf-8" DRAM region is dynamically set and the last valid physical address region with LoongArch Virt Machine. To record the last valid physical address, field ram_end is added in structure LoongArchVirtMachineState. In future end address of DRAM cannot exceed base addres of PCIE 64-bit MMIO region. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 2 ++ include/hw/loongarch/virt.h | 1 + 2 files changed, 3 insertions(+) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index c1760423ee..8740a3cf4b 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -850,8 +850,10 @@ static void virt_init(MachineState *machine) exit(EXIT_FAILURE); } machine_memory_devices_init(machine, base, device_mem_size); + base +=3D device_mem_size; } =20 + lvms->ram_end =3D base; /* load the BIOS image. */ virt_firmware_init(lvms); =20 diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 76fa57cd07..224a66d3cc 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -90,6 +90,7 @@ struct LoongArchVirtMachineState { uint64_t misc_feature; uint64_t misc_status; DeviceState *dintc; + hwaddr ram_end; }; =20 #define TYPE_LOONGARCH_VIRT_MACHINE MACHINE_TYPE_NAME("virt") --=20 2.39.3 From nobody Fri Nov 14 18:24:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176008494195770.29389747883874; Fri, 10 Oct 2025 01:29:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78TR-0007AE-Lm; Fri, 10 Oct 2025 04:27:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v78TO-00079c-JQ for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:34 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78TJ-0004Ug-Q0 for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:34 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxHvBqw+hoB5sUAA--.44168S3; Fri, 10 Oct 2025 16:27:22 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxzsFpw+hos0LYAA--.56940S5; Fri, 10 Oct 2025 16:27:22 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 3/8] hw/loongarch/virt: Add field gpex in LoongArchVirtMachineState Date: Fri, 10 Oct 2025 16:27:15 +0800 Message-Id: <20251010082720.3943996-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251010082720.3943996-1-maobibo@loongson.cn> References: <20251010082720.3943996-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxzsFpw+hos0LYAA--.56940S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1760084946891158500 Content-Type: text/plain; charset="utf-8" Add field gpex in structure LoongArchVirtMachineState, type of field gpex is structure GPEXConfig and it is to record configuration information about GPEX host bridge. And remove field pci_bus in structure LoongArchVirtMachineState since the information is in field gpex already. Signed-off-by: Bibo Mao --- hw/loongarch/virt-acpi-build.c | 13 +------------ hw/loongarch/virt.c | 9 ++++++++- include/hw/loongarch/virt.h | 3 ++- 3 files changed, 11 insertions(+), 14 deletions(-) diff --git a/hw/loongarch/virt-acpi-build.c b/hw/loongarch/virt-acpi-build.c index 8c2228a772..8f3f1afac5 100644 --- a/hw/loongarch/virt-acpi-build.c +++ b/hw/loongarch/virt-acpi-build.c @@ -384,18 +384,7 @@ build_la_ged_aml(Aml *dsdt, MachineState *machine) =20 static void build_pci_device_aml(Aml *scope, LoongArchVirtMachineState *lv= ms) { - struct GPEXConfig cfg =3D { - .mmio64.base =3D VIRT_PCI_MEM_BASE, - .mmio64.size =3D VIRT_PCI_MEM_SIZE, - .pio.base =3D VIRT_PCI_IO_BASE, - .pio.size =3D VIRT_PCI_IO_SIZE, - .ecam.base =3D VIRT_PCI_CFG_BASE, - .ecam.size =3D VIRT_PCI_CFG_SIZE, - .irq =3D VIRT_GSI_BASE + VIRT_DEVICE_IRQS, - .bus =3D lvms->pci_bus, - }; - - acpi_dsdt_add_gpex(scope, &cfg); + acpi_dsdt_add_gpex(scope, &lvms->gpex); } =20 static void build_flash_aml(Aml *scope, LoongArchVirtMachineState *lvms) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 8740a3cf4b..fd8b0c1182 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -299,7 +299,14 @@ static void virt_devices_init(DeviceState *pch_pic, d =3D SYS_BUS_DEVICE(gpex_dev); sysbus_realize_and_unref(d, &error_fatal); pci_bus =3D PCI_HOST_BRIDGE(gpex_dev)->bus; - lvms->pci_bus =3D pci_bus; + lvms->gpex.mmio64.base =3D VIRT_PCI_MEM_BASE; + lvms->gpex.mmio64.size =3D VIRT_PCI_MEM_SIZE; + lvms->gpex.pio.base =3D VIRT_PCI_IO_BASE; + lvms->gpex.pio.size =3D VIRT_PCI_IO_SIZE; + lvms->gpex.ecam.base =3D VIRT_PCI_CFG_BASE; + lvms->gpex.ecam.size =3D VIRT_PCI_CFG_SIZE; + lvms->gpex.irq =3D VIRT_GSI_BASE + VIRT_DEVICE_IRQS; + lvms->gpex.bus =3D pci_bus; =20 /* Map only part size_ecam bytes of ECAM space */ ecam_alias =3D g_new0(MemoryRegion, 1); diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 224a66d3cc..01f20a135a 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -12,6 +12,7 @@ #include "qemu/queue.h" #include "hw/block/flash.h" #include "hw/loongarch/boot.h" +#include "hw/pci-host/gpex.h" =20 #define IOCSRF_TEMP 0 #define IOCSRF_NODECNT 1 @@ -77,7 +78,6 @@ struct LoongArchVirtMachineState { DeviceState *acpi_ged; int fdt_size; DeviceState *platform_bus_dev; - PCIBus *pci_bus; PFlashCFI01 *flash[2]; MemoryRegion system_iocsr; MemoryRegion iocsr_mem; @@ -91,6 +91,7 @@ struct LoongArchVirtMachineState { uint64_t misc_status; DeviceState *dintc; hwaddr ram_end; + struct GPEXConfig gpex; }; =20 #define TYPE_LOONGARCH_VIRT_MACHINE MACHINE_TYPE_NAME("virt") --=20 2.39.3 From nobody Fri Nov 14 18:24:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176008492472832.609630176564906; Fri, 10 Oct 2025 01:28:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78TU-0007C8-V8; Fri, 10 Oct 2025 04:27:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v78TS-0007Ai-PJ for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:38 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78TJ-0004TB-O3 for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:37 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Dxvr9rw+hoCZsUAA--.42496S3; Fri, 10 Oct 2025 16:27:23 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxzsFpw+hos0LYAA--.56940S6; Fri, 10 Oct 2025 16:27:22 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 4/8] hw/loongarch/virt: Get irq number from gpex config info Date: Fri, 10 Oct 2025 16:27:16 +0800 Message-Id: <20251010082720.3943996-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251010082720.3943996-1-maobibo@loongson.cn> References: <20251010082720.3943996-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxzsFpw+hos0LYAA--.56940S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1760084928438158500 Content-Type: text/plain; charset="utf-8" The base irq number of GPEX PCIE host bridge can comes from gpex::irq. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index fd8b0c1182..d3793ba8bc 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -293,7 +293,7 @@ static void virt_devices_init(DeviceState *pch_pic, PCIBus *pci_bus; MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; MemoryRegion *mmio_alias, *mmio_reg; - int i; + int i, irq; =20 gpex_dev =3D qdev_new(TYPE_GPEX_HOST); d =3D SYS_BUS_DEVICE(gpex_dev); @@ -333,9 +333,9 @@ static void virt_devices_init(DeviceState *pch_pic, pio_alias); =20 for (i =3D 0; i < PCI_NUM_PINS; i++) { - sysbus_connect_irq(d, i, - qdev_get_gpio_in(pch_pic, 16 + i)); - gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); + irq =3D lvms->gpex.irq + i - VIRT_GSI_BASE; + sysbus_connect_irq(d, i, qdev_get_gpio_in(pch_pic, irq)); + gpex_set_irq_num(GPEX_HOST(gpex_dev), i, irq); } =20 /* @@ -344,7 +344,7 @@ static void virt_devices_init(DeviceState *pch_pic, */ for (i =3D VIRT_UART_COUNT; i-- > 0;) { hwaddr base =3D VIRT_UART_BASE + i * VIRT_UART_SIZE; - int irq =3D VIRT_UART_IRQ + i - VIRT_GSI_BASE; + irq =3D VIRT_UART_IRQ + i - VIRT_GSI_BASE; serial_mm_init(get_system_memory(), base, 0, qdev_get_gpio_in(pch_pic, irq), 115200, serial_hd(i), DEVICE_LITTLE_ENDIAN); --=20 2.39.3 From nobody Fri Nov 14 18:24:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760084947650754.0581249607646; Fri, 10 Oct 2025 01:29:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78Ta-0007DA-6y; Fri, 10 Oct 2025 04:27:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v78TV-0007CM-7u for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:41 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78TN-0004Uj-NZ for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:40 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxbNJrw+hoC5sUAA--.44247S3; Fri, 10 Oct 2025 16:27:23 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxzsFpw+hos0LYAA--.56940S7; Fri, 10 Oct 2025 16:27:23 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 5/8] hw/loongarch/virt: Get PCI info from gpex config info Date: Fri, 10 Oct 2025 16:27:17 +0800 Message-Id: <20251010082720.3943996-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251010082720.3943996-1-maobibo@loongson.cn> References: <20251010082720.3943996-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxzsFpw+hos0LYAA--.56940S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1760084948585158500 Content-Type: text/plain; charset="utf-8" PCIE host bridge configuration information such as MMIO/Conf/IO base and size can come from gpex config info. Signed-off-by: Bibo Mao --- hw/loongarch/virt-acpi-build.c | 4 ++-- hw/loongarch/virt-fdt-build.c | 14 +++++++------- hw/loongarch/virt.c | 16 +++++++++------- 3 files changed, 18 insertions(+), 16 deletions(-) diff --git a/hw/loongarch/virt-acpi-build.c b/hw/loongarch/virt-acpi-build.c index 8f3f1afac5..ca4ebf52eb 100644 --- a/hw/loongarch/virt-acpi-build.c +++ b/hw/loongarch/virt-acpi-build.c @@ -566,8 +566,8 @@ static void acpi_build(AcpiBuildTables *tables, Machine= State *machine) acpi_add_table(table_offsets, tables_blob); { AcpiMcfgInfo mcfg =3D { - .base =3D VIRT_PCI_CFG_BASE, - .size =3D VIRT_PCI_CFG_SIZE, + .base =3D lvms->gpex.ecam.base, + .size =3D lvms->gpex.ecam.size, }; build_mcfg(tables_blob, tables->linker, &mcfg, lvms->oem_id, lvms->oem_table_id); diff --git a/hw/loongarch/virt-fdt-build.c b/hw/loongarch/virt-fdt-build.c index 728ce46699..5453805ca1 100644 --- a/hw/loongarch/virt-fdt-build.c +++ b/hw/loongarch/virt-fdt-build.c @@ -367,12 +367,12 @@ static void fdt_add_pcie_node(const LoongArchVirtMach= ineState *lvms, uint32_t *pch_msi_phandle) { char *nodename; - hwaddr base_mmio =3D VIRT_PCI_MEM_BASE; - hwaddr size_mmio =3D VIRT_PCI_MEM_SIZE; - hwaddr base_pio =3D VIRT_PCI_IO_BASE; - hwaddr size_pio =3D VIRT_PCI_IO_SIZE; - hwaddr base_pcie =3D VIRT_PCI_CFG_BASE; - hwaddr size_pcie =3D VIRT_PCI_CFG_SIZE; + hwaddr base_mmio =3D lvms->gpex.mmio64.base; + hwaddr size_mmio =3D lvms->gpex.mmio64.size; + hwaddr base_pio =3D lvms->gpex.pio.base; + hwaddr size_pio =3D lvms->gpex.pio.size; + hwaddr base_pcie =3D lvms->gpex.ecam.base; + hwaddr size_pcie =3D lvms->gpex.ecam.size; hwaddr base =3D base_pcie; const MachineState *ms =3D MACHINE(lvms); =20 @@ -385,7 +385,7 @@ static void fdt_add_pcie_node(const LoongArchVirtMachin= eState *lvms, qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, - PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); + PCIE_MMCFG_BUS(size_pcie - 1)); qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base_pcie, 2, size_pcie); diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index d3793ba8bc..ad891a5972 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -293,6 +293,7 @@ static void virt_devices_init(DeviceState *pch_pic, PCIBus *pci_bus; MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; MemoryRegion *mmio_alias, *mmio_reg; + hwaddr mmio_base, mmio_size; int i, irq; =20 gpex_dev =3D qdev_new(TYPE_GPEX_HOST); @@ -307,29 +308,30 @@ static void virt_devices_init(DeviceState *pch_pic, lvms->gpex.ecam.size =3D VIRT_PCI_CFG_SIZE; lvms->gpex.irq =3D VIRT_GSI_BASE + VIRT_DEVICE_IRQS; lvms->gpex.bus =3D pci_bus; + mmio_base =3D lvms->gpex.mmio64.base; + mmio_size =3D lvms->gpex.mmio64.size; =20 /* Map only part size_ecam bytes of ECAM space */ ecam_alias =3D g_new0(MemoryRegion, 1); ecam_reg =3D sysbus_mmio_get_region(d, 0); memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", - ecam_reg, 0, VIRT_PCI_CFG_SIZE); - memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, + ecam_reg, 0, lvms->gpex.ecam.size); + memory_region_add_subregion(get_system_memory(), lvms->gpex.ecam.base, ecam_alias); =20 /* Map PCI mem space */ mmio_alias =3D g_new0(MemoryRegion, 1); mmio_reg =3D sysbus_mmio_get_region(d, 1); memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", - mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZ= E); - memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, - mmio_alias); + mmio_reg, mmio_base, mmio_size); + memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias= ); =20 /* Map PCI IO port space. */ pio_alias =3D g_new0(MemoryRegion, 1); pio_reg =3D sysbus_mmio_get_region(d, 2); memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_r= eg, - VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); - memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, + VIRT_PCI_IO_OFFSET, lvms->gpex.pio.size); + memory_region_add_subregion(get_system_memory(), lvms->gpex.pio.base, pio_alias); =20 for (i =3D 0; i < PCI_NUM_PINS; i++) { --=20 2.39.3 From nobody Fri Nov 14 18:24:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760084912899452.13950666753215; Fri, 10 Oct 2025 01:28:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78TU-0007BY-Dk; Fri, 10 Oct 2025 04:27:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v78TS-0007Az-HS for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:38 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78TL-0004UK-As for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:38 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Dx_79rw+hoDJsUAA--.43675S3; Fri, 10 Oct 2025 16:27:23 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxzsFpw+hos0LYAA--.56940S8; Fri, 10 Oct 2025 16:27:23 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 6/8] hw/loongarch/virt: Add property highmem_mmio with virt machine Date: Fri, 10 Oct 2025 16:27:18 +0800 Message-Id: <20251010082720.3943996-7-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251010082720.3943996-1-maobibo@loongson.cn> References: <20251010082720.3943996-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxzsFpw+hos0LYAA--.56940S8 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1760084925892154100 Content-Type: text/plain; charset="utf-8" On LoongArch Virt Machine, MMIO region with GPEX host bridge is 0x40000000 -- 0x7FFFFFFF. The total size is 1G bytes and it is enough for emulated virtio devices basically. However on some conditions such as hostmem is added with virtio-gpu device, the command line is -device virtio-gpu-gl,hostmem=3D4G. The PCIE MMIO region is not enough, 64-bit high MMIO region is required. Here add property highmem_mmio with virt machine, however it brings out incompatible issue. Here the default value is false. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 21 +++++++++++++++++++++ include/hw/loongarch/virt.h | 1 + 2 files changed, 22 insertions(+) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index ad891a5972..264070e787 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -90,6 +90,20 @@ static void virt_set_veiointc(Object *obj, Visitor *v, c= onst char *name, visit_type_OnOffAuto(v, name, &lvms->veiointc, errp); } =20 +static bool virt_get_highmem_mmio(Object *obj, Error **errp) +{ + LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(obj); + + return lvms->highmem_mmio; +} + +static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) +{ + LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(obj); + + lvms->highmem_mmio =3D value; +} + static PFlashCFI01 *virt_flash_create1(LoongArchVirtMachineState *lvms, const char *name, const char *alias_prop_name) @@ -1381,6 +1395,13 @@ static void virt_class_init(ObjectClass *oc, const v= oid *data) "Override the default value of f= ield OEM Table ID " "in ACPI table header." "The string may be up to 8 bytes= in size"); + + object_class_property_add_bool(oc, "highmem-mmio", + virt_get_highmem_mmio, + virt_set_highmem_mmio); + object_class_property_set_description(oc, "highmem-mmio", + "Set on/off to enable/disable hi= gh " + "memory region for PCI MMIO"); } =20 static const TypeInfo virt_machine_types[] =3D { diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 01f20a135a..8a289a49fa 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -92,6 +92,7 @@ struct LoongArchVirtMachineState { DeviceState *dintc; hwaddr ram_end; struct GPEXConfig gpex; + bool highmem_mmio; }; =20 #define TYPE_LOONGARCH_VIRT_MACHINE MACHINE_TYPE_NAME("virt") --=20 2.39.3 From nobody Fri Nov 14 18:24:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760084947127387.5984098296482; Fri, 10 Oct 2025 01:29:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78TV-0007Cc-Ep; Fri, 10 Oct 2025 04:27:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v78TU-0007BT-6a for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:40 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78TL-0004Uo-4L for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:39 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Bx1tBrw+hoD5sUAA--.43845S3; Fri, 10 Oct 2025 16:27:23 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxzsFpw+hos0LYAA--.56940S9; Fri, 10 Oct 2025 16:27:23 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 7/8] hw/loongarch/virt: Add high MMIO support with GPEX host Date: Fri, 10 Oct 2025 16:27:19 +0800 Message-Id: <20251010082720.3943996-8-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251010082720.3943996-1-maobibo@loongson.cn> References: <20251010082720.3943996-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxzsFpw+hos0LYAA--.56940S9 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1760084950598154100 Content-Type: text/plain; charset="utf-8" With high MMIO supported, its base address comes from physical end address of DRAM. Also add high MMIO support with GPEX host bridge. Signed-off-by: Bibo Mao --- hw/loongarch/virt-fdt-build.c | 33 ++++++++++++++---- hw/loongarch/virt.c | 63 +++++++++++++++++++++++++++++++++-- 2 files changed, 87 insertions(+), 9 deletions(-) diff --git a/hw/loongarch/virt-fdt-build.c b/hw/loongarch/virt-fdt-build.c index 5453805ca1..e4d3d80fe5 100644 --- a/hw/loongarch/virt-fdt-build.c +++ b/hw/loongarch/virt-fdt-build.c @@ -367,8 +367,8 @@ static void fdt_add_pcie_node(const LoongArchVirtMachin= eState *lvms, uint32_t *pch_msi_phandle) { char *nodename; - hwaddr base_mmio =3D lvms->gpex.mmio64.base; - hwaddr size_mmio =3D lvms->gpex.mmio64.size; + hwaddr base_mmio, base_mmio_high; + hwaddr size_mmio, size_mmio_high; hwaddr base_pio =3D lvms->gpex.pio.base; hwaddr size_pio =3D lvms->gpex.pio.size; hwaddr base_pcie =3D lvms->gpex.ecam.base; @@ -389,11 +389,30 @@ static void fdt_add_pcie_node(const LoongArchVirtMach= ineState *lvms, qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base_pcie, 2, size_pcie); - qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", - 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_O= FFSET, - 2, base_pio, 2, size_pio, - 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, - 2, base_mmio, 2, size_mmio); + if (lvms->highmem_mmio) { + base_mmio_high =3D lvms->gpex.mmio64.base; + size_mmio_high =3D lvms->gpex.mmio64.size; + base_mmio =3D lvms->gpex.mmio32.base; + size_mmio =3D lvms->gpex.mmio32.size; + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", + 1, FDT_PCI_RANGE_IOPORT, + 2, VIRT_PCI_IO_OFFSET, + 2, base_pio, 2, size_pio, + 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, + 2, base_mmio, 2, size_mmio, + 1, FDT_PCI_RANGE_MMIO_64BIT, + 2, base_mmio_high, + 2, base_mmio_high, 2, size_mmio_high); + } else { + base_mmio =3D lvms->gpex.mmio64.base; + size_mmio =3D lvms->gpex.mmio64.size; + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", + 1, FDT_PCI_RANGE_IOPORT, + 2, VIRT_PCI_IO_OFFSET, + 2, base_pio, 2, size_pio, + 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, + 2, base_mmio, 2, size_mmio); + } qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 0, *pch_msi_phandle, 0, 0x10000); fdt_add_pcie_irq_map_node(lvms, nodename, pch_pic_phandle); diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 264070e787..a7299dd658 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -73,6 +73,9 @@ static void virt_set_dmsi(Object *obj, Visitor *v, const = char *name, } } =20 +#define DEFAULT_HIGH_PCIE_MMIO_SIZE_GB 64 +#define DEFAULT_HIGH_PCIE_MMIO_SIZE (DEFAULT_HIGH_PCIE_MMIO_SIZE_GB * GiB) + static void virt_get_veiointc(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -298,6 +301,41 @@ static DeviceState *create_platform_bus(DeviceState *p= ch_pic) return dev; } =20 +static void virt_set_highmmio(LoongArchVirtMachineState *lvms) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(first_cpu); + CPULoongArchState *env =3D &cpu->env; + struct GPEXConfig *gpex; + + if (env->phys_bits <=3D 32) { + return; + } + + gpex =3D &lvms->gpex; + if (gpex->mmio64.size =3D=3D 0) { + gpex->mmio64.size =3D DEFAULT_HIGH_PCIE_MMIO_SIZE; + } + + /* + * GPEX base address starts from end of physical address + */ + gpex->mmio64.base =3D BIT_ULL(env->phys_bits) - BIT_ULL(env->phys_bits= - 3); + if (gpex->mmio64.base + gpex->mmio64.size > BIT_ULL(env->phys_bits)) { + error_report("GPEX region base %" PRIu64 " size %" PRIu64 + " exceeds %d physical bits", + gpex->mmio64.base, gpex->mmio64.size, + env->phys_bits); + exit(EXIT_FAILURE); + } + + if (lvms->ram_end > gpex->mmio64.base) { + error_report("DRAM end address %" PRIu64 + " exceeds GPEX region base %" PRIu64, + lvms->ram_end, gpex->mmio64.base); + exit(EXIT_FAILURE); + } +} + static void virt_devices_init(DeviceState *pch_pic, LoongArchVirtMachineState *lvms) { @@ -314,8 +352,6 @@ static void virt_devices_init(DeviceState *pch_pic, d =3D SYS_BUS_DEVICE(gpex_dev); sysbus_realize_and_unref(d, &error_fatal); pci_bus =3D PCI_HOST_BRIDGE(gpex_dev)->bus; - lvms->gpex.mmio64.base =3D VIRT_PCI_MEM_BASE; - lvms->gpex.mmio64.size =3D VIRT_PCI_MEM_SIZE; lvms->gpex.pio.base =3D VIRT_PCI_IO_BASE; lvms->gpex.pio.size =3D VIRT_PCI_IO_SIZE; lvms->gpex.ecam.base =3D VIRT_PCI_CFG_BASE; @@ -324,6 +360,18 @@ static void virt_devices_init(DeviceState *pch_pic, lvms->gpex.bus =3D pci_bus; mmio_base =3D lvms->gpex.mmio64.base; mmio_size =3D lvms->gpex.mmio64.size; + if (lvms->highmem_mmio) { + virt_set_highmmio(lvms); + lvms->gpex.mmio32.base =3D VIRT_PCI_MEM_BASE; + lvms->gpex.mmio32.size =3D VIRT_PCI_MEM_SIZE; + mmio_base =3D lvms->gpex.mmio32.base; + mmio_size =3D lvms->gpex.mmio32.size; + } else { + lvms->gpex.mmio64.base =3D VIRT_PCI_MEM_BASE; + lvms->gpex.mmio64.size =3D VIRT_PCI_MEM_SIZE; + mmio_base =3D lvms->gpex.mmio64.base; + mmio_size =3D lvms->gpex.mmio64.size; + } =20 /* Map only part size_ecam bytes of ECAM space */ ecam_alias =3D g_new0(MemoryRegion, 1); @@ -339,6 +387,17 @@ static void virt_devices_init(DeviceState *pch_pic, memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", mmio_reg, mmio_base, mmio_size); memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias= ); + if (lvms->highmem_mmio) { + /* Map high MMIO space */ + mmio_alias =3D g_new0(MemoryRegion, 1); + mmio_base =3D lvms->gpex.mmio64.base; + mmio_size =3D lvms->gpex.mmio64.size; + memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), + "pcie-mmio-high", mmio_reg, + mmio_base, mmio_size); + memory_region_add_subregion(get_system_memory(), mmio_base, + mmio_alias); + } =20 /* Map PCI IO port space. */ pio_alias =3D g_new0(MemoryRegion, 1); --=20 2.39.3 From nobody Fri Nov 14 18:24:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760084912986720.332141247621; Fri, 10 Oct 2025 01:28:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78TW-0007D9-V7; Fri, 10 Oct 2025 04:27:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v78TU-0007Bi-HM for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:40 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v78TN-0004V3-Em for qemu-devel@nongnu.org; Fri, 10 Oct 2025 04:27:40 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Axz79sw+hoEZsUAA--.42224S3; Fri, 10 Oct 2025 16:27:24 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxzsFpw+hos0LYAA--.56940S10; Fri, 10 Oct 2025 16:27:23 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 8/8] hw/loongarch/virt: Add property highmem-mmio-size with virt machine Date: Fri, 10 Oct 2025 16:27:20 +0800 Message-Id: <20251010082720.3943996-9-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251010082720.3943996-1-maobibo@loongson.cn> References: <20251010082720.3943996-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxzsFpw+hos0LYAA--.56940S10 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1760084919840158500 Content-Type: text/plain; charset="utf-8" The default high mmio size of GPEX PCIE host controller is 64G bytes on virt machine. If it does not meet requirements with some pass-throught HW devices in future, it can be adjust dynamically, here adds property highmem-mmio-size to set high mmio size. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index a7299dd658..324f14c898 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -7,6 +7,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qemu/datadir.h" +#include "qemu/cutils.h" #include "qapi/error.h" #include "exec/target_page.h" #include "hw/boards.h" @@ -107,6 +108,43 @@ static void virt_set_highmem_mmio(Object *obj, bool va= lue, Error **errp) lvms->highmem_mmio =3D value; } =20 +static void virt_get_highmem_mmio_size(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(obj); + uint64_t size =3D lvms->gpex.mmio64.size; + + visit_type_size(v, name, &size, errp); +} + +static void virt_set_highmem_mmio_size(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(obj); + uint64_t size; + + if (!visit_type_size(v, name, &size, errp)) { + return; + } + + if (!is_power_of_2(size)) { + error_setg(errp, "highmem-mmio-size is not a power of 2"); + return; + } + + if (size < DEFAULT_HIGH_PCIE_MMIO_SIZE) { + char *sz =3D size_to_str(DEFAULT_HIGH_PCIE_MMIO_SIZE); + error_setg(errp, "highmem-mmio-size cannot be set to a lower value= " + "than the default (%s)", sz); + g_free(sz); + return; + } + + lvms->gpex.mmio64.size =3D size; +} + static PFlashCFI01 *virt_flash_create1(LoongArchVirtMachineState *lvms, const char *name, const char *alias_prop_name) @@ -1461,6 +1499,13 @@ static void virt_class_init(ObjectClass *oc, const v= oid *data) object_class_property_set_description(oc, "highmem-mmio", "Set on/off to enable/disable hi= gh " "memory region for PCI MMIO"); + object_class_property_add(oc, "highmem-mmio-size", "size", + virt_get_highmem_mmio_size, + virt_set_highmem_mmio_size, + NULL, NULL); + object_class_property_set_description(oc, "highmem-mmio-size", + "Set the high memory region size= " + "for PCI MMIO"); } =20 static const TypeInfo virt_machine_types[] =3D { --=20 2.39.3