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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46fab3d2c1asm53511785e9.1.2025.10.10.00.07.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Oct 2025 00:07:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1760080029; x=1760684829; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FVb3aMnHodhOx3mpiCDcdapvdpvFoNzXZdFelJ9Oang=; b=I+RxmWslWUlGm/7/FeC3s+DErOd5494y2lEfeUe8G74NnwRssRk53K4WQpLHwUDocl ZLyAIbBXO32MRi4qF7b7l6gRhOKfPso0YTkThueSYR3mFs/nr/cV4zP8Ygg+qVjPib+l Rq0Wu2zdu0XXdycoibGcxpXg/BFDHoXFfadOmzr76PYmp+yq80twyyLObN4KqioxN48F l50hGWVU96H5PWPjlccq4nhhPx9rLf6RkpwRPHpmmXzSvsGyKvsDvjvH6YTd5dUHSmML ROKd15KeyjFBSggF1KxuV4W7g0GBmpQyp+7P9eW36IPeLwlR2RFcJopGA2oTSsBYHqRE Iykw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760080029; x=1760684829; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FVb3aMnHodhOx3mpiCDcdapvdpvFoNzXZdFelJ9Oang=; b=wl7XrRu9sNmIcM19MWUZh8WW2TMGhSVt/KLZFUb84cnp8tUTfw77ZafaWcgJ6m2Z4v f8VjZ3TyeurJTuZF1HXOhb1jxfD0ALDs18H+O84D654NmFcymt89xHuOILG7wz/gDMML 6pdZIy0Olc+NmXyOFYxR5hmL57hBG9VGUeawqXcQPluZFvrGHyQfg3AIhjrTpfsBlvjW XiluC3BegXLwZ8BcK2TlFZhti77K4ZWqV+3mcb87B8yYXBgVAhsxyt+EIgdlaG4RMLa0 RNR5F/N4VCy9j+exkTFi9CUkQ2f6+ILxZUFE2Qnll4nM/arMv3cHMQ6tLI9U/5yLvF1+ 9+nw== X-Gm-Message-State: AOJu0Yy7Bna0eGtb+TBrddFwAfhymVa7T2ZBdRAjZpDDDYkU5zBO2z5j XnRgoaJYJHX3onAClk7SRwP7uXZPekpsjL/4PN1/0Zrip7xKMXy8KLSf70F9AtXkVihJMKGBXYa Ne6nyftbTFw== X-Gm-Gg: ASbGnctB+fqMAxSuUufBUMzWBLnHRmFp4BMGHRo/b/59wYsly8CsL83Nap2kmEQbqIh hLHqgksPTKU2EUAaBNzy5HtzlFxIb9iaGaej6dAmZTaYBdFw/w5bg1VJQQ7pCk/Q3VIJMHVXpvz BI1kbnsDCAgDp2FZ5izS7ypkxHLe/84bwSVoI3/Msqyd2Id9INjkazXModHxbgVo9rW5FtaIIFp tCr5bYfuuGTn0XpG/qX9J/aT2nQ22MuINikHcZ5VQggslaUpbfpI6l/EiZ/rUvJ5/9MePQGT5y/ foaiRqWV343hjojSMG3NFS82dCK5841BPVWqMcXadZFv3s+mMzTcs2st1s5ZBAiPVNWpMPTjbd/ /C6hdIgzRl9S40yXtnxS0PPBqIKatz5FLbJOoJuWEPXuN7VX8QvzP6vs/qaPbZNHDQe7CaRAVGF 2YvxvRsqPGxP8Im+d1mX6xq59M X-Google-Smtp-Source: AGHT+IGl7vWcLyjhDRqCBUzsSKadWYhbRjWcuS1ysqrXLlHN2VmyOgnRPd2/0t9oAyVvc96tB02saA== X-Received: by 2002:a05:600d:4301:b0:46f:aa8a:d2e7 with SMTP id 5b1f17b1804b1-46faa8ad4bamr44608945e9.4.1760080029343; Fri, 10 Oct 2025 00:07:09 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Stafford Horne , Anton Johansson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 01/13] target/openrisc: Replace VMSTATE_UINTTL() -> VMSTATE_UINT32() Date: Fri, 10 Oct 2025 09:06:49 +0200 Message-ID: <20251010070702.51484-2-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251010070702.51484-1-philmd@linaro.org> References: <20251010070702.51484-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760080147139158500 Both OpenRISCTLBEntry fields are of uint32_t type. Use the appropriate VMSTATE_UINT32() macro. There is no functional change (the migration stream is not modified), because the OpenRISC targets are only built as 32-bit: $ git grep TARGET_LONG_BITS configs/targets/or1k-* configs/targets/or1k-linux-user.mak:5:TARGET_LONG_BITS=3D32 configs/targets/or1k-softmmu.mak:5:TARGET_LONG_BITS=3D32 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson --- target/openrisc/machine.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 081c706d02c..fa054e528bd 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -26,8 +26,8 @@ static const VMStateDescription vmstate_tlb_entry =3D { .version_id =3D 1, .minimum_version_id =3D 1, .fields =3D (const VMStateField[]) { - VMSTATE_UINTTL(mr, OpenRISCTLBEntry), - VMSTATE_UINTTL(tr, OpenRISCTLBEntry), + VMSTATE_UINT32(mr, OpenRISCTLBEntry), + VMSTATE_UINT32(tr, OpenRISCTLBEntry), VMSTATE_END_OF_LIST() } }; --=20 2.51.0 From nobody Fri Nov 14 18:19:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760080183; cv=none; d=zohomail.com; s=zohoarc; b=NFGXSu9wlqET8WFiWt2tRO4C4Iu05Q/z9vpg0iG9KFC0Jgnj36iLXIMaSC8LTEn+vX/4GCXYGAU/Loh145reANkNq5j/FAYmIUkxTXvsoSZ3GRAj1qDiXt61zHiX46FhPUcgPoRFLKQqdbvx9AtaSmQlxz5y+gu3cYQueCL4fqs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760080183; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qp4IO4MFNoh8safLEazorH+hzpRk3IlrvyISmNX81AI=; b=Xms/c4j8AXvvC05llCun7X9fe66GLXupc731kBEOvHqgVAmhP+GC2dYk5YkVjAmPeJDXKNDQ2m+A5xJ7uB9w2yX0MfYY6TtvVCXdQsEzDlwyQkyPLDKTP0tua/mSp9EE8rL/VA4Ty6fGwxY0kVPfiqrKuEnNeTd2uSvWuKzMty0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760080183118959.3992259295098; Fri, 10 Oct 2025 00:09:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v77Dr-0001bY-1N; Fri, 10 Oct 2025 03:07:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v77Dm-0001bE-Tn for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:07:23 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v77Dg-0007wZ-Sn for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:07:22 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-46e29d65728so10034345e9.3 for ; Fri, 10 Oct 2025 00:07:16 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson --- target/openrisc/sys_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index b091a9c6685..ad59939db3b 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -45,7 +45,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong sp= r, target_ulong rb) OpenRISCCPU *cpu =3D env_archcpu(env); #ifndef CONFIG_USER_ONLY CPUState *cs =3D env_cpu(env); - target_ulong mr; + uint32_t mr; int idx; #endif =20 --=20 2.51.0 From nobody Fri Nov 14 18:19:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760080099; cv=none; d=zohomail.com; s=zohoarc; b=lcptz4p5/wX2i5CFrZ31iJOw3lpMgHZCPtD3bSKKFUxxdIEWxLuA6pTD3dnDotILpzveXSoaPCQcdutKBLNak0U9pPqL+mw/DWy2/RTrFPq9aAAE1Cg7FQwQAotbcnbuZNamLFVlJ8aYw6X4EDdFd+aE2Wb96rF+yu1GQysRBs4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760080099; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=L5ER2oUjcbGwVSVbKc1P6Ocf6G/t516J/ZS3yvUvHLk=; b=SvrL21GzVJc5NzGmKhHqWIeKHArBN3/wiO8XsYePx5GQGFShTwqDrXDHOF6X7GNTMsZqD+kvRzDcIoFlb5wQAHuqVhn9aIQhz0oRV2D5wNoaxfzENK09oB+1P2t3B/yPwBJvc/1rPZuxC7MUfgO1hWqrcx0ZzxiPIFB1W71CoAA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760080099513750.4031270027048; Fri, 10 Oct 2025 00:08:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v77Dw-0001dG-Kf; Fri, 10 Oct 2025 03:07:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v77Dt-0001ch-Hq for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:07:29 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v77Dm-0007xD-Fb for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:07:28 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-46b303f755aso13419625e9.1 for ; Fri, 10 Oct 2025 00:07:22 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson --- target/openrisc/cpu.h | 9 --------- 1 file changed, 9 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index f4bcf00b073..87201365a91 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -220,15 +220,6 @@ typedef struct OpenRISCTLBEntry { typedef struct CPUOpenRISCTLBContext { OpenRISCTLBEntry itlb[TLB_SIZE]; OpenRISCTLBEntry dtlb[TLB_SIZE]; - - int (*cpu_openrisc_map_address_code)(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, - target_ulong address, int rw); - int (*cpu_openrisc_map_address_data)(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, - target_ulong address, int rw); } CPUOpenRISCTLBContext; #endif =20 --=20 2.51.0 From nobody Fri Nov 14 18:19:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760080116; cv=none; d=zohomail.com; s=zohoarc; b=D02uCAbKxHCFUS+pHoZmsaM/HWe5i7DgXCyMar5YQd4hZq2kgEib8k0oPFdQuA73QgeiBTXxXjNJ51KUDJ6XjQgBSzYYZ+Hrzk2qrCsWlMIWvsAUcjGT2AN9uJJOr+Gtg/cbyTwqqZRt5jZ6PLwAfGil2YC7A+9Y4gEImYPXQs8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760080116; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=UdXB7ylLc7Vhz3ZaX5Klsde0ekKLRZrXew/WW8Z5jnE=; b=L5nEgTd5nVgaUzkUcaesLwvDmPWbakeWV5Aey3FI2ezxSheESomnlVJPESOCkLMouq1ja1kg7q7VKLPsDFHZtGKBuoTzqG3JRSscNFI3yxYFmqgOmdXsimp2XhAJjATegOhQ53qHB+LhkAXNf9O0BPwEoFlp7bL79604KfNzPd8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760080115962755.6311164717433; Fri, 10 Oct 2025 00:08:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v77Dy-0001dp-WC; Fri, 10 Oct 2025 03:07:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v77Dx-0001dK-59 for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:07:33 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v77Ds-0007xT-1K for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:07:32 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-46e52279279so11653615e9.3 for ; Fri, 10 Oct 2025 00:07:27 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Do not inline get_phys_nommu(), rely on the linker to optimize at linking time. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson --- target/openrisc/mmu.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index acea50c41eb..ffb732e0d1f 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -28,15 +28,14 @@ #include "qemu/host-utils.h" #include "hw/loader.h" =20 -static inline void get_phys_nommu(hwaddr *phys_addr, int *prot, - target_ulong address) +static void get_phys_nommu(hwaddr *phys_addr, int *prot, vaddr address) { *phys_addr =3D address; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; } =20 static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot, - target_ulong addr, int need, bool super) + vaddr addr, int need, bool super) { int idx =3D (addr >> TARGET_PAGE_BITS) & TLB_MASK; uint32_t imr =3D cpu->env.tlb.itlb[idx].mr; @@ -95,7 +94,7 @@ static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_ad= dr, int *prot, } } =20 -static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, +static void raise_mmu_exception(OpenRISCCPU *cpu, vaddr address, int exception) { CPUState *cs =3D CPU(cpu); --=20 2.51.0 From nobody Fri Nov 14 18:19:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760080189; cv=none; d=zohomail.com; s=zohoarc; b=GX/4Iabt3wqnObvqQJ0xBouNkBJoOm+n+BbDjLFDcHHFfGkRiKrAdcOQD2+mFAhFMceDzT3TGtlsU5X6ylbvOGHTqWWR7yleDWAxzCj35XhTkpqOtCEenZ7a0D7JrLhSScQRhe3mvNEFCvzLLNnPvUbqhLnSrWLkqxQIAymlzMs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760080189; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dKAKoCrCXL4+jyUO8dvnijZXKLkuHiqnUNKcG3emi0Y=; b=fKUjPa6u1j/JvrP9R+sKcv8l3YB46W+9zituFb8wbPxRpAUgQVkCCSYDbvA5kvijoRmjg0xkIxQ1hB/BIvwBJDZOiAnxATXk+jiW28N5/SYA8ra3AgQKUD9Pfyky1cDbWVd3BF09tVoMihpwyjVT29Uw1wR/b8Y416DsoigHLDI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760080189353800.3670528210146; Fri, 10 Oct 2025 00:09:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v77E1-0001eS-DG; Fri, 10 Oct 2025 03:07:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v77Dz-0001dt-FQ for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:07:35 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v77Dw-0007xu-1f for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:07:33 -0400 Received: by mail-wm1-x343.google.com with SMTP id 5b1f17b1804b1-46e2e6a708fso11167525e9.0 for ; Fri, 10 Oct 2025 00:07:30 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson --- target/openrisc/translate.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 5ab3bc7021d..9f61f917b3b 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -51,7 +51,7 @@ typedef struct DisasContext { uint32_t avr; =20 /* If not -1, jmp_pc contains this value and so is a direct jump. */ - target_ulong jmp_pc_imm; + vaddr jmp_pc_imm; =20 /* The temporary corresponding to register 0 for this compilation. */ TCGv R0; @@ -580,7 +580,7 @@ static bool trans_l_muldu(DisasContext *dc, arg_ab *a) =20 static bool trans_l_j(DisasContext *dc, arg_l_j *a) { - target_ulong tmp_pc =3D dc->base.pc_next + a->n * 4; + vaddr tmp_pc =3D dc->base.pc_next + a->n * 4; =20 tcg_gen_movi_tl(jmp_pc, tmp_pc); dc->jmp_pc_imm =3D tmp_pc; @@ -590,8 +590,8 @@ static bool trans_l_j(DisasContext *dc, arg_l_j *a) =20 static bool trans_l_jal(DisasContext *dc, arg_l_jal *a) { - target_ulong tmp_pc =3D dc->base.pc_next + a->n * 4; - target_ulong ret_pc =3D dc->base.pc_next + 8; + vaddr tmp_pc =3D dc->base.pc_next + a->n * 4; + vaddr ret_pc =3D dc->base.pc_next + 8; =20 tcg_gen_movi_tl(cpu_regs[9], ret_pc); /* Optimize jal being used to load the PC for PIC. */ @@ -605,7 +605,7 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *a) =20 static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond) { - target_ulong tmp_pc =3D dc->base.pc_next + a->n * 4; + vaddr tmp_pc =3D dc->base.pc_next + a->n * 4; TCGv t_next =3D tcg_constant_tl(dc->base.pc_next + 8); TCGv t_true =3D tcg_constant_tl(tmp_pc); =20 @@ -1586,7 +1586,7 @@ static void openrisc_tr_translate_insn(DisasContextBa= se *dcbase, CPUState *cs) static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - target_ulong jmp_dest; + vaddr jmp_dest; =20 /* If we have already exited the TB, nothing following has effect. */ if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { --=20 2.51.0 From nobody Fri Nov 14 18:19:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760080103; cv=none; d=zohomail.com; s=zohoarc; b=IiqBOQbmDrCmAqSoe1Idlm5n6TmEmPtiuy/jaywaUxKc/5kaLNFJ8z2eslT1yLPl5GfkBoAfjoW4tX7TTu02XgEviPFxvLkGmeKJvG1PvS9ORZBktQdEEKVBOCZV8edfM5C7o1EeT1hZGWnFTDa2gdWNBWlFa74HjxR8WHXR+ak= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760080103; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mIyiqfArKbn1ZklyRRQRhl2a6Voqe2HH/5GIa/YoHgM=; b=FPFkjThtxgV57t9P5BQiBtkJbJ/YI9K4khv9S5Xh3r3fT32VNcS+aAzkQAo5Js87KdXT943DtWs7v8qQ37k72T9KCmJ9MPKbJpyIDC60yTPux71567xqpomInzU/aSP47NOdG2vfzfNR3KmpusHTPuB7dDEUS8ubcwV+9uWiRsQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760080103633946.9597054877119; Fri, 10 Oct 2025 00:08:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v77EF-0001ia-OZ; Fri, 10 Oct 2025 03:07:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v77ED-0001gc-Pb for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:07:49 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v77E2-0007yL-DA for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:07:49 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-46e37d6c21eso10116355e9.0 for ; Fri, 10 Oct 2025 00:07:34 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/openrisc/translate.c | 33 ++++----------------------------- 1 file changed, 4 insertions(+), 29 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 9f61f917b3b..29e6b51a930 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -298,19 +298,8 @@ static void gen_muld(DisasContext *dc, TCGv srca, TCGv= srcb) =20 tcg_gen_ext_tl_i64(t1, srca); tcg_gen_ext_tl_i64(t2, srcb); - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_gen_mul_i64(cpu_mac, t1, t2); - tcg_gen_movi_tl(cpu_sr_ov, 0); - } else { - TCGv_i64 high =3D tcg_temp_new_i64(); - - tcg_gen_muls2_i64(cpu_mac, high, t1, t2); - tcg_gen_sari_i64(t1, cpu_mac, 63); - tcg_gen_negsetcond_i64(TCG_COND_NE, t1, t1, high); - tcg_gen_trunc_i64_tl(cpu_sr_ov, t1); - - gen_ove_ov(dc); - } + tcg_gen_mul_i64(cpu_mac, t1, t2); + tcg_gen_movi_tl(cpu_sr_ov, 0); } =20 static void gen_muldu(DisasContext *dc, TCGv srca, TCGv srcb) @@ -320,18 +309,8 @@ static void gen_muldu(DisasContext *dc, TCGv srca, TCG= v srcb) =20 tcg_gen_extu_tl_i64(t1, srca); tcg_gen_extu_tl_i64(t2, srcb); - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_gen_mul_i64(cpu_mac, t1, t2); - tcg_gen_movi_tl(cpu_sr_cy, 0); - } else { - TCGv_i64 high =3D tcg_temp_new_i64(); - - tcg_gen_mulu2_i64(cpu_mac, high, t1, t2); - tcg_gen_setcondi_i64(TCG_COND_NE, high, high, 0); - tcg_gen_trunc_i64_tl(cpu_sr_cy, high); - - gen_ove_cy(dc); - } + tcg_gen_mul_i64(cpu_mac, t1, t2); + tcg_gen_movi_tl(cpu_sr_cy, 0); } =20 static void gen_mac(DisasContext *dc, TCGv srca, TCGv srcb) @@ -349,11 +328,7 @@ static void gen_mac(DisasContext *dc, TCGv srca, TCGv = srcb) tcg_gen_xor_i64(t1, t1, cpu_mac); tcg_gen_andc_i64(t1, t1, t2); =20 -#if TARGET_LONG_BITS =3D=3D 32 tcg_gen_extrh_i64_i32(cpu_sr_ov, t1); -#else - tcg_gen_mov_i64(cpu_sr_ov, t1); -#endif =20 gen_ove_ov(dc); } --=20 2.51.0 From nobody Fri Nov 14 18:19:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760080114; cv=none; d=zohomail.com; s=zohoarc; b=ZQepItcJ11KJvVgrn6TJcci4/YU13FfQxvP8weN5k+aowe95CwsMa+tntgisJ66aT/ErJ5jV0WciMi/go94KzEe4BtPXylZL55DFslCNlCeCz4gzXp/ft/bPhK6ihnEVSxgSSmzo1HkyJ36VtMoEGQ2nOk2ypY1yNSWkXzcggX8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760080114; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qoB4mQdJ5q/PSA40CHqGuTxSzS9aCnGI7d52zanhXww=; b=J5RtSoZmXBQu98kFe5jvJ3Yx1hTJ+HMJde8bEIqTx9BTWeCm0/d1COMvC70BWbecNDIlGVms7JvzMZmzBs6UfK45wcg/nj29yAF7vYM4IV60e/3DF9hq6oSUrkULOiKF8llRbUwrT3vyDHDMLwwLprWKLNVOcbeGqUnXJWvsICk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176008011436690.68163641333854; Fri, 10 Oct 2025 00:08:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v77EB-0001fd-3d; Fri, 10 Oct 2025 03:07:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v77E8-0001es-Vf for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:07:46 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v77E5-0007ye-6s for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:07:44 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-46e3af7889fso9342425e9.2 for ; Fri, 10 Oct 2025 00:07:39 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/openrisc); \ done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/openrisc/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 29e6b51a930..52d51313f77 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -622,7 +622,7 @@ static bool trans_l_lwa(DisasContext *dc, arg_load *a) check_r0_write(dc, a->d); ea =3D tcg_temp_new(); tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); - tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, MO_TEUL); + tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, MO_TE | MO_UL); tcg_gen_mov_tl(cpu_lock_addr, ea); tcg_gen_mov_tl(cpu_lock_value, cpu_R(dc, a->d)); return true; @@ -640,13 +640,13 @@ static void do_load(DisasContext *dc, arg_load *a, Me= mOp mop) =20 static bool trans_l_lwz(DisasContext *dc, arg_load *a) { - do_load(dc, a, MO_TEUL); + do_load(dc, a, MO_TE | MO_UL); return true; } =20 static bool trans_l_lws(DisasContext *dc, arg_load *a) { - do_load(dc, a, MO_TESL); + do_load(dc, a, MO_TE | MO_SL); return true; } =20 @@ -664,13 +664,13 @@ static bool trans_l_lbs(DisasContext *dc, arg_load *a) =20 static bool trans_l_lhz(DisasContext *dc, arg_load *a) { - do_load(dc, a, MO_TEUW); + do_load(dc, a, MO_TE | MO_UW); return true; } =20 static bool trans_l_lhs(DisasContext *dc, arg_load *a) { - do_load(dc, a, MO_TESW); + do_load(dc, a, MO_TE | MO_SW); return true; } =20 @@ -688,7 +688,7 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a) =20 val =3D tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, - cpu_R(dc, a->b), dc->mem_idx, MO_TEUL); + cpu_R(dc, a->b), dc->mem_idx, MO_TE | MO_UL); tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); =20 tcg_gen_br(lab_done); @@ -710,7 +710,7 @@ static void do_store(DisasContext *dc, arg_store *a, Me= mOp mop) =20 static bool trans_l_sw(DisasContext *dc, arg_store *a) { - do_store(dc, a, MO_TEUL); + do_store(dc, a, MO_TE | MO_UL); return true; } =20 @@ -722,7 +722,7 @@ static bool trans_l_sb(DisasContext *dc, arg_store *a) =20 static bool trans_l_sh(DisasContext *dc, arg_store *a) { - do_store(dc, a, MO_TEUW); + do_store(dc, a, MO_TE | MO_UW); return true; } =20 --=20 2.51.0 From nobody Fri Nov 14 18:19:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760080216; cv=none; d=zohomail.com; s=zohoarc; b=PQ+t0TVMjot3Kt9a8HlYXFLQ9bpxmKQ8kZBXj4jNRO4y2It3GtkcF9hACgdNdi3oKcIYoPE7AC0FeGWL6PcKWCqL1msPIKN53cqs2KI1GyIkLUEqngq1CQOq6UFhGtHJ0w0uKPG+CUwI1/HFoqyNgVQDkRuivNRRF04MvT2gRzo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760080216; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Mf9zsMIIBLVPDxYKWcw2p2yBA08+F1bZhOqIsBLAVw4=; b=SIqfqiO9Ne6f35Kg/PIlKsVrDhwSIYC9EN47NdB4R7zSswb3NUVpbk27lw1SqJNYGoHX1w2xvEmrqk+z4lV0BgCVJGvft/rBBEuAgv1gYXlSNvfWbqZ9434/oZt57t4GV/RIM3cMlVikzOFrN3cFuZb1Ah2snFK0MdxS30t0Ycs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17600802165825.719566237947902; Fri, 10 Oct 2025 00:10:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v77EE-0001gU-F8; Fri, 10 Oct 2025 03:07:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v77EB-0001fv-VI for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:07:47 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v77E9-0007z5-D8 for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:07:47 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-3fc36b99e92so2007569f8f.0 for ; Fri, 10 Oct 2025 00:07:44 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Fri, 10 Oct 2025 00:07:42 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Stafford Horne , Anton Johansson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 08/13] target/openrisc: Conceal MO_TE within do_load() Date: Fri, 10 Oct 2025 09:06:56 +0200 Message-ID: <20251010070702.51484-9-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251010070702.51484-1-philmd@linaro.org> References: <20251010070702.51484-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760080217985158500 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/openrisc/translate.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 52d51313f77..fe9128ea2fd 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -633,6 +633,7 @@ static void do_load(DisasContext *dc, arg_load *a, MemO= p mop) TCGv ea; =20 check_r0_write(dc, a->d); + mop |=3D MO_TE; ea =3D tcg_temp_new(); tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, mop); @@ -640,13 +641,13 @@ static void do_load(DisasContext *dc, arg_load *a, Me= mOp mop) =20 static bool trans_l_lwz(DisasContext *dc, arg_load *a) { - do_load(dc, a, MO_TE | MO_UL); + do_load(dc, a, MO_UL); return true; } =20 static bool trans_l_lws(DisasContext *dc, arg_load *a) { - do_load(dc, a, MO_TE | MO_SL); + do_load(dc, a, MO_SL); return true; } =20 @@ -664,13 +665,13 @@ static bool trans_l_lbs(DisasContext *dc, arg_load *a) =20 static bool trans_l_lhz(DisasContext *dc, arg_load *a) { - do_load(dc, a, MO_TE | MO_UW); + do_load(dc, a, MO_UW); return true; } =20 static bool trans_l_lhs(DisasContext *dc, arg_load *a) { - do_load(dc, a, MO_TE | MO_SW); + do_load(dc, a, MO_SW); return true; } =20 --=20 2.51.0 From nobody Fri Nov 14 18:19:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 10 Oct 2025 00:07:46 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Stafford Horne , Anton Johansson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 09/13] target/openrisc: Conceal MO_TE within do_store() Date: Fri, 10 Oct 2025 09:06:57 +0200 Message-ID: <20251010070702.51484-10-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251010070702.51484-1-philmd@linaro.org> References: <20251010070702.51484-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760080138078154100 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/openrisc/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index fe9128ea2fd..7363c45425e 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -705,13 +705,15 @@ static bool trans_l_swa(DisasContext *dc, arg_store *= a) static void do_store(DisasContext *dc, arg_store *a, MemOp mop) { TCGv t0 =3D tcg_temp_new(); + + mop |=3D MO_TE; tcg_gen_addi_tl(t0, cpu_R(dc, a->a), a->i); tcg_gen_qemu_st_tl(cpu_R(dc, a->b), t0, dc->mem_idx, mop); } =20 static bool trans_l_sw(DisasContext *dc, arg_store *a) { - do_store(dc, a, MO_TE | MO_UL); + do_store(dc, a, MO_UL); return true; } =20 @@ -723,7 +725,7 @@ static bool trans_l_sb(DisasContext *dc, arg_store *a) =20 static bool trans_l_sh(DisasContext *dc, arg_store *a) { - do_store(dc, a, MO_TE | MO_UW); + do_store(dc, a, MO_UW); return true; } =20 --=20 2.51.0 From nobody Fri Nov 14 18:19:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760080235; cv=none; d=zohomail.com; s=zohoarc; b=E0mFv+vCDjCp/6yJayo+iIsIXajA8fAzbFzj4P2BvuuyHi6KRA8x44VyOXSIyproPNBHcEcwFMqTEIvWTrrlC8j9uSgjqmvL/jGmK0L0W8dPY71odXUY+FvL3Iynr+nkFCMwcKusICiP6KGkSXRk6aRYZga2WxWBxlt9Lk+jPmY= ARC-Message-Signature: i=1; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/openrisc/translate.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 7363c45425e..6879a0cff80 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -59,6 +59,11 @@ typedef struct DisasContext { TCGv zero; } DisasContext; =20 +static inline MemOp mo_endian(DisasContext *dc) +{ + return MO_TE; +} + static inline bool is_user(DisasContext *dc) { #ifdef CONFIG_USER_ONLY @@ -622,7 +627,8 @@ static bool trans_l_lwa(DisasContext *dc, arg_load *a) check_r0_write(dc, a->d); ea =3D tcg_temp_new(); tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); - tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, MO_TE | MO_UL); + tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, + mo_endian(dc) | MO_UL); tcg_gen_mov_tl(cpu_lock_addr, ea); tcg_gen_mov_tl(cpu_lock_value, cpu_R(dc, a->d)); return true; @@ -633,7 +639,7 @@ static void do_load(DisasContext *dc, arg_load *a, MemO= p mop) TCGv ea; =20 check_r0_write(dc, a->d); - mop |=3D MO_TE; + mop |=3D mo_endian(dc); ea =3D tcg_temp_new(); tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, mop); @@ -689,7 +695,8 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a) =20 val =3D tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, - cpu_R(dc, a->b), dc->mem_idx, MO_TE | MO_UL); + cpu_R(dc, a->b), dc->mem_idx, + mo_endian(dc) | MO_UL); tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); =20 tcg_gen_br(lab_done); @@ -706,7 +713,7 @@ static void do_store(DisasContext *dc, arg_store *a, Me= mOp mop) { TCGv t0 =3D tcg_temp_new(); =20 - mop |=3D MO_TE; + mop |=3D mo_endian(dc); tcg_gen_addi_tl(t0, cpu_R(dc, a->a), a->i); tcg_gen_qemu_st_tl(cpu_R(dc, a->b), t0, dc->mem_idx, mop); } --=20 2.51.0 From nobody Fri Nov 14 18:19:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760080130; cv=none; d=zohomail.com; s=zohoarc; b=UbkxQ20nkssqOu1yMM6g1ad7fdJU3/LLxu9LaUsyEPnlqN4MI6lLGyY752Ki9bSYU0c59Er1uEvxQsc5zxLpxnsAtF+AjRzHH14jI321ITTFGZBjRCcggo9nGmXxOjnrDRCWZT1Npo4QOjZhR7DYpYQPhkvwbSmCqNUOedXxs0E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760080130; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=R/S+AbO3mfIrfPCoYS8ALK2aseZFhvV+JaaLQc6aYmk=; b=lM0jIH9A/I6ZZKhBMC8C13xkvEyVgHAfRdZ+KJiTU2pyO7TKuHTa4748/Zv9FNWVm4/T4z4hT9MH/H+Y8RuU4/HDvY0BWrvc+CxuVJthJ8ZSFAJtYDLI4IIZO81AHEV1JWttIdHqPLmmcBnryQORroZE3I3PitGo5LqbMXTlP14= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760080130053321.4264327952683; Fri, 10 Oct 2025 00:08:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v77ES-0001wY-0M; Fri, 10 Oct 2025 03:08:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v77EP-0001sE-H2 for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:08:01 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v77EN-00080H-GX for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:08:01 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-42557c5cedcso1020301f8f.0 for ; Fri, 10 Oct 2025 00:07:58 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Use the latter to simplify. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/openrisc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 6879a0cff80..a626ffaf25b 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -61,7 +61,7 @@ typedef struct DisasContext { =20 static inline MemOp mo_endian(DisasContext *dc) { - return MO_TE; + return MO_BE; } =20 static inline bool is_user(DisasContext *dc) --=20 2.51.0 From nobody Fri Nov 14 18:19:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760080158; cv=none; d=zohomail.com; s=zohoarc; b=XwTlm/gn0wHf2G/Efm1sLjAtz/ODhUkZe3noXRgbPsVIFgEwFMFmtEHAVCKjB0w3biJbt3X89PZezIO5m8KrS9DMBxwdV6mRcLrxgRePEAKIfoRe5qOVB778NdVD6j+dqevuE8maVGVy060NtynOESonTLSaiawvqAjsIfXTgbU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760080158; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0vS8HXyJHSXQcuzNI3sZRrJF0hK2dW0GVHTdSkTtKx4=; b=Np0v9iCST6+s1ykDF/WrxbfXwgq1UZJz7beYI24CUlM6R8+Yv8tox/bM+1aYWdUV0IRT7f7IUyrOgO9qUZk1BEJDlzBOfObwSqaiFklFtSmM5pZECfKZNhEoYJZjm0yglt078QweprA8enxQvSuxRgdLO23f25GZlxNd6dU290U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176008015839585.01014782185473; Fri, 10 Oct 2025 00:09:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v77Ej-00028x-1v; Fri, 10 Oct 2025 03:08:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v77Eb-00021u-Ey for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:08:15 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v77EU-000818-3W for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:08:12 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-45b4d89217aso9515705e9.2 for ; Fri, 10 Oct 2025 00:08:04 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Use the latter to simplify the next commit mechanical change. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson --- target/openrisc/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index a626ffaf25b..f33b9632d67 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -350,7 +350,7 @@ static void gen_macu(DisasContext *dc, TCGv srca, TCGv = srcb) /* Note that overflow is only computed during addition stage. */ tcg_gen_add_i64(cpu_mac, cpu_mac, t1); tcg_gen_setcond_i64(TCG_COND_LTU, t1, cpu_mac, t1); - tcg_gen_trunc_i64_tl(cpu_sr_cy, t1); + tcg_gen_extrl_i64_i32(cpu_sr_cy, t1); =20 gen_ove_cy(dc); } @@ -391,7 +391,7 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv = srcb) /* Note that overflow is only computed during subtraction stage. */ tcg_gen_setcond_i64(TCG_COND_LTU, t2, cpu_mac, t1); tcg_gen_sub_i64(cpu_mac, cpu_mac, t1); - tcg_gen_trunc_i64_tl(cpu_sr_cy, t2); + tcg_gen_extrl_i64_i32(cpu_sr_cy, t2); =20 gen_ove_cy(dc); } @@ -914,7 +914,7 @@ static bool trans_l_movhi(DisasContext *dc, arg_l_movhi= *a) static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a) { check_r0_write(dc, a->d); - tcg_gen_trunc_i64_tl(cpu_R(dc, a->d), cpu_mac); + tcg_gen_extrl_i64_i32(cpu_R(dc, a->d), cpu_mac); tcg_gen_movi_i64(cpu_mac, 0); return true; } --=20 2.51.0 From nobody Fri Nov 14 18:19:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760080136; cv=none; d=zohomail.com; s=zohoarc; b=H2p4AOta0a0HSBdtOAG4sGF/uHnoHhlK8Wk7UM+S9tCu5QKjeNXlcynBMdCYrwIVOw83ierGLtTilLGWO6X8KNiBO3WLWNAtRO2L/4l70pX6FG/onCImFuKrLBww9nCIRobf+4n++p7pGS+ndS8MNbyxiukk2lHkmKIKpEu4GEw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760080136; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=UCMyiC0mLy9lsD+lPps/0V1YotsK9zUvMMo1YEtM728=; b=eU6HLUO1N9+FIg7FDCbQrX1bN3WtiR11D6FuxapxexfFzHIKDltEeTEdV0UY3wxk11CMLeEklC7QsbdjkTKEW6Spc2PUoG0J4m0+t9jEcmRAO9rwqKwPnJdEF942A1VAzhYz8ZdPG9qKyMuiCYe9GKC17+uuPWVZqtPq10QNXIQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760080136442166.03341073709078; Fri, 10 Oct 2025 00:08:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v77Em-0002ET-9f; Fri, 10 Oct 2025 03:08:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v77Ej-00028w-F2 for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:08:22 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v77EZ-00081i-Rz for qemu-devel@nongnu.org; Fri, 10 Oct 2025 03:08:20 -0400 Received: by mail-wm1-x342.google.com with SMTP id 5b1f17b1804b1-46e504975dbso10097305e9.1 for ; Fri, 10 Oct 2025 00:08:09 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Replace and adapt the API uses mechanically: target_ulong -> uint32_t target_long -> int32_t tl -> i32 TCGv -> TCGv_i32 tcg_temp_new -> tcg_temp_new_i32 tcg_global_mem_new -> tcg_global_mem_new_i32 VMSTATE_UINTTL -> VMSTATE_UINT32 There is no functional change (the migration stream is not modified). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson --- target/openrisc/cpu.h | 22 +- target/openrisc/helper.h | 8 +- target/openrisc/fpu_helper.c | 8 +- target/openrisc/machine.c | 16 +- target/openrisc/sys_helper.c | 5 +- target/openrisc/translate.c | 392 ++++++++++++++++++----------------- 6 files changed, 228 insertions(+), 223 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 87201365a91..c8e2827930b 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -224,20 +224,20 @@ typedef struct CPUOpenRISCTLBContext { #endif =20 typedef struct CPUArchState { - target_ulong shadow_gpr[16][32]; /* Shadow registers */ + uint32_t shadow_gpr[16][32]; /* Shadow registers */ =20 - target_ulong pc; /* Program counter */ - target_ulong ppc; /* Prev PC */ - target_ulong jmp_pc; /* Jump PC */ + uint32_t pc; /* Program counter */ + uint32_t ppc; /* Prev PC */ + uint32_t jmp_pc; /* Jump PC */ =20 uint64_t mac; /* Multiply registers MACHI:MACLO */ =20 - target_ulong epcr; /* Exception PC register */ - target_ulong eear; /* Exception EA register */ + uint32_t epcr; /* Exception PC register */ + uint32_t eear; /* Exception EA register */ =20 - target_ulong sr_f; /* the SR_F bit, values 0, 1. */ - target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */ - target_long sr_ov; /* the SR_OV bit (in the sign bit only) */ + uint32_t sr_f; /* the SR_F bit, values 0, 1. */ + uint32_t sr_cy; /* the SR_CY bit, values 0, 1. */ + int32_t sr_ov; /* the SR_OV bit (in the sign bit only) */ uint32_t sr; /* Supervisor register, without SR_{F,CY,OV}= */ uint32_t esr; /* Exception supervisor register */ uint32_t evbar; /* Exception vector base address register */ @@ -245,8 +245,8 @@ typedef struct CPUArchState { uint32_t fpcsr; /* Float register */ float_status fp_status; =20 - target_ulong lock_addr; - target_ulong lock_value; + uint32_t lock_addr; + uint32_t lock_value; =20 uint32_t dflag; /* In delay slot (boolean) */ =20 diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h index d847814a28d..e0a8d402271 100644 --- a/target/openrisc/helper.h +++ b/target/openrisc/helper.h @@ -47,8 +47,8 @@ FOP_CALC(rem) #undef FOP_CALC =20 #define FOP_CMP(op) \ -DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_RWG, tl, env, i32, i32)= \ -DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, tl, env, i64, i64) +DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_RWG, i32, env, i32, i32= ) \ +DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, i32, env, i64, i64) FOP_CMP(eq) FOP_CMP(lt) FOP_CMP(le) @@ -62,5 +62,5 @@ FOP_CMP(ult) DEF_HELPER_FLAGS_1(rfe, 0, void, env) =20 /* sys */ -DEF_HELPER_FLAGS_3(mtspr, 0, void, env, tl, tl) -DEF_HELPER_FLAGS_3(mfspr, TCG_CALL_NO_WG, tl, env, tl, tl) +DEF_HELPER_FLAGS_3(mtspr, 0, void, env, i32, i32) +DEF_HELPER_FLAGS_3(mfspr, TCG_CALL_NO_WG, i32, env, i32, i32) diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index dba997255c6..39b6195dd7d 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -146,10 +146,10 @@ uint32_t helper_float_madd_s(CPUOpenRISCState *env, u= int32_t a, =20 =20 #define FLOAT_CMP(name, impl) \ -target_ulong helper_float_ ## name ## _d(CPUOpenRISCState *env, \ +uint32_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ uint64_t fdt0, uint64_t fdt1) \ { return float64_ ## impl(fdt0, fdt1, &env->fp_status); } \ -target_ulong helper_float_ ## name ## _s(CPUOpenRISCState *env, \ +uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ uint32_t fdt0, uint32_t fdt1) \ { return float32_ ## impl(fdt0, fdt1, &env->fp_status); } =20 @@ -160,13 +160,13 @@ FLOAT_CMP(un, unordered_quiet) #undef FLOAT_CMP =20 #define FLOAT_UCMP(name, expr) \ -target_ulong helper_float_ ## name ## _d(CPUOpenRISCState *env, \ +uint32_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ uint64_t fdt0, uint64_t fdt1) \ { \ FloatRelation r =3D float64_compare_quiet(fdt0, fdt1, &env->fp_status)= ; \ return expr; \ } \ -target_ulong helper_float_ ## name ## _s(CPUOpenRISCState *env, \ +uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ uint32_t fdt0, uint32_t fdt1) \ { \ FloatRelation r =3D float32_compare_quiet(fdt0, fdt1, &env->fp_status)= ; \ diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index fa054e528bd..f2853674f0f 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -72,14 +72,14 @@ static const VMStateDescription vmstate_env =3D { .version_id =3D 6, .minimum_version_id =3D 6, .fields =3D (const VMStateField[]) { - VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), - VMSTATE_UINTTL(pc, CPUOpenRISCState), - VMSTATE_UINTTL(ppc, CPUOpenRISCState), - VMSTATE_UINTTL(jmp_pc, CPUOpenRISCState), - VMSTATE_UINTTL(lock_addr, CPUOpenRISCState), - VMSTATE_UINTTL(lock_value, CPUOpenRISCState), - VMSTATE_UINTTL(epcr, CPUOpenRISCState), - VMSTATE_UINTTL(eear, CPUOpenRISCState), + VMSTATE_UINT32_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), + VMSTATE_UINT32(pc, CPUOpenRISCState), + VMSTATE_UINT32(ppc, CPUOpenRISCState), + VMSTATE_UINT32(jmp_pc, CPUOpenRISCState), + VMSTATE_UINT32(lock_addr, CPUOpenRISCState), + VMSTATE_UINT32(lock_value, CPUOpenRISCState), + VMSTATE_UINT32(epcr, CPUOpenRISCState), + VMSTATE_UINT32(eear, CPUOpenRISCState), =20 /* Save the architecture value of the SR, not the internally expanded version. Since this architecture value does not diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index ad59939db3b..7ad908b6322 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -40,7 +40,7 @@ static inline bool is_user(CPUOpenRISCState *env) #endif } =20 -void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong r= b) +void HELPER(mtspr)(CPUOpenRISCState *env, uint32_t spr, uint32_t rb) { OpenRISCCPU *cpu =3D env_archcpu(env); #ifndef CONFIG_USER_ONLY @@ -213,8 +213,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong = spr, target_ulong rb) #endif } =20 -target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, - target_ulong spr) +uint32_t HELPER(mfspr)(CPUOpenRISCState *env, uint32_t rd, uint32_t spr) { OpenRISCCPU *cpu =3D env_archcpu(env); #ifndef CONFIG_USER_ONLY diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index f33b9632d67..ba4dbd13794 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -54,9 +54,9 @@ typedef struct DisasContext { vaddr jmp_pc_imm; =20 /* The temporary corresponding to register 0 for this compilation. */ - TCGv R0; + TCGv_i32 R0; /* The constant zero. */ - TCGv zero; + TCGv_i32 zero; } DisasContext; =20 static inline MemOp mo_endian(DisasContext *dc) @@ -76,16 +76,16 @@ static inline bool is_user(DisasContext *dc) /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" =20 -static TCGv cpu_sr; -static TCGv cpu_regs[32]; -static TCGv cpu_pc; -static TCGv jmp_pc; /* l.jr/l.jalr temp pc */ -static TCGv cpu_ppc; -static TCGv cpu_sr_f; /* bf/bnf, F flag taken */ -static TCGv cpu_sr_cy; /* carry (unsigned overflow) */ -static TCGv cpu_sr_ov; /* signed overflow */ -static TCGv cpu_lock_addr; -static TCGv cpu_lock_value; +static TCGv_i32 cpu_sr; +static TCGv_i32 cpu_regs[32]; +static TCGv_i32 cpu_pc; +static TCGv_i32 jmp_pc; /* l.jr/l.jalr temp pc */ +static TCGv_i32 cpu_ppc; +static TCGv_i32 cpu_sr_f; /* bf/bnf, F flag taken */ +static TCGv_i32 cpu_sr_cy; /* carry (unsigned overflow) */ +static TCGv_i32 cpu_sr_ov; /* signed overflow */ +static TCGv_i32 cpu_lock_addr; +static TCGv_i32 cpu_lock_value; static TCGv_i32 fpcsr; static TCGv_i64 cpu_mac; /* MACHI:MACLO */ static TCGv_i32 cpu_dflag; @@ -100,27 +100,27 @@ void openrisc_translate_init(void) }; int i; =20 - cpu_sr =3D tcg_global_mem_new(tcg_env, + cpu_sr =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUOpenRISCState, sr), "sr"); cpu_dflag =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUOpenRISCState, dflag), "dflag"); - cpu_pc =3D tcg_global_mem_new(tcg_env, + cpu_pc =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUOpenRISCState, pc), "pc"); - cpu_ppc =3D tcg_global_mem_new(tcg_env, + cpu_ppc =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUOpenRISCState, ppc), "ppc"); - jmp_pc =3D tcg_global_mem_new(tcg_env, + jmp_pc =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUOpenRISCState, jmp_pc), "jmp_p= c"); - cpu_sr_f =3D tcg_global_mem_new(tcg_env, + cpu_sr_f =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUOpenRISCState, sr_f), "sr_f"= ); - cpu_sr_cy =3D tcg_global_mem_new(tcg_env, + cpu_sr_cy =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUOpenRISCState, sr_cy), "sr_= cy"); - cpu_sr_ov =3D tcg_global_mem_new(tcg_env, + cpu_sr_ov =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUOpenRISCState, sr_ov), "sr_= ov"); - cpu_lock_addr =3D tcg_global_mem_new(tcg_env, + cpu_lock_addr =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUOpenRISCState, lock_add= r), "lock_addr"); - cpu_lock_value =3D tcg_global_mem_new(tcg_env, + cpu_lock_value =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUOpenRISCState, lock_va= lue), "lock_value"); fpcsr =3D tcg_global_mem_new_i32(tcg_env, @@ -130,7 +130,7 @@ void openrisc_translate_init(void) offsetof(CPUOpenRISCState, mac), "mac"); for (i =3D 0; i < 32; i++) { - cpu_regs[i] =3D tcg_global_mem_new(tcg_env, + cpu_regs[i] =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUOpenRISCState, shadow_gpr[0][i]), regnames[i]); @@ -144,7 +144,7 @@ static void gen_exception(DisasContext *dc, unsigned in= t excp) =20 static void gen_illegal_exception(DisasContext *dc) { - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); gen_exception(dc, EXCP_ILLEGAL); dc->base.is_jmp =3D DISAS_NORETURN; } @@ -164,7 +164,7 @@ static bool check_of64a32s(DisasContext *dc) return dc->cpucfgr & CPUCFGR_OF64A32S; } =20 -static TCGv cpu_R(DisasContext *dc, int reg) +static TCGv_i32 cpu_R(DisasContext *dc, int reg) { if (reg =3D=3D 0) { return dc->R0; @@ -205,126 +205,133 @@ static void gen_ove_cyov(DisasContext *dc) } } =20 -static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) +static void gen_add(DisasContext *dc, TCGv_i32 dest, + TCGv_i32 srca, TCGv_i32 srcb) { - TCGv t0 =3D tcg_temp_new(); - TCGv res =3D tcg_temp_new(); + TCGv_i32 t0 =3D tcg_temp_new_i32(); + TCGv_i32 res =3D tcg_temp_new_i32(); =20 - tcg_gen_add2_tl(res, cpu_sr_cy, srca, dc->zero, srcb, dc->zero); - tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); - tcg_gen_xor_tl(t0, res, srcb); - tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); + tcg_gen_add2_i32(res, cpu_sr_cy, srca, dc->zero, srcb, dc->zero); + tcg_gen_xor_i32(cpu_sr_ov, srca, srcb); + tcg_gen_xor_i32(t0, res, srcb); + tcg_gen_andc_i32(cpu_sr_ov, t0, cpu_sr_ov); =20 - tcg_gen_mov_tl(dest, res); + tcg_gen_mov_i32(dest, res); =20 gen_ove_cyov(dc); } =20 -static void gen_addc(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) +static void gen_addc(DisasContext *dc, TCGv_i32 dest, + TCGv_i32 srca, TCGv_i32 srcb) { - TCGv t0 =3D tcg_temp_new(); - TCGv res =3D tcg_temp_new(); + TCGv_i32 t0 =3D tcg_temp_new_i32(); + TCGv_i32 res =3D tcg_temp_new_i32(); =20 - tcg_gen_addcio_tl(res, cpu_sr_cy, srca, srcb, cpu_sr_cy); - tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); - tcg_gen_xor_tl(t0, res, srcb); - tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); + tcg_gen_addcio_i32(res, cpu_sr_cy, srca, srcb, cpu_sr_cy); + tcg_gen_xor_i32(cpu_sr_ov, srca, srcb); + tcg_gen_xor_i32(t0, res, srcb); + tcg_gen_andc_i32(cpu_sr_ov, t0, cpu_sr_ov); =20 - tcg_gen_mov_tl(dest, res); + tcg_gen_mov_i32(dest, res); =20 gen_ove_cyov(dc); } =20 -static void gen_sub(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) +static void gen_sub(DisasContext *dc, TCGv_i32 dest, + TCGv_i32 srca, TCGv_i32 srcb) { - TCGv res =3D tcg_temp_new(); + TCGv_i32 res =3D tcg_temp_new_i32(); =20 - tcg_gen_sub_tl(res, srca, srcb); - tcg_gen_xor_tl(cpu_sr_cy, srca, srcb); - tcg_gen_xor_tl(cpu_sr_ov, res, srcb); - tcg_gen_and_tl(cpu_sr_ov, cpu_sr_ov, cpu_sr_cy); - tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_cy, srca, srcb); + tcg_gen_sub_i32(res, srca, srcb); + tcg_gen_xor_i32(cpu_sr_cy, srca, srcb); + tcg_gen_xor_i32(cpu_sr_ov, res, srcb); + tcg_gen_and_i32(cpu_sr_ov, cpu_sr_ov, cpu_sr_cy); + tcg_gen_setcond_i32(TCG_COND_LTU, cpu_sr_cy, srca, srcb); =20 - tcg_gen_mov_tl(dest, res); + tcg_gen_mov_i32(dest, res); =20 gen_ove_cyov(dc); } =20 -static void gen_mul(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) +static void gen_mul(DisasContext *dc, TCGv_i32 dest, + TCGv_i32 srca, TCGv_i32 srcb) { - TCGv t0 =3D tcg_temp_new(); + TCGv_i32 t0 =3D tcg_temp_new_i32(); =20 - tcg_gen_muls2_tl(dest, cpu_sr_ov, srca, srcb); - tcg_gen_sari_tl(t0, dest, TARGET_LONG_BITS - 1); - tcg_gen_negsetcond_tl(TCG_COND_NE, cpu_sr_ov, cpu_sr_ov, t0); + tcg_gen_muls2_i32(dest, cpu_sr_ov, srca, srcb); + tcg_gen_sari_i32(t0, dest, TARGET_LONG_BITS - 1); + tcg_gen_negsetcond_i32(TCG_COND_NE, cpu_sr_ov, cpu_sr_ov, t0); =20 gen_ove_ov(dc); } =20 -static void gen_mulu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) +static void gen_mulu(DisasContext *dc, TCGv_i32 dest, + TCGv_i32 srca, TCGv_i32 srcb) { - tcg_gen_muls2_tl(dest, cpu_sr_cy, srca, srcb); - tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_cy, cpu_sr_cy, 0); + tcg_gen_muls2_i32(dest, cpu_sr_cy, srca, srcb); + tcg_gen_setcondi_i32(TCG_COND_NE, cpu_sr_cy, cpu_sr_cy, 0); =20 gen_ove_cy(dc); } =20 -static void gen_div(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) +static void gen_div(DisasContext *dc, TCGv_i32 dest, + TCGv_i32 srca, TCGv_i32 srcb) { - TCGv t0 =3D tcg_temp_new(); + TCGv_i32 t0 =3D tcg_temp_new_i32(); =20 - tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_ov, srcb, 0); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_ov, srcb, 0); /* The result of divide-by-zero is undefined. Suppress the host-side exception by dividing by 1. */ - tcg_gen_or_tl(t0, srcb, cpu_sr_ov); - tcg_gen_div_tl(dest, srca, t0); + tcg_gen_or_i32(t0, srcb, cpu_sr_ov); + tcg_gen_div_i32(dest, srca, t0); =20 - tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); + tcg_gen_neg_i32(cpu_sr_ov, cpu_sr_ov); gen_ove_ov(dc); } =20 -static void gen_divu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) +static void gen_divu(DisasContext *dc, TCGv_i32 dest, + TCGv_i32 srca, TCGv_i32 srcb) { - TCGv t0 =3D tcg_temp_new(); + TCGv_i32 t0 =3D tcg_temp_new_i32(); =20 - tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_cy, srcb, 0); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_cy, srcb, 0); /* The result of divide-by-zero is undefined. Suppress the host-side exception by dividing by 1. */ - tcg_gen_or_tl(t0, srcb, cpu_sr_cy); - tcg_gen_divu_tl(dest, srca, t0); + tcg_gen_or_i32(t0, srcb, cpu_sr_cy); + tcg_gen_divu_i32(dest, srca, t0); =20 gen_ove_cy(dc); } =20 -static void gen_muld(DisasContext *dc, TCGv srca, TCGv srcb) +static void gen_muld(DisasContext *dc, TCGv_i32 srca, TCGv_i32 srcb) { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 - tcg_gen_ext_tl_i64(t1, srca); - tcg_gen_ext_tl_i64(t2, srcb); + tcg_gen_ext_i32_i64(t1, srca); + tcg_gen_ext_i32_i64(t2, srcb); tcg_gen_mul_i64(cpu_mac, t1, t2); - tcg_gen_movi_tl(cpu_sr_ov, 0); + tcg_gen_movi_i32(cpu_sr_ov, 0); } =20 -static void gen_muldu(DisasContext *dc, TCGv srca, TCGv srcb) +static void gen_muldu(DisasContext *dc, TCGv_i32 srca, TCGv_i32 srcb) { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 - tcg_gen_extu_tl_i64(t1, srca); - tcg_gen_extu_tl_i64(t2, srcb); + tcg_gen_extu_i32_i64(t1, srca); + tcg_gen_extu_i32_i64(t2, srcb); tcg_gen_mul_i64(cpu_mac, t1, t2); - tcg_gen_movi_tl(cpu_sr_cy, 0); + tcg_gen_movi_i32(cpu_sr_cy, 0); } =20 -static void gen_mac(DisasContext *dc, TCGv srca, TCGv srcb) +static void gen_mac(DisasContext *dc, TCGv_i32 srca, TCGv_i32 srcb) { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 - tcg_gen_ext_tl_i64(t1, srca); - tcg_gen_ext_tl_i64(t2, srcb); + tcg_gen_ext_i32_i64(t1, srca); + tcg_gen_ext_i32_i64(t2, srcb); tcg_gen_mul_i64(t1, t1, t2); =20 /* Note that overflow is only computed during addition stage. */ @@ -338,13 +345,13 @@ static void gen_mac(DisasContext *dc, TCGv srca, TCGv= srcb) gen_ove_ov(dc); } =20 -static void gen_macu(DisasContext *dc, TCGv srca, TCGv srcb) +static void gen_macu(DisasContext *dc, TCGv_i32 srca, TCGv_i32 srcb) { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 - tcg_gen_extu_tl_i64(t1, srca); - tcg_gen_extu_tl_i64(t2, srcb); + tcg_gen_extu_i32_i64(t1, srca); + tcg_gen_extu_i32_i64(t2, srcb); tcg_gen_mul_i64(t1, t1, t2); =20 /* Note that overflow is only computed during addition stage. */ @@ -355,13 +362,13 @@ static void gen_macu(DisasContext *dc, TCGv srca, TCG= v srcb) gen_ove_cy(dc); } =20 -static void gen_msb(DisasContext *dc, TCGv srca, TCGv srcb) +static void gen_msb(DisasContext *dc, TCGv_i32 srca, TCGv_i32 srcb) { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 - tcg_gen_ext_tl_i64(t1, srca); - tcg_gen_ext_tl_i64(t2, srcb); + tcg_gen_ext_i32_i64(t1, srca); + tcg_gen_ext_i32_i64(t2, srcb); tcg_gen_mul_i64(t1, t1, t2); =20 /* Note that overflow is only computed during subtraction stage. */ @@ -379,13 +386,13 @@ static void gen_msb(DisasContext *dc, TCGv srca, TCGv= srcb) gen_ove_ov(dc); } =20 -static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb) +static void gen_msbu(DisasContext *dc, TCGv_i32 srca, TCGv_i32 srcb) { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 - tcg_gen_extu_tl_i64(t1, srca); - tcg_gen_extu_tl_i64(t2, srcb); + tcg_gen_extu_i32_i64(t1, srca); + tcg_gen_extu_i32_i64(t2, srcb); tcg_gen_mul_i64(t1, t1, t2); =20 /* Note that overflow is only computed during subtraction stage. */ @@ -420,84 +427,84 @@ static bool trans_l_sub(DisasContext *dc, arg_dab *a) static bool trans_l_and(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - tcg_gen_and_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); + tcg_gen_and_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_or(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - tcg_gen_or_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); + tcg_gen_or_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_xor(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - tcg_gen_xor_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); + tcg_gen_xor_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sll(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - tcg_gen_shl_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); + tcg_gen_shl_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_srl(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - tcg_gen_shr_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); + tcg_gen_shr_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sra(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - tcg_gen_sar_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); + tcg_gen_sar_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_ror(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - tcg_gen_rotr_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); + tcg_gen_rotr_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_exths(DisasContext *dc, arg_da *a) { check_r0_write(dc, a->d); - tcg_gen_ext16s_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); + tcg_gen_ext16s_i32(cpu_R(dc, a->d), cpu_R(dc, a->a)); return true; } =20 static bool trans_l_extbs(DisasContext *dc, arg_da *a) { check_r0_write(dc, a->d); - tcg_gen_ext8s_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); + tcg_gen_ext8s_i32(cpu_R(dc, a->d), cpu_R(dc, a->a)); return true; } =20 static bool trans_l_exthz(DisasContext *dc, arg_da *a) { check_r0_write(dc, a->d); - tcg_gen_ext16u_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); + tcg_gen_ext16u_i32(cpu_R(dc, a->d), cpu_R(dc, a->a)); return true; } =20 static bool trans_l_extbz(DisasContext *dc, arg_da *a) { check_r0_write(dc, a->d); - tcg_gen_ext8u_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); + tcg_gen_ext8u_i32(cpu_R(dc, a->d), cpu_R(dc, a->a)); return true; } =20 static bool trans_l_cmov(DisasContext *dc, arg_dab *a) { check_r0_write(dc, a->d); - tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, dc->zero, + tcg_gen_movcond_i32(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, dc->zero, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } @@ -505,16 +512,16 @@ static bool trans_l_cmov(DisasContext *dc, arg_dab *a) static bool trans_l_ff1(DisasContext *dc, arg_da *a) { check_r0_write(dc, a->d); - tcg_gen_ctzi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), -1); - tcg_gen_addi_tl(cpu_R(dc, a->d), cpu_R(dc, a->d), 1); + tcg_gen_ctzi_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), -1); + tcg_gen_addi_i32(cpu_R(dc, a->d), cpu_R(dc, a->d), 1); return true; } =20 static bool trans_l_fl1(DisasContext *dc, arg_da *a) { check_r0_write(dc, a->d); - tcg_gen_clzi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), TARGET_LONG_BITS); - tcg_gen_subfi_tl(cpu_R(dc, a->d), TARGET_LONG_BITS, cpu_R(dc, a->d)); + tcg_gen_clzi_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), TARGET_LONG_BITS); + tcg_gen_subfi_i32(cpu_R(dc, a->d), TARGET_LONG_BITS, cpu_R(dc, a->d)); return true; } =20 @@ -562,7 +569,7 @@ static bool trans_l_j(DisasContext *dc, arg_l_j *a) { vaddr tmp_pc =3D dc->base.pc_next + a->n * 4; =20 - tcg_gen_movi_tl(jmp_pc, tmp_pc); + tcg_gen_movi_i32(jmp_pc, tmp_pc); dc->jmp_pc_imm =3D tmp_pc; dc->delayed_branch =3D 2; return true; @@ -573,10 +580,10 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *= a) vaddr tmp_pc =3D dc->base.pc_next + a->n * 4; vaddr ret_pc =3D dc->base.pc_next + 8; =20 - tcg_gen_movi_tl(cpu_regs[9], ret_pc); + tcg_gen_movi_i32(cpu_regs[9], ret_pc); /* Optimize jal being used to load the PC for PIC. */ if (tmp_pc !=3D ret_pc) { - tcg_gen_movi_tl(jmp_pc, tmp_pc); + tcg_gen_movi_i32(jmp_pc, tmp_pc); dc->jmp_pc_imm =3D tmp_pc; dc->delayed_branch =3D 2; } @@ -586,10 +593,10 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *= a) static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond) { vaddr tmp_pc =3D dc->base.pc_next + a->n * 4; - TCGv t_next =3D tcg_constant_tl(dc->base.pc_next + 8); - TCGv t_true =3D tcg_constant_tl(tmp_pc); + TCGv_i32 t_next =3D tcg_constant_i32(dc->base.pc_next + 8); + TCGv_i32 t_true =3D tcg_constant_i32(tmp_pc); =20 - tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, dc->zero, t_true, t_next); + tcg_gen_movcond_i32(cond, jmp_pc, cpu_sr_f, dc->zero, t_true, t_next); dc->delayed_branch =3D 2; } =20 @@ -607,42 +614,42 @@ static bool trans_l_bnf(DisasContext *dc, arg_l_bf *a) =20 static bool trans_l_jr(DisasContext *dc, arg_l_jr *a) { - tcg_gen_mov_tl(jmp_pc, cpu_R(dc, a->b)); + tcg_gen_mov_i32(jmp_pc, cpu_R(dc, a->b)); dc->delayed_branch =3D 2; return true; } =20 static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a) { - tcg_gen_mov_tl(jmp_pc, cpu_R(dc, a->b)); - tcg_gen_movi_tl(cpu_regs[9], dc->base.pc_next + 8); + tcg_gen_mov_i32(jmp_pc, cpu_R(dc, a->b)); + tcg_gen_movi_i32(cpu_regs[9], dc->base.pc_next + 8); dc->delayed_branch =3D 2; return true; } =20 static bool trans_l_lwa(DisasContext *dc, arg_load *a) { - TCGv ea; + TCGv_i32 ea; =20 check_r0_write(dc, a->d); - ea =3D tcg_temp_new(); - tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); - tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, - mo_endian(dc) | MO_UL); - tcg_gen_mov_tl(cpu_lock_addr, ea); - tcg_gen_mov_tl(cpu_lock_value, cpu_R(dc, a->d)); + ea =3D tcg_temp_new_i32(); + tcg_gen_addi_i32(ea, cpu_R(dc, a->a), a->i); + tcg_gen_qemu_ld_i32(cpu_R(dc, a->d), ea, dc->mem_idx, + mo_endian(dc) | MO_UL); + tcg_gen_mov_i32(cpu_lock_addr, ea); + tcg_gen_mov_i32(cpu_lock_value, cpu_R(dc, a->d)); return true; } =20 static void do_load(DisasContext *dc, arg_load *a, MemOp mop) { - TCGv ea; + TCGv_i32 ea; =20 check_r0_write(dc, a->d); mop |=3D mo_endian(dc); - ea =3D tcg_temp_new(); - tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); - tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, mop); + ea =3D tcg_temp_new_i32(); + tcg_gen_addi_i32(ea, cpu_R(dc, a->a), a->i); + tcg_gen_qemu_ld_i32(cpu_R(dc, a->d), ea, dc->mem_idx, mop); } =20 static bool trans_l_lwz(DisasContext *dc, arg_load *a) @@ -683,39 +690,38 @@ static bool trans_l_lhs(DisasContext *dc, arg_load *a) =20 static bool trans_l_swa(DisasContext *dc, arg_store *a) { - TCGv ea, val; + TCGv_i32 ea, val; TCGLabel *lab_fail, *lab_done; =20 - ea =3D tcg_temp_new(); - tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); + ea =3D tcg_temp_new_i32(); + tcg_gen_addi_i32(ea, cpu_R(dc, a->a), a->i); =20 lab_fail =3D gen_new_label(); lab_done =3D gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); + tcg_gen_brcond_i32(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); =20 - val =3D tcg_temp_new(); - tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, + val =3D tcg_temp_new_i32(); + tcg_gen_atomic_cmpxchg_i32(val, cpu_lock_addr, cpu_lock_value, cpu_R(dc, a->b), dc->mem_idx, mo_endian(dc) | MO_UL); - tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); + tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); =20 tcg_gen_br(lab_done); =20 gen_set_label(lab_fail); - tcg_gen_movi_tl(cpu_sr_f, 0); + tcg_gen_movi_i32(cpu_sr_f, 0); =20 gen_set_label(lab_done); - tcg_gen_movi_tl(cpu_lock_addr, -1); + tcg_gen_movi_i32(cpu_lock_addr, -1); return true; } =20 static void do_store(DisasContext *dc, arg_store *a, MemOp mop) { - TCGv t0 =3D tcg_temp_new(); - + TCGv_i32 t0 =3D tcg_temp_new_i32(); mop |=3D mo_endian(dc); - tcg_gen_addi_tl(t0, cpu_R(dc, a->a), a->i); - tcg_gen_qemu_st_tl(cpu_R(dc, a->b), t0, dc->mem_idx, mop); + tcg_gen_addi_i32(t0, cpu_R(dc, a->a), a->i); + tcg_gen_qemu_st_i32(cpu_R(dc, a->b), t0, dc->mem_idx, mop); } =20 static bool trans_l_sw(DisasContext *dc, arg_store *a) @@ -757,75 +763,75 @@ static bool trans_l_adrp(DisasContext *dc, arg_l_adrp= *a) static bool trans_l_addi(DisasContext *dc, arg_rri *a) { check_r0_write(dc, a->d); - gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i)); + gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_i32(a->i)); return true; } =20 static bool trans_l_addic(DisasContext *dc, arg_rri *a) { check_r0_write(dc, a->d); - gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i)); + gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_i32(a->i)); return true; } =20 static bool trans_l_muli(DisasContext *dc, arg_rri *a) { check_r0_write(dc, a->d); - gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i)); + gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_i32(a->i)); return true; } =20 static bool trans_l_maci(DisasContext *dc, arg_l_maci *a) { - gen_mac(dc, cpu_R(dc, a->a), tcg_constant_tl(a->i)); + gen_mac(dc, cpu_R(dc, a->a), tcg_constant_i32(a->i)); return true; } =20 static bool trans_l_andi(DisasContext *dc, arg_rrk *a) { check_r0_write(dc, a->d); - tcg_gen_andi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->k); + tcg_gen_andi_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), a->k); return true; } =20 static bool trans_l_ori(DisasContext *dc, arg_rrk *a) { check_r0_write(dc, a->d); - tcg_gen_ori_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->k); + tcg_gen_ori_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), a->k); return true; } =20 static bool trans_l_xori(DisasContext *dc, arg_rri *a) { check_r0_write(dc, a->d); - tcg_gen_xori_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->i); + tcg_gen_xori_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a) { - TCGv spr =3D tcg_temp_new(); + TCGv_i32 spr =3D tcg_temp_new_i32(); =20 check_r0_write(dc, a->d); =20 if (translator_io_start(&dc->base)) { if (dc->delayed_branch) { - tcg_gen_mov_tl(cpu_pc, jmp_pc); - tcg_gen_discard_tl(jmp_pc); + tcg_gen_mov_i32(cpu_pc, jmp_pc); + tcg_gen_discard_i32(jmp_pc); } else { - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); } dc->base.is_jmp =3D DISAS_EXIT; } =20 - tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); + tcg_gen_ori_i32(spr, cpu_R(dc, a->a), a->k); gen_helper_mfspr(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->d), spr); return true; } =20 static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) { - TCGv spr =3D tcg_temp_new(); + TCGv_i32 spr =3D tcg_temp_new_i32(); =20 translator_io_start(&dc->base); =20 @@ -836,14 +842,14 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mts= pr *a) * of the cpu state first, allowing it to be overwritten. */ if (dc->delayed_branch) { - tcg_gen_mov_tl(cpu_pc, jmp_pc); - tcg_gen_discard_tl(jmp_pc); + tcg_gen_mov_i32(cpu_pc, jmp_pc); + tcg_gen_discard_i32(jmp_pc); } else { - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); } dc->base.is_jmp =3D DISAS_EXIT; =20 - tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); + tcg_gen_ori_i32(spr, cpu_R(dc, a->a), a->k); gen_helper_mtspr(tcg_env, spr, cpu_R(dc, a->b)); return true; } @@ -875,7 +881,7 @@ static bool trans_l_msbu(DisasContext *dc, arg_ab *a) static bool trans_l_slli(DisasContext *dc, arg_dal *a) { check_r0_write(dc, a->d); - tcg_gen_shli_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), + tcg_gen_shli_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), a->l & (TARGET_LONG_BITS - 1)); return true; } @@ -883,7 +889,7 @@ static bool trans_l_slli(DisasContext *dc, arg_dal *a) static bool trans_l_srli(DisasContext *dc, arg_dal *a) { check_r0_write(dc, a->d); - tcg_gen_shri_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), + tcg_gen_shri_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), a->l & (TARGET_LONG_BITS - 1)); return true; } @@ -891,7 +897,7 @@ static bool trans_l_srli(DisasContext *dc, arg_dal *a) static bool trans_l_srai(DisasContext *dc, arg_dal *a) { check_r0_write(dc, a->d); - tcg_gen_sari_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), + tcg_gen_sari_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), a->l & (TARGET_LONG_BITS - 1)); return true; } @@ -899,7 +905,7 @@ static bool trans_l_srai(DisasContext *dc, arg_dal *a) static bool trans_l_rori(DisasContext *dc, arg_dal *a) { check_r0_write(dc, a->d); - tcg_gen_rotri_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), + tcg_gen_rotri_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), a->l & (TARGET_LONG_BITS - 1)); return true; } @@ -907,7 +913,7 @@ static bool trans_l_rori(DisasContext *dc, arg_dal *a) static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a) { check_r0_write(dc, a->d); - tcg_gen_movi_tl(cpu_R(dc, a->d), a->k << 16); + tcg_gen_movi_i32(cpu_R(dc, a->d), a->k << 16); return true; } =20 @@ -921,137 +927,137 @@ static bool trans_l_macrc(DisasContext *dc, arg_l_m= acrc *a) =20 static bool trans_l_sfeq(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, + tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_f, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfne(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, + tcg_gen_setcond_i32(TCG_COND_NE, cpu_sr_f, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, + tcg_gen_setcond_i32(TCG_COND_GTU, cpu_sr_f, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, + tcg_gen_setcond_i32(TCG_COND_GEU, cpu_sr_f, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfltu(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, + tcg_gen_setcond_i32(TCG_COND_LTU, cpu_sr_f, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfleu(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, + tcg_gen_setcond_i32(TCG_COND_LEU, cpu_sr_f, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfgts(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, + tcg_gen_setcond_i32(TCG_COND_GT, cpu_sr_f, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfges(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, + tcg_gen_setcond_i32(TCG_COND_GE, cpu_sr_f, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sflts(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, + tcg_gen_setcond_i32(TCG_COND_LT, cpu_sr_f, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfles(DisasContext *dc, arg_ab *a) { - tcg_gen_setcond_tl(TCG_COND_LE, + tcg_gen_setcond_i32(TCG_COND_LE, cpu_sr_f, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } =20 static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R(dc, a->a), a->i); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sfnei(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R(dc, a->a), a->i); + tcg_gen_setcondi_i32(TCG_COND_NE, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R(dc, a->a), a->i); + tcg_gen_setcondi_i32(TCG_COND_GTU, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R(dc, a->a), a->i); + tcg_gen_setcondi_i32(TCG_COND_GEU, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sfltui(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R(dc, a->a), a->i); + tcg_gen_setcondi_i32(TCG_COND_LTU, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sfleui(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R(dc, a->a), a->i); + tcg_gen_setcondi_i32(TCG_COND_LEU, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R(dc, a->a), a->i); + tcg_gen_setcondi_i32(TCG_COND_GT, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R(dc, a->a), a->i); + tcg_gen_setcondi_i32(TCG_COND_GE, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R(dc, a->a), a->i); + tcg_gen_setcondi_i32(TCG_COND_LT, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sflesi(DisasContext *dc, arg_ai *a) { - tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R(dc, a->a), a->i); + tcg_gen_setcondi_i32(TCG_COND_LE, cpu_sr_f, cpu_R(dc, a->a), a->i); return true; } =20 static bool trans_l_sys(DisasContext *dc, arg_l_sys *a) { - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); gen_exception(dc, EXCP_SYSCALL); dc->base.is_jmp =3D DISAS_NORETURN; return true; @@ -1059,7 +1065,7 @@ static bool trans_l_sys(DisasContext *dc, arg_l_sys *= a) =20 static bool trans_l_trap(DisasContext *dc, arg_l_trap *a) { - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); gen_exception(dc, EXCP_TRAP); dc->base.is_jmp =3D DISAS_NORETURN; return true; @@ -1093,7 +1099,7 @@ static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *= a) } =20 static bool do_fp2(DisasContext *dc, arg_da *a, - void (*fn)(TCGv, TCGv_env, TCGv)) + void (*fn)(TCGv_i32, TCGv_env, TCGv_i32)) { if (!check_of32s(dc)) { return false; @@ -1105,7 +1111,7 @@ static bool do_fp2(DisasContext *dc, arg_da *a, } =20 static bool do_fp3(DisasContext *dc, arg_dab *a, - void (*fn)(TCGv, TCGv_env, TCGv, TCGv)) + void (*fn)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)) { if (!check_of32s(dc)) { return false; @@ -1117,7 +1123,7 @@ static bool do_fp3(DisasContext *dc, arg_dab *a, } =20 static bool do_fpcmp(DisasContext *dc, arg_ab *a, - void (*fn)(TCGv, TCGv_env, TCGv, TCGv), + void (*fn)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32), bool inv, bool swap) { if (!check_of32s(dc)) { @@ -1129,7 +1135,7 @@ static bool do_fpcmp(DisasContext *dc, arg_ab *a, fn(cpu_sr_f, tcg_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); } if (inv) { - tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); + tcg_gen_xori_i32(cpu_sr_f, cpu_sr_f, 1); } gen_helper_update_fpcsr(tcg_env); return true; @@ -1322,7 +1328,7 @@ static bool do_dp2(DisasContext *dc, arg_da_pair *a, } =20 static bool do_dpcmp(DisasContext *dc, arg_ab_pair *a, - void (*fn)(TCGv, TCGv_env, TCGv_i64, TCGv_i64), + void (*fn)(TCGv_i32, TCGv_env, TCGv_i64, TCGv_i64), bool inv, bool swap) { TCGv_i64 t0, t1; @@ -1344,7 +1350,7 @@ static bool do_dpcmp(DisasContext *dc, arg_ab_pair *a, } =20 if (inv) { - tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); + tcg_gen_xori_i32(cpu_sr_f, cpu_sr_f, 1); } gen_helper_update_fpcsr(tcg_env); return true; @@ -1529,7 +1535,7 @@ static void openrisc_tr_tb_start(DisasContextBase *db= , CPUState *cs) =20 /* Allow the TCG optimizer to see that R0 =3D=3D 0, when it's true, which is the common case. */ - dc->zero =3D tcg_constant_tl(0); + dc->zero =3D tcg_constant_i32(0); if (dc->tb_flags & TB_FLAGS_R0_0) { dc->R0 =3D dc->zero; } else { @@ -1585,32 +1591,32 @@ static void openrisc_tr_tb_stop(DisasContextBase *d= cbase, CPUState *cs) =20 /* For DISAS_TOO_MANY, jump to the next insn. */ jmp_dest =3D dc->base.pc_next; - tcg_gen_movi_tl(cpu_ppc, jmp_dest - 4); + tcg_gen_movi_i32(cpu_ppc, jmp_dest - 4); =20 switch (dc->base.is_jmp) { case DISAS_JUMP: jmp_dest =3D dc->jmp_pc_imm; if (jmp_dest =3D=3D -1) { /* The jump destination is indirect/computed; use jmp_pc. */ - tcg_gen_mov_tl(cpu_pc, jmp_pc); - tcg_gen_discard_tl(jmp_pc); + tcg_gen_mov_i32(cpu_pc, jmp_pc); + tcg_gen_discard_i32(jmp_pc); tcg_gen_lookup_and_goto_ptr(); break; } /* The jump destination is direct; use jmp_pc_imm. However, we will have stored into jmp_pc as well; we know now that it wasn't needed. */ - tcg_gen_discard_tl(jmp_pc); + tcg_gen_discard_i32(jmp_pc); /* fallthru */ =20 case DISAS_TOO_MANY: if (translator_use_goto_tb(&dc->base, jmp_dest)) { tcg_gen_goto_tb(0); - tcg_gen_movi_tl(cpu_pc, jmp_dest); + tcg_gen_movi_i32(cpu_pc, jmp_dest); tcg_gen_exit_tb(dc->base.tb, 0); break; } - tcg_gen_movi_tl(cpu_pc, jmp_dest); + tcg_gen_movi_i32(cpu_pc, jmp_dest); tcg_gen_lookup_and_goto_ptr(); break; =20 --=20 2.51.0