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Update the 2 callers. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/rx/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/rx/translate.c b/target/rx/translate.c index 19a9584a829..c22ca78a055 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -85,7 +85,7 @@ static uint32_t decode_load_bytes(DisasContext *ctx, uint= 32_t insn, =20 static uint32_t li(DisasContext *ctx, int sz) { - target_ulong addr; + vaddr addr; uint32_t tmp; CPURXState *env =3D ctx->env; addr =3D ctx->base.pc_next; @@ -147,7 +147,7 @@ void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } =20 -static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) +static void gen_goto_tb(DisasContext *dc, int n, vaddr dest) { if (translator_use_goto_tb(&dc->base, dest)) { tcg_gen_goto_tb(n); --=20 2.51.0 From nobody Fri Nov 14 18:17:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760023063; cv=none; d=zohomail.com; s=zohoarc; b=lim8qyBEBKh4lofUbGCByGG656nSi0UFcX4mVoZ5MNvGII2YNoBmr+91wzBUAql776CYltcZfFnhkyqcDvsE4EOjQUDeLeWYaLgTAl86ZtzBCK8Mi9Rl1E+nbLVD5QJ9Tqf3mI2qXnFO3zvYAMoOvm8yNS6xN0LPiHgD2j+Cze0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760023063; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CR4uK/LFS4qCC5cLf+9cRuqkH8EtKE5g9jNBAjT6o58=; b=Cfy+UDr5eaJwuXM6iHPq7LUG1/g7X/uxzcKc/0TpW8Ntuymp3kRrwj4exIFsZH8iaeVcoJ0t3TvRu/rWURIW/FiYd02ElvAgwT+g+APc69ljqmogcNQFmN3EdHtSpsKLB8GQ45KOQOlWNZBrO+Ndz8oRM7a8+Baz4W7VMtZtG30= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176002306396759.53202880176525; Thu, 9 Oct 2025 08:17:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v6sNc-00013V-MJ; Thu, 09 Oct 2025 11:16:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v6sNa-00013M-Gh for qemu-devel@nongnu.org; Thu, 09 Oct 2025 11:16:30 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v6sNS-00012p-Vu for qemu-devel@nongnu.org; Thu, 09 Oct 2025 11:16:30 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-46e29d65728so6717915e9.3 for ; Thu, 09 Oct 2025 08:16:22 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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All callers respect that. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/rx/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/rx/translate.c b/target/rx/translate.c index c22ca78a055..9a2be2107bd 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -161,19 +161,19 @@ static void gen_goto_tb(DisasContext *dc, int n, vadd= r dest) } =20 /* generic load wrapper */ -static inline void rx_gen_ld(unsigned int size, TCGv reg, TCGv mem) +static inline void rx_gen_ld(MemOp size, TCGv reg, TCGv mem) { tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE); } =20 /* unsigned load wrapper */ -static inline void rx_gen_ldu(unsigned int size, TCGv reg, TCGv mem) +static inline void rx_gen_ldu(MemOp size, TCGv reg, TCGv mem) { tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_TE); } =20 /* generic store wrapper */ -static inline void rx_gen_st(unsigned int size, TCGv reg, TCGv mem) +static inline void rx_gen_st(MemOp size, TCGv reg, TCGv mem) { tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE); } --=20 2.51.0 From nobody Fri Nov 14 18:17:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760023063; cv=none; d=zohomail.com; s=zohoarc; b=S/9MuO1PBu1OP43MBmENNxTbovLbPgGxtvyhybVUkrKG9hcOi2XcWG8HtqEe9Ax18s8eIVuSEfSKcuIyT+gKs1ku2IMHsW8BZ1t8nXrgPaDxamqtEBdEQM7Z918zvmlfLAoZdZGmY+a3azN18NFnwum4TFeu11xPnFQxp9zE7o8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760023063; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WMpGbvMM36NwbK8kSwDRJa9hCDWv5SxuYSTE3Zgo8Kw=; b=m5IoLR+roAw9BTjVGsFyyhGmz7zwz3C7yCw0/N19JgV4rU7htH0P8HsqIJCnQqeC6DeOD4h6CcBNAlEn+gJZxlmNoNNY/luwydVBGTfIYSBy3QQxRemiGr7Jea28XEqTrQ9i45aEPLjM6KOpWmHuBLkTppBGJ2lkaDlY0EtFrC0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760023063516851.7541858935699; Thu, 9 Oct 2025 08:17:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v6sNk-000149-68; Thu, 09 Oct 2025 11:16:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v6sNd-00013k-Ma for qemu-devel@nongnu.org; Thu, 09 Oct 2025 11:16:33 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v6sNX-00013H-Sq for qemu-devel@nongnu.org; Thu, 09 Oct 2025 11:16:33 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-46e3af7889fso5978065e9.2 for ; Thu, 09 Oct 2025 08:16:26 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Thu, 09 Oct 2025 08:16:24 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Yoshinori Sato , Anton Johansson , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 3/8] target/rx: Propagate DisasContext to generated helpers Date: Thu, 9 Oct 2025 17:16:02 +0200 Message-ID: <20251009151607.26278-4-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251009151607.26278-1-philmd@linaro.org> References: <20251009151607.26278-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760023070760116600 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/rx/translate.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/rx/translate.c b/target/rx/translate.c index 9a2be2107bd..f02a8cc5dc9 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -1894,7 +1894,7 @@ static bool trans_ITOF(DisasContext *ctx, arg_ITOF * = a) return true; } =20 -static void rx_bsetm(TCGv mem, TCGv mask) +static void rx_bsetm(DisasContext *ctx, TCGv mem, TCGv mask) { TCGv val; val =3D tcg_temp_new(); @@ -1903,7 +1903,7 @@ static void rx_bsetm(TCGv mem, TCGv mask) rx_gen_st(MO_8, val, mem); } =20 -static void rx_bclrm(TCGv mem, TCGv mask) +static void rx_bclrm(DisasContext *ctx, TCGv mem, TCGv mask) { TCGv val; val =3D tcg_temp_new(); @@ -1912,7 +1912,7 @@ static void rx_bclrm(TCGv mem, TCGv mask) rx_gen_st(MO_8, val, mem); } =20 -static void rx_btstm(TCGv mem, TCGv mask) +static void rx_btstm(DisasContext *ctx, TCGv mem, TCGv mask) { TCGv val; val =3D tcg_temp_new(); @@ -1922,7 +1922,7 @@ static void rx_btstm(TCGv mem, TCGv mask) tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); } =20 -static void rx_bnotm(TCGv mem, TCGv mask) +static void rx_bnotm(DisasContext *ctx, TCGv mem, TCGv mask) { TCGv val; val =3D tcg_temp_new(); @@ -1931,17 +1931,17 @@ static void rx_bnotm(TCGv mem, TCGv mask) rx_gen_st(MO_8, val, mem); } =20 -static void rx_bsetr(TCGv reg, TCGv mask) +static void rx_bsetr(DisasContext *ctx, TCGv reg, TCGv mask) { tcg_gen_or_i32(reg, reg, mask); } =20 -static void rx_bclrr(TCGv reg, TCGv mask) +static void rx_bclrr(DisasContext *ctx, TCGv reg, TCGv mask) { tcg_gen_andc_i32(reg, reg, mask); } =20 -static inline void rx_btstr(TCGv reg, TCGv mask) +static inline void rx_btstr(DisasContext *ctx, TCGv reg, TCGv mask) { TCGv t0; t0 =3D tcg_temp_new(); @@ -1950,7 +1950,7 @@ static inline void rx_btstr(TCGv reg, TCGv mask) tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); } =20 -static inline void rx_bnotr(TCGv reg, TCGv mask) +static inline void rx_bnotr(DisasContext *ctx, TCGv reg, TCGv mask) { tcg_gen_xor_i32(reg, reg, mask); } @@ -1963,7 +1963,7 @@ static inline void rx_bnotr(TCGv reg, TCGv mask) mem =3D tcg_temp_new(); \ mask =3D tcg_constant_i32(1 << a->imm); \ addr =3D rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ - cat3(rx_, op, m)(addr, mask); \ + cat3(rx_, op, m)(ctx, addr, mask); \ return true; \ } \ static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ @@ -1971,7 +1971,7 @@ static inline void rx_bnotr(TCGv reg, TCGv mask) { \ TCGv mask; \ mask =3D tcg_constant_i32(1 << a->imm); \ - cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ + cat3(rx_, op, r)(ctx, cpu_regs[a->rd], mask); \ return true; \ } \ static bool cat3(trans_, name, _rr)(DisasContext *ctx, \ @@ -1982,7 +1982,7 @@ static inline void rx_bnotr(TCGv reg, TCGv mask) b =3D tcg_temp_new(); \ tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \ tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \ - cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ + cat3(rx_, op, r)(ctx, cpu_regs[a->rd], mask); \ return true; \ } \ static bool cat3(trans_, name, _rm)(DisasContext *ctx, \ @@ -1995,7 +1995,7 @@ static inline void rx_bnotr(TCGv reg, TCGv mask) tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \ mem =3D tcg_temp_new(); \ addr =3D rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ - cat3(rx_, op, m)(addr, mask); \ + cat3(rx_, op, m)(ctx, addr, mask); \ return true; \ } =20 --=20 2.51.0 From nobody Fri Nov 14 18:17:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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Thu, 09 Oct 2025 08:16:28 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Yoshinori Sato , Anton Johansson , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 4/8] target/rx: Propagate DisasContext to push() / pop() Date: Thu, 9 Oct 2025 17:16:03 +0200 Message-ID: <20251009151607.26278-5-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251009151607.26278-1-philmd@linaro.org> References: <20251009151607.26278-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=philmd@linaro.org; helo=mail-wm1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760023141636116600 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/rx/translate.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/target/rx/translate.c b/target/rx/translate.c index f02a8cc5dc9..0d5356cd35d 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -414,13 +414,13 @@ static void move_to_cr(DisasContext *ctx, TCGv val, i= nt cr) } } =20 -static void push(TCGv val) +static void push(DisasContext *ctx, TCGv val) { tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); rx_gen_st(MO_32, val, cpu_sp); } =20 -static void pop(TCGv ret) +static void pop(DisasContext *ctx, TCGv ret) { rx_gen_ld(MO_32, ret, cpu_sp); tcg_gen_addi_i32(cpu_sp, cpu_sp, 4); @@ -619,7 +619,7 @@ static bool trans_POPC(DisasContext *ctx, arg_POPC *a) { TCGv val; val =3D tcg_temp_new(); - pop(val); + pop(ctx, val); move_to_cr(ctx, val, a->cr); return true; } @@ -634,7 +634,7 @@ static bool trans_POPM(DisasContext *ctx, arg_POPM *a) } r =3D a->rd; while (r <=3D a->rd2 && r < 16) { - pop(cpu_regs[r++]); + pop(ctx, cpu_regs[r++]); } return true; } @@ -670,7 +670,7 @@ static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a) TCGv val; val =3D tcg_temp_new(); move_from_cr(ctx, val, a->cr, ctx->pc); - push(val); + push(ctx, val); return true; } =20 @@ -685,7 +685,7 @@ static bool trans_PUSHM(DisasContext *ctx, arg_PUSHM *a) } r =3D a->rs2; while (r >=3D a->rs && r >=3D 0) { - push(cpu_regs[r--]); + push(ctx, cpu_regs[r--]); } return true; } @@ -772,7 +772,7 @@ static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a) static bool trans_RTSD_i(DisasContext *ctx, arg_RTSD_i *a) { tcg_gen_addi_i32(cpu_sp, cpu_sp, a->imm << 2); - pop(cpu_pc); + pop(ctx, cpu_pc); ctx->base.is_jmp =3D DISAS_JUMP; return true; } @@ -792,9 +792,9 @@ static bool trans_RTSD_irr(DisasContext *ctx, arg_RTSD_= irr *a) tcg_gen_addi_i32(cpu_sp, cpu_sp, adj << 2); dst =3D a->rd; while (dst <=3D a->rd2 && dst < 16) { - pop(cpu_regs[dst++]); + pop(ctx, cpu_regs[dst++]); } - pop(cpu_pc); + pop(ctx, cpu_pc); ctx->base.is_jmp =3D DISAS_JUMP; return true; } @@ -1585,7 +1585,7 @@ static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l = *a) static inline void rx_save_pc(DisasContext *ctx) { TCGv pc =3D tcg_constant_i32(ctx->base.pc_next); - push(pc); + push(ctx, pc); } =20 /* jmp rs */ @@ -1626,7 +1626,7 @@ static bool trans_BSR_l(DisasContext *ctx, arg_BSR_l = *a) /* rts */ static bool trans_RTS(DisasContext *ctx, arg_RTS *a) { - pop(cpu_pc); + pop(ctx, cpu_pc); ctx->base.is_jmp =3D DISAS_JUMP; return true; } @@ -2154,8 +2154,8 @@ static bool trans_RTE(DisasContext *ctx, arg_RTE *a) TCGv psw; if (is_privileged(ctx, 1)) { psw =3D tcg_temp_new(); - pop(cpu_pc); - pop(psw); + pop(ctx, cpu_pc); + pop(ctx, psw); gen_helper_set_psw_rte(tcg_env, psw); ctx->base.is_jmp =3D DISAS_EXIT; } --=20 2.51.0 From nobody Fri Nov 14 18:17:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760023068; cv=none; d=zohomail.com; s=zohoarc; b=ieHhqcpUk4/vj/L1VXM6xiO7/ZxvJck/dBMMjviQcJu7ZRd91T5vPxiORMrzlif+BsUh8JX3YwGudUA46svlUqK9nP9vTSVg5+EfngF6pXLq/5N/t9oxphZZHBErkIPh56f2kfTjK/zp8bmolAmonxkeIUYV/wGoZQK0GLzbxUc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760023068; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 09 Oct 2025 08:16:34 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Yoshinori Sato , Anton Johansson , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 5/8] target/rx: Propagate DisasContext to gen_ld[u]() and gen_st() Date: Thu, 9 Oct 2025 17:16:04 +0200 Message-ID: <20251009151607.26278-6-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251009151607.26278-1-philmd@linaro.org> References: <20251009151607.26278-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760023075354116600 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/rx/translate.c | 64 +++++++++++++++++++++---------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/target/rx/translate.c b/target/rx/translate.c index 0d5356cd35d..ae9382e0756 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -161,19 +161,19 @@ static void gen_goto_tb(DisasContext *dc, int n, vadd= r dest) } =20 /* generic load wrapper */ -static inline void rx_gen_ld(MemOp size, TCGv reg, TCGv mem) +static inline void rx_gen_ld(DisasContext *ctx, MemOp size, TCGv reg, TCGv= mem) { tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE); } =20 /* unsigned load wrapper */ -static inline void rx_gen_ldu(MemOp size, TCGv reg, TCGv mem) +static inline void rx_gen_ldu(DisasContext *ctx, MemOp size, TCGv reg, TCG= v mem) { tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_TE); } =20 /* generic store wrapper */ -static inline void rx_gen_st(MemOp size, TCGv reg, TCGv mem) +static inline void rx_gen_st(DisasContext *ctx, MemOp size, TCGv reg, TCGv= mem) { tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE); } @@ -417,12 +417,12 @@ static void move_to_cr(DisasContext *ctx, TCGv val, i= nt cr) static void push(DisasContext *ctx, TCGv val) { tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); - rx_gen_st(MO_32, val, cpu_sp); + rx_gen_st(ctx, MO_32, val, cpu_sp); } =20 static void pop(DisasContext *ctx, TCGv ret) { - rx_gen_ld(MO_32, ret, cpu_sp); + rx_gen_ld(ctx, MO_32, ret, cpu_sp); tcg_gen_addi_i32(cpu_sp, cpu_sp, 4); } =20 @@ -432,7 +432,7 @@ static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm = *a) TCGv mem; mem =3D tcg_temp_new(); tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); - rx_gen_st(a->sz, cpu_regs[a->rs], mem); + rx_gen_st(ctx, a->sz, cpu_regs[a->rs], mem); return true; } =20 @@ -442,7 +442,7 @@ static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr = *a) TCGv mem; mem =3D tcg_temp_new(); tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); - rx_gen_ld(a->sz, cpu_regs[a->rd], mem); + rx_gen_ld(ctx, a->sz, cpu_regs[a->rd], mem); return true; } =20 @@ -463,7 +463,7 @@ static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im = *a) imm =3D tcg_constant_i32(a->imm); mem =3D tcg_temp_new(); tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); - rx_gen_st(a->sz, imm, mem); + rx_gen_st(ctx, a->sz, imm, mem); return true; } =20 @@ -473,7 +473,7 @@ static bool trans_MOV_ar(DisasContext *ctx, arg_MOV_ar = *a) TCGv mem; mem =3D tcg_temp_new(); rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); - rx_gen_ld(a->sz, cpu_regs[a->rd], mem); + rx_gen_ld(ctx, a->sz, cpu_regs[a->rd], mem); return true; } =20 @@ -483,7 +483,7 @@ static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra = *a) TCGv mem; mem =3D tcg_temp_new(); rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); - rx_gen_st(a->sz, cpu_regs[a->rs], mem); + rx_gen_st(ctx, a->sz, cpu_regs[a->rs], mem); return true; } =20 @@ -505,18 +505,18 @@ static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_m= m *a) if (a->lds =3D=3D 3) { /* mov. rs,dsp[rd] */ addr =3D rx_index_addr(ctx, mem, a->ldd, a->sz, a->rs); - rx_gen_st(a->sz, cpu_regs[a->rd], addr); + rx_gen_st(ctx, a->sz, cpu_regs[a->rd], addr); } else if (a->ldd =3D=3D 3) { /* mov. dsp[rs],rd */ addr =3D rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); - rx_gen_ld(a->sz, cpu_regs[a->rd], addr); + rx_gen_ld(ctx, a->sz, cpu_regs[a->rd], addr); } else { /* mov. dsp[rs],dsp[rd] */ tmp =3D tcg_temp_new(); addr =3D rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); - rx_gen_ld(a->sz, tmp, addr); + rx_gen_ld(ctx, a->sz, tmp, addr); addr =3D rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd); - rx_gen_st(a->sz, tmp, addr); + rx_gen_st(ctx, a->sz, tmp, addr); } return true; } @@ -531,7 +531,7 @@ static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp = *a) if (a->ad =3D=3D 1) { tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); } - rx_gen_st(a->sz, val, cpu_regs[a->rd]); + rx_gen_st(ctx, a->sz, val, cpu_regs[a->rd]); if (a->ad =3D=3D 0) { tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); } @@ -547,7 +547,7 @@ static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr = *a) if (a->ad =3D=3D 1) { tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); } - rx_gen_ld(a->sz, val, cpu_regs[a->rd]); + rx_gen_ld(ctx, a->sz, val, cpu_regs[a->rd]); if (a->ad =3D=3D 0) { tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); } @@ -562,7 +562,7 @@ static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_m= r *a) TCGv mem; mem =3D tcg_temp_new(); tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); - rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); + rx_gen_ldu(ctx, a->sz, cpu_regs[a->rd], mem); return true; } =20 @@ -579,7 +579,7 @@ static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_a= r *a) TCGv mem; mem =3D tcg_temp_new(); rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); - rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); + rx_gen_ldu(ctx, a->sz, cpu_regs[a->rd], mem); return true; } =20 @@ -592,7 +592,7 @@ static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_p= r *a) if (a->ad =3D=3D 1) { tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); } - rx_gen_ldu(a->sz, val, cpu_regs[a->rd]); + rx_gen_ldu(ctx, a->sz, val, cpu_regs[a->rd]); if (a->ad =3D=3D 0) { tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); } @@ -647,7 +647,7 @@ static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r = *a) val =3D tcg_temp_new(); tcg_gen_mov_i32(val, cpu_regs[a->rs]); tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); - rx_gen_st(a->sz, val, cpu_sp); + rx_gen_st(ctx, a->sz, val, cpu_sp); return true; } =20 @@ -658,9 +658,9 @@ static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m = *a) mem =3D tcg_temp_new(); val =3D tcg_temp_new(); addr =3D rx_index_addr(ctx, mem, a->ld, a->sz, a->rs); - rx_gen_ld(a->sz, val, addr); + rx_gen_ld(ctx, a->sz, val, addr); tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); - rx_gen_st(a->sz, val, cpu_sp); + rx_gen_st(ctx, a->sz, val, cpu_sp); return true; } =20 @@ -761,7 +761,7 @@ static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a) mem =3D tcg_temp_new(); tcg_gen_setcondi_i32(dc.cond, val, dc.value, 0); addr =3D rx_index_addr(ctx, mem, a->sz, a->ld, a->rd); - rx_gen_st(a->sz, val, addr); + rx_gen_st(ctx, a->sz, val, addr); } else { tcg_gen_setcondi_i32(dc.cond, cpu_regs[a->rd], dc.value, 0); } @@ -1898,25 +1898,25 @@ static void rx_bsetm(DisasContext *ctx, TCGv mem, T= CGv mask) { TCGv val; val =3D tcg_temp_new(); - rx_gen_ld(MO_8, val, mem); + rx_gen_ld(ctx, MO_8, val, mem); tcg_gen_or_i32(val, val, mask); - rx_gen_st(MO_8, val, mem); + rx_gen_st(ctx, MO_8, val, mem); } =20 static void rx_bclrm(DisasContext *ctx, TCGv mem, TCGv mask) { TCGv val; val =3D tcg_temp_new(); - rx_gen_ld(MO_8, val, mem); + rx_gen_ld(ctx, MO_8, val, mem); tcg_gen_andc_i32(val, val, mask); - rx_gen_st(MO_8, val, mem); + rx_gen_st(ctx, MO_8, val, mem); } =20 static void rx_btstm(DisasContext *ctx, TCGv mem, TCGv mask) { TCGv val; val =3D tcg_temp_new(); - rx_gen_ld(MO_8, val, mem); + rx_gen_ld(ctx, MO_8, val, mem); tcg_gen_and_i32(val, val, mask); tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, val, 0); tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); @@ -1926,9 +1926,9 @@ static void rx_bnotm(DisasContext *ctx, TCGv mem, TCG= v mask) { TCGv val; val =3D tcg_temp_new(); - rx_gen_ld(MO_8, val, mem); + rx_gen_ld(ctx, MO_8, val, mem); tcg_gen_xor_i32(val, val, mask); - rx_gen_st(MO_8, val, mem); + rx_gen_st(ctx, MO_8, val, mem); } =20 static void rx_bsetr(DisasContext *ctx, TCGv reg, TCGv mask) @@ -2023,9 +2023,9 @@ static bool trans_BMCnd_im(DisasContext *ctx, arg_BMC= nd_im *a) val =3D tcg_temp_new(); mem =3D tcg_temp_new(); addr =3D rx_index_addr(ctx, mem, a->ld, MO_8, a->rd); - rx_gen_ld(MO_8, val, addr); + rx_gen_ld(ctx, MO_8, val, addr); bmcnd_op(val, a->cd, a->imm); - rx_gen_st(MO_8, val, addr); + rx_gen_st(ctx, MO_8, val, addr); return true; } =20 --=20 2.51.0 From nobody Fri Nov 14 18:17:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 09 Oct 2025 08:16:39 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Yoshinori Sato , Anton Johansson , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 6/8] target/rx: Factor mo_endian() helper out Date: Thu, 9 Oct 2025 17:16:05 +0200 Message-ID: <20251009151607.26278-7-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251009151607.26278-1-philmd@linaro.org> References: <20251009151607.26278-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1760023131859154100 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/rx/translate.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/rx/translate.c b/target/rx/translate.c index ae9382e0756..01a065f937a 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -72,6 +72,11 @@ static TCGv_i64 cpu_acc; =20 #define cpu_sp cpu_regs[0] =20 +static inline MemOp mo_endian(DisasContext *dc) +{ + return MO_TE; +} + /* decoder helper */ static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn, int i, int n) @@ -163,19 +168,19 @@ static void gen_goto_tb(DisasContext *dc, int n, vadd= r dest) /* generic load wrapper */ static inline void rx_gen_ld(DisasContext *ctx, MemOp size, TCGv reg, TCGv= mem) { - tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE); + tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | mo_endian(ctx)); } =20 /* unsigned load wrapper */ static inline void rx_gen_ldu(DisasContext *ctx, MemOp size, TCGv reg, TCG= v mem) { - tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_TE); + tcg_gen_qemu_ld_i32(reg, mem, 0, size | mo_endian(ctx)); } =20 /* generic store wrapper */ static inline void rx_gen_st(DisasContext *ctx, MemOp size, TCGv reg, TCGv= mem) { - tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE); + tcg_gen_qemu_st_i32(reg, mem, 0, size | mo_endian(ctx)); } =20 /* [ri, rb] */ @@ -226,7 +231,7 @@ static inline TCGv rx_load_source(DisasContext *ctx, TC= Gv mem, if (ld < 3) { mop =3D mi_to_mop(mi); addr =3D rx_index_addr(ctx, mem, ld, mop & MO_SIZE, rs); - tcg_gen_qemu_ld_i32(mem, addr, 0, mop | MO_TE); + tcg_gen_qemu_ld_i32(mem, addr, 0, mop | mo_endian(ctx)); return mem; } else { return cpu_regs[rs]; --=20 2.51.0 From nobody Fri Nov 14 18:17:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760023064; cv=none; d=zohomail.com; s=zohoarc; b=ITWxX1sEDYJQq9jfc5VVBKeL+mF9qpZI3l0RZf5W/Hwr+D/NVtTJKfs2fSodO51SlGLis/Ft2L8xQWfmPj9I6QcD1wnyR54AJdw7tIJVJ5vJPuBssrCmklVJ3DyGhgnzpBwwtheSI2713u7Ujeh3P5tXRT2ONKTDwC03ESWodkE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760023064; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Use the latter to simplify. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/rx/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/rx/translate.c b/target/rx/translate.c index 01a065f937a..c83e7afc60f 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -74,7 +74,7 @@ static TCGv_i64 cpu_acc; =20 static inline MemOp mo_endian(DisasContext *dc) { - return MO_TE; + return MO_LE; } =20 /* decoder helper */ --=20 2.51.0 From nobody Fri Nov 14 18:17:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1760023126; cv=none; d=zohomail.com; s=zohoarc; b=Os9pDjWKrfePJYGL6AaBObgzEJNKaXEPDsGOjKA7VbClGVYr86cchm70qMPShF9lRyTu05/hJ27ikf/ps8kaonGFnJTzkk2XtwKyhhjdpTdpo18IaVWTyCaArpWf1wyW9Q504/szizn5z1/C6lkC7BmrgGCI5Y6T460kjBt3Rxw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760023126; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bQJ+OrHYqVgBYhVx+LrRn1tYdILCbq/u6DwNuowQaY4=; b=g+gbB8G34aizvA+c8uxwIzSGVZIHLHyGo85jyy535wg5Ckeo9fMK/a1w4edSJlC1GTmBjS7yEom+pg6X0ouYtIYRgMSFbJ/AgvvAMwACf5hsGmJiszT89VDy3Y4V8yjDiHjVzpp0+SBlK8s3UCZ5mp+7zHINdmebatsx0cPx6j8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1760023126007407.15155388791595; Thu, 9 Oct 2025 08:18:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v6sO7-0001EY-8e; Thu, 09 Oct 2025 11:17:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v6sO3-0001DI-EV for qemu-devel@nongnu.org; Thu, 09 Oct 2025 11:17:01 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1v6sNv-00015i-MZ for qemu-devel@nongnu.org; Thu, 09 Oct 2025 11:16:57 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-46e29d65728so6723305e9.3 for ; Thu, 09 Oct 2025 08:16:51 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/rx/translate.c | 322 +++++++++++++++++++++--------------------- 1 file changed, 161 insertions(+), 161 deletions(-) diff --git a/target/rx/translate.c b/target/rx/translate.c index c83e7afc60f..ada2d99f7c3 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -40,8 +40,8 @@ typedef struct DisasContext { } DisasContext; =20 typedef struct DisasCompare { - TCGv value; - TCGv temp; + TCGv_i32 value; + TCGv_i32 temp; TCGCond cond; } DisasCompare; =20 @@ -63,11 +63,11 @@ const char *rx_crname(uint8_t cr) #define DISAS_EXIT DISAS_TARGET_2 =20 /* global register indexes */ -static TCGv cpu_regs[16]; -static TCGv cpu_psw_o, cpu_psw_s, cpu_psw_z, cpu_psw_c; -static TCGv cpu_psw_i, cpu_psw_pm, cpu_psw_u, cpu_psw_ipl; -static TCGv cpu_usp, cpu_fpsw, cpu_bpsw, cpu_bpc, cpu_isp; -static TCGv cpu_fintv, cpu_intb, cpu_pc; +static TCGv_i32 cpu_regs[16]; +static TCGv_i32 cpu_psw_o, cpu_psw_s, cpu_psw_z, cpu_psw_c; +static TCGv_i32 cpu_psw_i, cpu_psw_pm, cpu_psw_u, cpu_psw_ipl; +static TCGv_i32 cpu_usp, cpu_fpsw, cpu_bpsw, cpu_bpc, cpu_isp; +static TCGv_i32 cpu_fintv, cpu_intb, cpu_pc; static TCGv_i64 cpu_acc; =20 #define cpu_sp cpu_regs[0] @@ -166,25 +166,25 @@ static void gen_goto_tb(DisasContext *dc, int n, vadd= r dest) } =20 /* generic load wrapper */ -static inline void rx_gen_ld(DisasContext *ctx, MemOp size, TCGv reg, TCGv= mem) +static inline void rx_gen_ld(DisasContext *ctx, MemOp size, TCGv_i32 reg, = TCGv_i32 mem) { tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | mo_endian(ctx)); } =20 /* unsigned load wrapper */ -static inline void rx_gen_ldu(DisasContext *ctx, MemOp size, TCGv reg, TCG= v mem) +static inline void rx_gen_ldu(DisasContext *ctx, MemOp size, TCGv_i32 reg,= TCGv_i32 mem) { tcg_gen_qemu_ld_i32(reg, mem, 0, size | mo_endian(ctx)); } =20 /* generic store wrapper */ -static inline void rx_gen_st(DisasContext *ctx, MemOp size, TCGv reg, TCGv= mem) +static inline void rx_gen_st(DisasContext *ctx, MemOp size, TCGv_i32 reg, = TCGv_i32 mem) { tcg_gen_qemu_st_i32(reg, mem, 0, size | mo_endian(ctx)); } =20 /* [ri, rb] */ -static inline void rx_gen_regindex(DisasContext *ctx, TCGv mem, +static inline void rx_gen_regindex(DisasContext *ctx, TCGv_i32 mem, int size, int ri, int rb) { tcg_gen_shli_i32(mem, cpu_regs[ri], size); @@ -192,7 +192,7 @@ static inline void rx_gen_regindex(DisasContext *ctx, T= CGv mem, } =20 /* dsp[reg] */ -static inline TCGv rx_index_addr(DisasContext *ctx, TCGv mem, +static inline TCGv_i32 rx_index_addr(DisasContext *ctx, TCGv_i32 mem, int ld, int size, int reg) { uint32_t dsp; @@ -223,10 +223,10 @@ static inline MemOp mi_to_mop(unsigned mi) } =20 /* load source operand */ -static inline TCGv rx_load_source(DisasContext *ctx, TCGv mem, +static inline TCGv_i32 rx_load_source(DisasContext *ctx, TCGv_i32 mem, int ld, int mi, int rs) { - TCGv addr; + TCGv_i32 addr; MemOp mop; if (ld < 3) { mop =3D mi_to_mop(mi); @@ -320,7 +320,7 @@ static void psw_cond(DisasCompare *dc, uint32_t cond) } } =20 -static void move_from_cr(DisasContext *ctx, TCGv ret, int cr, uint32_t pc) +static void move_from_cr(DisasContext *ctx, TCGv_i32 ret, int cr, uint32_t= pc) { switch (cr) { case 0: /* PSW */ @@ -366,7 +366,7 @@ static void move_from_cr(DisasContext *ctx, TCGv ret, i= nt cr, uint32_t pc) } } =20 -static void move_to_cr(DisasContext *ctx, TCGv val, int cr) +static void move_to_cr(DisasContext *ctx, TCGv_i32 val, int cr) { if (cr >=3D 8 && !is_privileged(ctx, 0)) { /* Some control registers can only be written in privileged mode. = */ @@ -419,13 +419,13 @@ static void move_to_cr(DisasContext *ctx, TCGv val, i= nt cr) } } =20 -static void push(DisasContext *ctx, TCGv val) +static void push(DisasContext *ctx, TCGv_i32 val) { tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); rx_gen_st(ctx, MO_32, val, cpu_sp); } =20 -static void pop(DisasContext *ctx, TCGv ret) +static void pop(DisasContext *ctx, TCGv_i32 ret) { rx_gen_ld(ctx, MO_32, ret, cpu_sp); tcg_gen_addi_i32(cpu_sp, cpu_sp, 4); @@ -434,8 +434,8 @@ static void pop(DisasContext *ctx, TCGv ret) /* mov. rs,dsp5[rd] */ static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a) { - TCGv mem; - mem =3D tcg_temp_new(); + TCGv_i32 mem; + mem =3D tcg_temp_new_i32(); tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); rx_gen_st(ctx, a->sz, cpu_regs[a->rs], mem); return true; @@ -444,8 +444,8 @@ static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm = *a) /* mov. dsp5[rs],rd */ static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a) { - TCGv mem; - mem =3D tcg_temp_new(); + TCGv_i32 mem; + mem =3D tcg_temp_new_i32(); tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); rx_gen_ld(ctx, a->sz, cpu_regs[a->rd], mem); return true; @@ -464,9 +464,9 @@ static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir = *a) /* mov. #imm, dsp[rd] */ static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a) { - TCGv imm, mem; + TCGv_i32 imm, mem; imm =3D tcg_constant_i32(a->imm); - mem =3D tcg_temp_new(); + mem =3D tcg_temp_new_i32(); tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); rx_gen_st(ctx, a->sz, imm, mem); return true; @@ -475,8 +475,8 @@ static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im = *a) /* mov. [ri,rb],rd */ static bool trans_MOV_ar(DisasContext *ctx, arg_MOV_ar *a) { - TCGv mem; - mem =3D tcg_temp_new(); + TCGv_i32 mem; + mem =3D tcg_temp_new_i32(); rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); rx_gen_ld(ctx, a->sz, cpu_regs[a->rd], mem); return true; @@ -485,8 +485,8 @@ static bool trans_MOV_ar(DisasContext *ctx, arg_MOV_ar = *a) /* mov. rd,[ri,rb] */ static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a) { - TCGv mem; - mem =3D tcg_temp_new(); + TCGv_i32 mem; + mem =3D tcg_temp_new_i32(); rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); rx_gen_st(ctx, a->sz, cpu_regs[a->rs], mem); return true; @@ -498,7 +498,7 @@ static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra = *a) /* mov. rs,rd */ static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a) { - TCGv tmp, mem, addr; + TCGv_i32 tmp, mem, addr; =20 if (a->lds =3D=3D 3 && a->ldd =3D=3D 3) { /* mov. rs,rd */ @@ -506,7 +506,7 @@ static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm = *a) return true; } =20 - mem =3D tcg_temp_new(); + mem =3D tcg_temp_new_i32(); if (a->lds =3D=3D 3) { /* mov. rs,dsp[rd] */ addr =3D rx_index_addr(ctx, mem, a->ldd, a->sz, a->rs); @@ -517,7 +517,7 @@ static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm = *a) rx_gen_ld(ctx, a->sz, cpu_regs[a->rd], addr); } else { /* mov. dsp[rs],dsp[rd] */ - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i32(); addr =3D rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); rx_gen_ld(ctx, a->sz, tmp, addr); addr =3D rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd); @@ -530,8 +530,8 @@ static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm = *a) /* mov. rs,[-rd] */ static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a) { - TCGv val; - val =3D tcg_temp_new(); + TCGv_i32 val; + val =3D tcg_temp_new_i32(); tcg_gen_mov_i32(val, cpu_regs[a->rs]); if (a->ad =3D=3D 1) { tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); @@ -547,8 +547,8 @@ static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp = *a) /* mov. [-rd],rs */ static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a) { - TCGv val; - val =3D tcg_temp_new(); + TCGv_i32 val; + val =3D tcg_temp_new_i32(); if (a->ad =3D=3D 1) { tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); } @@ -564,8 +564,8 @@ static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr = *a) /* movu. dsp[rs],rd */ static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_mr *a) { - TCGv mem; - mem =3D tcg_temp_new(); + TCGv_i32 mem; + mem =3D tcg_temp_new_i32(); tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); rx_gen_ldu(ctx, a->sz, cpu_regs[a->rd], mem); return true; @@ -581,8 +581,8 @@ static bool trans_MOVU_rr(DisasContext *ctx, arg_MOVU_r= r *a) /* movu. [ri,rb],rd */ static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_ar *a) { - TCGv mem; - mem =3D tcg_temp_new(); + TCGv_i32 mem; + mem =3D tcg_temp_new_i32(); rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); rx_gen_ldu(ctx, a->sz, cpu_regs[a->rd], mem); return true; @@ -592,8 +592,8 @@ static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_a= r *a) /* mov. [-rd],rs */ static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_pr *a) { - TCGv val; - val =3D tcg_temp_new(); + TCGv_i32 val; + val =3D tcg_temp_new_i32(); if (a->ad =3D=3D 1) { tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); } @@ -622,8 +622,8 @@ static bool trans_POP(DisasContext *ctx, arg_POP *a) /* popc cr */ static bool trans_POPC(DisasContext *ctx, arg_POPC *a) { - TCGv val; - val =3D tcg_temp_new(); + TCGv_i32 val; + val =3D tcg_temp_new_i32(); pop(ctx, val); move_to_cr(ctx, val, a->cr); return true; @@ -648,8 +648,8 @@ static bool trans_POPM(DisasContext *ctx, arg_POPM *a) /* push. rs */ static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a) { - TCGv val; - val =3D tcg_temp_new(); + TCGv_i32 val; + val =3D tcg_temp_new_i32(); tcg_gen_mov_i32(val, cpu_regs[a->rs]); tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); rx_gen_st(ctx, a->sz, val, cpu_sp); @@ -659,9 +659,9 @@ static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r = *a) /* push. dsp[rs] */ static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m *a) { - TCGv mem, val, addr; - mem =3D tcg_temp_new(); - val =3D tcg_temp_new(); + TCGv_i32 mem, val, addr; + mem =3D tcg_temp_new_i32(); + val =3D tcg_temp_new_i32(); addr =3D rx_index_addr(ctx, mem, a->ld, a->sz, a->rs); rx_gen_ld(ctx, a->sz, val, addr); tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); @@ -672,8 +672,8 @@ static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m = *a) /* pushc rx */ static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a) { - TCGv val; - val =3D tcg_temp_new(); + TCGv_i32 val; + val =3D tcg_temp_new_i32(); move_from_cr(ctx, val, a->cr, ctx->pc); push(ctx, val); return true; @@ -698,8 +698,8 @@ static bool trans_PUSHM(DisasContext *ctx, arg_PUSHM *a) /* xchg rs,rd */ static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_rr *a) { - TCGv tmp; - tmp =3D tcg_temp_new(); + TCGv_i32 tmp; + tmp =3D tcg_temp_new_i32(); tcg_gen_mov_i32(tmp, cpu_regs[a->rs]); tcg_gen_mov_i32(cpu_regs[a->rs], cpu_regs[a->rd]); tcg_gen_mov_i32(cpu_regs[a->rd], tmp); @@ -709,8 +709,8 @@ static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_r= r *a) /* xchg dsp[rs].,rd */ static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a) { - TCGv mem, addr; - mem =3D tcg_temp_new(); + TCGv_i32 mem, addr; + mem =3D tcg_temp_new_i32(); switch (a->mi) { case 0: /* dsp[rs].b */ case 1: /* dsp[rs].w */ @@ -731,8 +731,8 @@ static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_m= r *a) =20 static inline void stcond(TCGCond cond, int rd, int imm) { - TCGv z; - TCGv _imm; + TCGv_i32 z; + TCGv_i32 _imm; z =3D tcg_constant_i32(0); _imm =3D tcg_constant_i32(imm); tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z, @@ -758,12 +758,12 @@ static bool trans_STNZ(DisasContext *ctx, arg_STNZ *a) static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a) { DisasCompare dc; - TCGv val, mem, addr; - dc.temp =3D tcg_temp_new(); + TCGv_i32 val, mem, addr; + dc.temp =3D tcg_temp_new_i32(); psw_cond(&dc, a->cd); if (a->ld < 3) { - val =3D tcg_temp_new(); - mem =3D tcg_temp_new(); + val =3D tcg_temp_new_i32(); + mem =3D tcg_temp_new_i32(); tcg_gen_setcondi_i32(dc.cond, val, dc.value, 0); addr =3D rx_index_addr(ctx, mem, a->sz, a->ld, a->rd); rx_gen_st(ctx, a->sz, val, addr); @@ -804,8 +804,8 @@ static bool trans_RTSD_irr(DisasContext *ctx, arg_RTSD_= irr *a) return true; } =20 -typedef void (*op2fn)(TCGv ret, TCGv arg1); -typedef void (*op3fn)(TCGv ret, TCGv arg1, TCGv arg2); +typedef void (*op2fn)(TCGv_i32 ret, TCGv_i32 arg1); +typedef void (*op3fn)(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); =20 static inline void rx_gen_op_rr(op2fn opr, int dst, int src) { @@ -819,20 +819,20 @@ static inline void rx_gen_op_rrr(op3fn opr, int dst, = int src, int src2) =20 static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src= 2) { - TCGv imm =3D tcg_constant_i32(src2); + TCGv_i32 imm =3D tcg_constant_i32(src2); opr(cpu_regs[dst], cpu_regs[src], imm); } =20 static inline void rx_gen_op_mr(op3fn opr, DisasContext *ctx, int dst, int src, int ld, int mi) { - TCGv val, mem; - mem =3D tcg_temp_new(); + TCGv_i32 val, mem; + mem =3D tcg_temp_new_i32(); val =3D rx_load_source(ctx, mem, ld, mi, src); opr(cpu_regs[dst], cpu_regs[dst], val); } =20 -static void rx_and(TCGv ret, TCGv arg1, TCGv arg2) +static void rx_and(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_and_i32(cpu_psw_s, arg1, arg2); tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); @@ -862,7 +862,7 @@ static bool trans_AND_rrr(DisasContext *ctx, arg_AND_rr= r *a) return true; } =20 -static void rx_or(TCGv ret, TCGv arg1, TCGv arg2) +static void rx_or(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_or_i32(cpu_psw_s, arg1, arg2); tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); @@ -892,7 +892,7 @@ static bool trans_OR_rrr(DisasContext *ctx, arg_OR_rrr = *a) return true; } =20 -static void rx_xor(TCGv ret, TCGv arg1, TCGv arg2) +static void rx_xor(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_xor_i32(cpu_psw_s, arg1, arg2); tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); @@ -914,7 +914,7 @@ static bool trans_XOR_mr(DisasContext *ctx, arg_XOR_mr = *a) return true; } =20 -static void rx_tst(TCGv ret, TCGv arg1, TCGv arg2) +static void rx_tst(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_and_i32(cpu_psw_s, arg1, arg2); tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); @@ -935,7 +935,7 @@ static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr = *a) return true; } =20 -static void rx_not(TCGv ret, TCGv arg1) +static void rx_not(TCGv_i32 ret, TCGv_i32 arg1) { tcg_gen_not_i32(ret, arg1); tcg_gen_mov_i32(cpu_psw_z, ret); @@ -950,7 +950,7 @@ static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr = *a) return true; } =20 -static void rx_neg(TCGv ret, TCGv arg1) +static void rx_neg(TCGv_i32 ret, TCGv_i32 arg1) { tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, arg1, 0x80000000); tcg_gen_neg_i32(ret, arg1); @@ -969,9 +969,9 @@ static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr = *a) } =20 /* ret =3D arg1 + arg2 + psw_c */ -static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2) +static void rx_adc(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { - TCGv z =3D tcg_constant_i32(0); + TCGv_i32 z =3D tcg_constant_i32(0); tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z); tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z); tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); @@ -1007,9 +1007,9 @@ static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_m= r *a) } =20 /* ret =3D arg1 + arg2 */ -static void rx_add(TCGv ret, TCGv arg1, TCGv arg2) +static void rx_add(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { - TCGv z =3D tcg_constant_i32(0); + TCGv_i32 z =3D tcg_constant_i32(0); tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z); tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); @@ -1042,7 +1042,7 @@ static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_= rrr *a) } =20 /* ret =3D arg1 - arg2 */ -static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2) +static void rx_sub(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { tcg_gen_sub_i32(cpu_psw_s, arg1, arg2); tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2); @@ -1056,17 +1056,17 @@ static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2) } } =20 -static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2) +static void rx_cmp(TCGv_i32 dummy, TCGv_i32 arg1, TCGv_i32 arg2) { rx_sub(NULL, arg1, arg2); } =20 /* ret =3D arg1 - arg2 - !psw_c */ /* -> ret =3D arg1 + ~arg2 + psw_c */ -static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2) +static void rx_sbb(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { - TCGv temp; - temp =3D tcg_temp_new(); + TCGv_i32 temp; + temp =3D tcg_temp_new_i32(); tcg_gen_not_i32(temp, arg2); rx_adc(ret, arg1, temp); } @@ -1192,7 +1192,7 @@ static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_= rrr *a) /* emul #imm, rd */ static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a) { - TCGv imm =3D tcg_constant_i32(a->imm); + TCGv_i32 imm =3D tcg_constant_i32(a->imm); if (a->rd > 14) { qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); } @@ -1205,11 +1205,11 @@ static bool trans_EMUL_ir(DisasContext *ctx, arg_EM= UL_ir *a) /* emul dsp[rs], rd */ static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a) { - TCGv val, mem; + TCGv_i32 val, mem; if (a->rd > 14) { qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); } - mem =3D tcg_temp_new(); + mem =3D tcg_temp_new_i32(); val =3D rx_load_source(ctx, mem, a->ld, a->mi, a->rs); tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], cpu_regs[a->rd], val); @@ -1219,7 +1219,7 @@ static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL= _mr *a) /* emulu #imm, rd */ static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a) { - TCGv imm =3D tcg_constant_i32(a->imm); + TCGv_i32 imm =3D tcg_constant_i32(a->imm); if (a->rd > 14) { qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); } @@ -1232,23 +1232,23 @@ static bool trans_EMULU_ir(DisasContext *ctx, arg_E= MULU_ir *a) /* emulu dsp[rs], rd */ static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a) { - TCGv val, mem; + TCGv_i32 val, mem; if (a->rd > 14) { qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); } - mem =3D tcg_temp_new(); + mem =3D tcg_temp_new_i32(); val =3D rx_load_source(ctx, mem, a->ld, a->mi, a->rs); tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], cpu_regs[a->rd], val); return true; } =20 -static void rx_div(TCGv ret, TCGv arg1, TCGv arg2) +static void rx_div(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { gen_helper_div(ret, tcg_env, arg1, arg2); } =20 -static void rx_divu(TCGv ret, TCGv arg1, TCGv arg2) +static void rx_divu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { gen_helper_divu(ret, tcg_env, arg1, arg2); } @@ -1288,8 +1288,8 @@ static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU= _mr *a) /* shll #imm:5, rs2, rd */ static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a) { - TCGv tmp; - tmp =3D tcg_temp_new(); + TCGv_i32 tmp; + tmp =3D tcg_temp_new_i32(); if (a->imm) { tcg_gen_sari_i32(cpu_psw_c, cpu_regs[a->rs2], 32 - a->imm); tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rs2], a->imm); @@ -1311,14 +1311,14 @@ static bool trans_SHLL_irr(DisasContext *ctx, arg_S= HLL_irr *a) static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a) { TCGLabel *noshift, *done; - TCGv count, tmp; + TCGv_i32 count, tmp; =20 noshift =3D gen_new_label(); done =3D gen_new_label(); /* if (cpu_regs[a->rs]) { */ tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift); - count =3D tcg_temp_new(); - tmp =3D tcg_temp_new(); + count =3D tcg_temp_new_i32(); + tmp =3D tcg_temp_new_i32(); tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31); tcg_gen_sub_i32(count, tcg_constant_i32(32), tmp); tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count); @@ -1342,7 +1342,7 @@ static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL= _rr *a) static inline void shiftr_imm(uint32_t rd, uint32_t rs, uint32_t imm, unsigned int alith) { - static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) =3D { + static void (* const gen_sXri[])(TCGv_i32 ret, TCGv_i32 arg1, int arg2= ) =3D { tcg_gen_shri_i32, tcg_gen_sari_i32, }; tcg_debug_assert(alith < 2); @@ -1362,17 +1362,17 @@ static inline void shiftr_imm(uint32_t rd, uint32_t= rs, uint32_t imm, static inline void shiftr_reg(uint32_t rd, uint32_t rs, unsigned int alith) { TCGLabel *noshift, *done; - TCGv count; - static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) =3D { + TCGv_i32 count; + static void (* const gen_sXri[])(TCGv_i32 ret, TCGv_i32 arg1, int arg2= ) =3D { tcg_gen_shri_i32, tcg_gen_sari_i32, }; - static void (* const gen_sXr[])(TCGv ret, TCGv arg1, TCGv arg2) =3D { + static void (* const gen_sXr[])(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 = arg2) =3D { tcg_gen_shr_i32, tcg_gen_sar_i32, }; tcg_debug_assert(alith < 2); noshift =3D gen_new_label(); done =3D gen_new_label(); - count =3D tcg_temp_new(); + count =3D tcg_temp_new_i32(); /* if (cpu_regs[rs]) { */ tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[rs], 0, noshift); tcg_gen_andi_i32(count, cpu_regs[rs], 31); @@ -1424,8 +1424,8 @@ static bool trans_SHLR_rr(DisasContext *ctx, arg_SHLR= _rr *a) /* rolc rd */ static bool trans_ROLC(DisasContext *ctx, arg_ROLC *a) { - TCGv tmp; - tmp =3D tcg_temp_new(); + TCGv_i32 tmp; + tmp =3D tcg_temp_new_i32(); tcg_gen_shri_i32(tmp, cpu_regs[a->rd], 31); tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); @@ -1438,8 +1438,8 @@ static bool trans_ROLC(DisasContext *ctx, arg_ROLC *a) /* rorc rd */ static bool trans_RORC(DisasContext *ctx, arg_RORC *a) { - TCGv tmp; - tmp =3D tcg_temp_new(); + TCGv_i32 tmp; + tmp =3D tcg_temp_new_i32(); tcg_gen_andi_i32(tmp, cpu_regs[a->rd], 0x00000001); tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); tcg_gen_shli_i32(cpu_psw_c, cpu_psw_c, 31); @@ -1514,8 +1514,8 @@ static bool trans_REVL(DisasContext *ctx, arg_REVL *a) /* revw rs, rd */ static bool trans_REVW(DisasContext *ctx, arg_REVW *a) { - TCGv tmp; - tmp =3D tcg_temp_new(); + TCGv_i32 tmp; + tmp =3D tcg_temp_new_i32(); tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 0x00ff00ff); tcg_gen_shli_i32(tmp, tmp, 8); tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rs], 8); @@ -1532,7 +1532,7 @@ static void rx_bcnd_main(DisasContext *ctx, int cd, i= nt dst) =20 switch (cd) { case 0 ... 13: - dc.temp =3D tcg_temp_new(); + dc.temp =3D tcg_temp_new_i32(); psw_cond(&dc, cd); t =3D gen_new_label(); done =3D gen_new_label(); @@ -1589,7 +1589,7 @@ static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l = *a) =20 static inline void rx_save_pc(DisasContext *ctx) { - TCGv pc =3D tcg_constant_i32(ctx->base.pc_next); + TCGv_i32 pc =3D tcg_constant_i32(ctx->base.pc_next); push(ctx, pc); } =20 @@ -1672,7 +1672,7 @@ static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB = *a) =20 #define STRING(op) \ do { \ - TCGv size =3D tcg_constant_i32(a->sz); \ + TCGv_i32 size =3D tcg_constant_i32(a->sz); \ gen_helper_##op(tcg_env, size); \ } while (0) =20 @@ -1803,7 +1803,7 @@ static bool trans_MVTACLO(DisasContext *ctx, arg_MVTA= CLO *a) /* racw #imm */ static bool trans_RACW(DisasContext *ctx, arg_RACW *a) { - TCGv imm =3D tcg_constant_i32(a->imm + 1); + TCGv_i32 imm =3D tcg_constant_i32(a->imm + 1); gen_helper_racw(tcg_env, imm); return true; } @@ -1811,8 +1811,8 @@ static bool trans_RACW(DisasContext *ctx, arg_RACW *a) /* sat rd */ static bool trans_SAT(DisasContext *ctx, arg_SAT *a) { - TCGv tmp, z; - tmp =3D tcg_temp_new(); + TCGv_i32 tmp, z; + tmp =3D tcg_temp_new_i32(); z =3D tcg_constant_i32(0); /* S =3D=3D 1 -> 0xffffffff / S =3D=3D 0 -> 0x00000000 */ tcg_gen_sari_i32(tmp, cpu_psw_s, 31); @@ -1835,7 +1835,7 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a) static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ cat3(arg_, name, _ir) * a) \ { \ - TCGv imm =3D tcg_constant_i32(li(ctx, 0)); \ + TCGv_i32 imm =3D tcg_constant_i32(li(ctx, 0)); = \ gen_helper_##op(cpu_regs[a->rd], tcg_env, \ cpu_regs[a->rd], imm); \ return true; \ @@ -1843,8 +1843,8 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a) static bool cat3(trans_, name, _mr)(DisasContext *ctx, \ cat3(arg_, name, _mr) * a) \ { \ - TCGv val, mem; \ - mem =3D tcg_temp_new(); \ + TCGv_i32 val, mem; = \ + mem =3D tcg_temp_new_i32(); = \ val =3D rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ gen_helper_##op(cpu_regs[a->rd], tcg_env, \ cpu_regs[a->rd], val); \ @@ -1854,8 +1854,8 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a) #define FCONVOP(name, op) \ static bool trans_##name(DisasContext *ctx, arg_##name * a) \ { \ - TCGv val, mem; \ - mem =3D tcg_temp_new(); \ + TCGv_i32 val, mem; \ + mem =3D tcg_temp_new_i32(); \ val =3D rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ gen_helper_##op(cpu_regs[a->rd], tcg_env, val); \ return true; \ @@ -1869,7 +1869,7 @@ FOP(FDIV, fdiv) /* fcmp #imm, rd */ static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a) { - TCGv imm =3D tcg_constant_i32(li(ctx, 0)); + TCGv_i32 imm =3D tcg_constant_i32(li(ctx, 0)); gen_helper_fcmp(tcg_env, cpu_regs[a->rd], imm); return true; } @@ -1878,8 +1878,8 @@ static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP= _ir * a) /* fcmp rs, rd */ static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a) { - TCGv val, mem; - mem =3D tcg_temp_new(); + TCGv_i32 val, mem; + mem =3D tcg_temp_new_i32(); val =3D rx_load_source(ctx, mem, a->ld, MO_32, a->rs); gen_helper_fcmp(tcg_env, cpu_regs[a->rd], val); return true; @@ -1892,70 +1892,70 @@ FCONVOP(ROUND, round) /* itof dsp[rs], rd */ static bool trans_ITOF(DisasContext *ctx, arg_ITOF * a) { - TCGv val, mem; - mem =3D tcg_temp_new(); + TCGv_i32 val, mem; + mem =3D tcg_temp_new_i32(); val =3D rx_load_source(ctx, mem, a->ld, a->mi, a->rs); gen_helper_itof(cpu_regs[a->rd], tcg_env, val); return true; } =20 -static void rx_bsetm(DisasContext *ctx, TCGv mem, TCGv mask) +static void rx_bsetm(DisasContext *ctx, TCGv_i32 mem, TCGv_i32 mask) { - TCGv val; - val =3D tcg_temp_new(); + TCGv_i32 val; + val =3D tcg_temp_new_i32(); rx_gen_ld(ctx, MO_8, val, mem); tcg_gen_or_i32(val, val, mask); rx_gen_st(ctx, MO_8, val, mem); } =20 -static void rx_bclrm(DisasContext *ctx, TCGv mem, TCGv mask) +static void rx_bclrm(DisasContext *ctx, TCGv_i32 mem, TCGv_i32 mask) { - TCGv val; - val =3D tcg_temp_new(); + TCGv_i32 val; + val =3D tcg_temp_new_i32(); rx_gen_ld(ctx, MO_8, val, mem); tcg_gen_andc_i32(val, val, mask); rx_gen_st(ctx, MO_8, val, mem); } =20 -static void rx_btstm(DisasContext *ctx, TCGv mem, TCGv mask) +static void rx_btstm(DisasContext *ctx, TCGv_i32 mem, TCGv_i32 mask) { - TCGv val; - val =3D tcg_temp_new(); + TCGv_i32 val; + val =3D tcg_temp_new_i32(); rx_gen_ld(ctx, MO_8, val, mem); tcg_gen_and_i32(val, val, mask); tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, val, 0); tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); } =20 -static void rx_bnotm(DisasContext *ctx, TCGv mem, TCGv mask) +static void rx_bnotm(DisasContext *ctx, TCGv_i32 mem, TCGv_i32 mask) { - TCGv val; - val =3D tcg_temp_new(); + TCGv_i32 val; + val =3D tcg_temp_new_i32(); rx_gen_ld(ctx, MO_8, val, mem); tcg_gen_xor_i32(val, val, mask); rx_gen_st(ctx, MO_8, val, mem); } =20 -static void rx_bsetr(DisasContext *ctx, TCGv reg, TCGv mask) +static void rx_bsetr(DisasContext *ctx, TCGv_i32 reg, TCGv_i32 mask) { tcg_gen_or_i32(reg, reg, mask); } =20 -static void rx_bclrr(DisasContext *ctx, TCGv reg, TCGv mask) +static void rx_bclrr(DisasContext *ctx, TCGv_i32 reg, TCGv_i32 mask) { tcg_gen_andc_i32(reg, reg, mask); } =20 -static inline void rx_btstr(DisasContext *ctx, TCGv reg, TCGv mask) +static inline void rx_btstr(DisasContext *ctx, TCGv_i32 reg, TCGv_i32 mask) { - TCGv t0; - t0 =3D tcg_temp_new(); + TCGv_i32 t0; + t0 =3D tcg_temp_new_i32(); tcg_gen_and_i32(t0, reg, mask); tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, t0, 0); tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); } =20 -static inline void rx_bnotr(DisasContext *ctx, TCGv reg, TCGv mask) +static inline void rx_bnotr(DisasContext *ctx, TCGv_i32 reg, TCGv_i32 mask) { tcg_gen_xor_i32(reg, reg, mask); } @@ -1964,8 +1964,8 @@ static inline void rx_bnotr(DisasContext *ctx, TCGv r= eg, TCGv mask) static bool cat3(trans_, name, _im)(DisasContext *ctx, \ cat3(arg_, name, _im) * a) \ { \ - TCGv mask, mem, addr; \ - mem =3D tcg_temp_new(); \ + TCGv_i32 mask, mem, addr; = \ + mem =3D tcg_temp_new_i32(); = \ mask =3D tcg_constant_i32(1 << a->imm); \ addr =3D rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ cat3(rx_, op, m)(ctx, addr, mask); \ @@ -1974,7 +1974,7 @@ static inline void rx_bnotr(DisasContext *ctx, TCGv r= eg, TCGv mask) static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ cat3(arg_, name, _ir) * a) \ { \ - TCGv mask; \ + TCGv_i32 mask; = \ mask =3D tcg_constant_i32(1 << a->imm); \ cat3(rx_, op, r)(ctx, cpu_regs[a->rd], mask); \ return true; \ @@ -1982,9 +1982,9 @@ static inline void rx_bnotr(DisasContext *ctx, TCGv r= eg, TCGv mask) static bool cat3(trans_, name, _rr)(DisasContext *ctx, \ cat3(arg_, name, _rr) * a) \ { \ - TCGv mask, b; \ - mask =3D tcg_temp_new(); \ - b =3D tcg_temp_new(); \ + TCGv_i32 mask, b; = \ + mask =3D tcg_temp_new_i32(); = \ + b =3D tcg_temp_new_i32(); = \ tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \ tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \ cat3(rx_, op, r)(ctx, cpu_regs[a->rd], mask); \ @@ -1993,12 +1993,12 @@ static inline void rx_bnotr(DisasContext *ctx, TCGv= reg, TCGv mask) static bool cat3(trans_, name, _rm)(DisasContext *ctx, \ cat3(arg_, name, _rm) * a) \ { \ - TCGv mask, mem, addr, b; \ - mask =3D tcg_temp_new(); \ - b =3D tcg_temp_new(); \ + TCGv_i32 mask, mem, addr, b; = \ + mask =3D tcg_temp_new_i32(); = \ + b =3D tcg_temp_new_i32(); = \ tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \ tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \ - mem =3D tcg_temp_new(); \ + mem =3D tcg_temp_new_i32(); = \ addr =3D rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ cat3(rx_, op, m)(ctx, addr, mask); \ return true; \ @@ -2009,12 +2009,12 @@ BITOP(BCLR, bclr) BITOP(BTST, btst) BITOP(BNOT, bnot) =20 -static inline void bmcnd_op(TCGv val, TCGCond cond, int pos) +static inline void bmcnd_op(TCGv_i32 val, TCGCond cond, int pos) { - TCGv bit; + TCGv_i32 bit; DisasCompare dc; - dc.temp =3D tcg_temp_new(); - bit =3D tcg_temp_new(); + dc.temp =3D tcg_temp_new_i32(); + bit =3D tcg_temp_new_i32(); psw_cond(&dc, cond); tcg_gen_andi_i32(val, val, ~(1 << pos)); tcg_gen_setcondi_i32(dc.cond, bit, dc.value, 0); @@ -2024,9 +2024,9 @@ static inline void bmcnd_op(TCGv val, TCGCond cond, i= nt pos) /* bmcnd #imm, dsp[rd] */ static bool trans_BMCnd_im(DisasContext *ctx, arg_BMCnd_im *a) { - TCGv val, mem, addr; - val =3D tcg_temp_new(); - mem =3D tcg_temp_new(); + TCGv_i32 val, mem, addr; + val =3D tcg_temp_new_i32(); + mem =3D tcg_temp_new_i32(); addr =3D rx_index_addr(ctx, mem, a->ld, MO_8, a->rd); rx_gen_ld(ctx, MO_8, val, addr); bmcnd_op(val, a->cd, a->imm); @@ -2118,7 +2118,7 @@ static bool trans_MVTIPL(DisasContext *ctx, arg_MVTIP= L *a) /* mvtc #imm, rd */ static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a) { - TCGv imm; + TCGv_i32 imm; =20 imm =3D tcg_constant_i32(a->imm); move_to_cr(ctx, imm, a->cr); @@ -2142,9 +2142,9 @@ static bool trans_MVFC(DisasContext *ctx, arg_MVFC *a) /* rtfi */ static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a) { - TCGv psw; + TCGv_i32 psw; if (is_privileged(ctx, 1)) { - psw =3D tcg_temp_new(); + psw =3D tcg_temp_new_i32(); tcg_gen_mov_i32(cpu_pc, cpu_bpc); tcg_gen_mov_i32(psw, cpu_bpsw); gen_helper_set_psw_rte(tcg_env, psw); @@ -2156,9 +2156,9 @@ static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a) /* rte */ static bool trans_RTE(DisasContext *ctx, arg_RTE *a) { - TCGv psw; + TCGv_i32 psw; if (is_privileged(ctx, 1)) { - psw =3D tcg_temp_new(); + psw =3D tcg_temp_new_i32(); pop(ctx, cpu_pc); pop(ctx, psw); gen_helper_set_psw_rte(tcg_env, psw); @@ -2179,7 +2179,7 @@ static bool trans_BRK(DisasContext *ctx, arg_BRK *a) /* int #imm */ static bool trans_INT(DisasContext *ctx, arg_INT *a) { - TCGv vec; + TCGv_i32 vec; =20 tcg_debug_assert(a->imm < 0x100); vec =3D tcg_constant_i32(a->imm); --=20 2.51.0