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Thu, 09 Oct 2025 00:51:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGczbXWVL2aWvb6Pxa50DHzHGLyehHz6kU28lBmnHI94yWWpjBN10sij+q8Xgc7Qsj9T2AbjA== X-Received: by 2002:a05:6000:2c0d:b0:3e9:9282:cfdf with SMTP id ffacd0b85a97d-4266e8d777bmr4026374f8f.41.1759996290592; Thu, 09 Oct 2025 00:51:30 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Magnus Kulke Subject: [PULL 28/35] target/i386/mshv: Implement mshv_vcpu_run() Date: Thu, 9 Oct 2025 09:50:18 +0200 Message-ID: <20251009075026.505715-29-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251009075026.505715-1-pbonzini@redhat.com> References: <20251009075026.505715-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.442, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1759996602514116600 Content-Type: text/plain; charset="utf-8" From: Magnus Kulke Add the main vCPU execution loop for MSHV using the MSHV_RUN_VP ioctl. The execution loop handles guest entry and VM exits. There are handlers for memory r/w, PIO and MMIO to which the exit events are dispatched. In case of MMIO the i386 instruction decoder/emulator is invoked to perform the operation in user space. Signed-off-by: Magnus Kulke Link: https://lore.kernel.org/r/20250916164847.77883-23-magnuskulke@linux.m= icrosoft.com Signed-off-by: Paolo Bonzini --- target/i386/mshv/mshv-cpu.c | 444 +++++++++++++++++++++++++++++++++++- 1 file changed, 442 insertions(+), 2 deletions(-) diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 33a3ce8b110..7edc032cea3 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -1082,10 +1082,450 @@ void mshv_arch_amend_proc_features( features->access_guest_idle_reg =3D 1; } =20 +static int set_memory_info(const struct hyperv_message *msg, + struct hv_x64_memory_intercept_message *info) +{ + if (msg->header.message_type !=3D HVMSG_GPA_INTERCEPT + && msg->header.message_type !=3D HVMSG_UNMAPPED_GPA + && msg->header.message_type !=3D HVMSG_UNACCEPTED_GPA) { + error_report("invalid message type"); + return -1; + } + memcpy(info, msg->payload, sizeof(*info)); + + return 0; +} + +static int emulate_instruction(CPUState *cpu, + const uint8_t *insn_bytes, size_t insn_len, + uint64_t gva, uint64_t gpa) +{ + X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; + struct x86_decode decode =3D { 0 }; + int ret; + x86_insn_stream stream =3D { .bytes =3D insn_bytes, .len =3D insn_len = }; + + ret =3D mshv_load_regs(cpu); + if (ret < 0) { + error_report("failed to load registers"); + return -1; + } + + decode_instruction_stream(env, &decode, &stream); + exec_instruction(env, &decode); + + ret =3D mshv_store_regs(cpu); + if (ret < 0) { + error_report("failed to store registers"); + return -1; + } + + return 0; +} + +static int handle_mmio(CPUState *cpu, const struct hyperv_message *msg, + MshvVmExit *exit_reason) +{ + struct hv_x64_memory_intercept_message info =3D { 0 }; + size_t insn_len; + uint8_t access_type; + uint8_t *instruction_bytes; + int ret; + + ret =3D set_memory_info(msg, &info); + if (ret < 0) { + error_report("failed to convert message to memory info"); + return -1; + } + insn_len =3D info.instruction_byte_count; + access_type =3D info.header.intercept_access_type; + + if (access_type =3D=3D HV_X64_INTERCEPT_ACCESS_TYPE_EXECUTE) { + error_report("invalid intercept access type: execute"); + return -1; + } + + if (insn_len > 16) { + error_report("invalid mmio instruction length: %zu", insn_len); + return -1; + } + + trace_mshv_handle_mmio(info.guest_virtual_address, + info.guest_physical_address, + info.instruction_byte_count, access_type); + + instruction_bytes =3D info.instruction_bytes; + + ret =3D emulate_instruction(cpu, instruction_bytes, insn_len, + info.guest_virtual_address, + info.guest_physical_address); + if (ret < 0) { + error_report("failed to emulate mmio"); + return -1; + } + + *exit_reason =3D MshvVmExitIgnore; + + return 0; +} + +static int set_ioport_info(const struct hyperv_message *msg, + hv_x64_io_port_intercept_message *info) +{ + if (msg->header.message_type !=3D HVMSG_X64_IO_PORT_INTERCEPT) { + error_report("Invalid message type"); + return -1; + } + memcpy(info, msg->payload, sizeof(*info)); + + return 0; +} + +static int set_x64_registers(const CPUState *cpu, const uint32_t *names, + const uint64_t *values) +{ + + hv_register_assoc assocs[2]; + int ret; + + for (size_t i =3D 0; i < ARRAY_SIZE(assocs); i++) { + assocs[i].name =3D names[i]; + assocs[i].value.reg64 =3D values[i]; + } + + ret =3D mshv_set_generic_regs(cpu, assocs, ARRAY_SIZE(assocs)); + if (ret < 0) { + error_report("failed to set x64 registers"); + return -1; + } + + return 0; +} + +static inline MemTxAttrs get_mem_attrs(bool is_secure_mode) +{ + MemTxAttrs memattr =3D {0}; + memattr.secure =3D is_secure_mode; + return memattr; +} + +static void pio_read(uint64_t port, uint8_t *data, uintptr_t size, + bool is_secure_mode) +{ + int ret =3D 0; + MemTxAttrs memattr =3D get_mem_attrs(is_secure_mode); + ret =3D address_space_rw(&address_space_io, port, memattr, (void *)dat= a, size, + false); + if (ret !=3D MEMTX_OK) { + error_report("Failed to read from port %lx: %d", port, ret); + abort(); + } +} + +static int pio_write(uint64_t port, const uint8_t *data, uintptr_t size, + bool is_secure_mode) +{ + int ret =3D 0; + MemTxAttrs memattr =3D get_mem_attrs(is_secure_mode); + ret =3D address_space_rw(&address_space_io, port, memattr, (void *)dat= a, size, + true); + return ret; +} + +static int handle_pio_non_str(const CPUState *cpu, + hv_x64_io_port_intercept_message *info) +{ + size_t len =3D info->access_info.access_size; + uint8_t access_type =3D info->header.intercept_access_type; + int ret; + uint32_t val, eax; + const uint32_t eax_mask =3D 0xffffffffu >> (32 - len * 8); + size_t insn_len; + uint64_t rip, rax; + uint32_t reg_names[2]; + uint64_t reg_values[2]; + uint16_t port =3D info->port_number; + + if (access_type =3D=3D HV_X64_INTERCEPT_ACCESS_TYPE_WRITE) { + union { + uint32_t u32; + uint8_t bytes[4]; + } conv; + + /* convert the first 4 bytes of rax to bytes */ + conv.u32 =3D (uint32_t)info->rax; + /* secure mode is set to false */ + ret =3D pio_write(port, conv.bytes, len, false); + if (ret < 0) { + error_report("Failed to write to io port"); + return -1; + } + } else { + uint8_t data[4] =3D { 0 }; + /* secure mode is set to false */ + pio_read(info->port_number, data, len, false); + + /* Preserve high bits in EAX, but clear out high bits in RAX */ + val =3D *(uint32_t *)data; + eax =3D (((uint32_t)info->rax) & ~eax_mask) | (val & eax_mask); + info->rax =3D (uint64_t)eax; + } + + insn_len =3D info->header.instruction_length; + + /* Advance RIP and update RAX */ + rip =3D info->header.rip + insn_len; + rax =3D info->rax; + + reg_names[0] =3D HV_X64_REGISTER_RIP; + reg_values[0] =3D rip; + reg_names[1] =3D HV_X64_REGISTER_RAX; + reg_values[1] =3D rax; + + ret =3D set_x64_registers(cpu, reg_names, reg_values); + if (ret < 0) { + error_report("Failed to set x64 registers"); + return -1; + } + + cpu->accel->dirty =3D false; + + return 0; +} + +static int fetch_guest_state(CPUState *cpu) +{ + int ret; + + ret =3D mshv_get_standard_regs(cpu); + if (ret < 0) { + error_report("Failed to get standard registers"); + return -1; + } + + ret =3D mshv_get_special_regs(cpu); + if (ret < 0) { + error_report("Failed to get special registers"); + return -1; + } + + return 0; +} + +static int read_memory(const CPUState *cpu, uint64_t initial_gva, + uint64_t initial_gpa, uint64_t gva, uint8_t *data, + size_t len) +{ + int ret; + uint64_t gpa, flags; + + if (gva =3D=3D initial_gva) { + gpa =3D initial_gpa; + } else { + flags =3D HV_TRANSLATE_GVA_VALIDATE_READ; + ret =3D translate_gva(cpu, gva, &gpa, flags); + if (ret < 0) { + return -1; + } + + ret =3D mshv_guest_mem_read(gpa, data, len, false, false); + if (ret < 0) { + error_report("failed to read guest mem"); + return -1; + } + } + + return 0; +} + +static int write_memory(const CPUState *cpu, uint64_t initial_gva, + uint64_t initial_gpa, uint64_t gva, const uint8_t = *data, + size_t len) +{ + int ret; + uint64_t gpa, flags; + + if (gva =3D=3D initial_gva) { + gpa =3D initial_gpa; + } else { + flags =3D HV_TRANSLATE_GVA_VALIDATE_WRITE; + ret =3D translate_gva(cpu, gva, &gpa, flags); + if (ret < 0) { + error_report("failed to translate gva to gpa"); + return -1; + } + } + ret =3D mshv_guest_mem_write(gpa, data, len, false); + if (ret !=3D MEMTX_OK) { + error_report("failed to write to mmio"); + return -1; + } + + return 0; +} + +static int handle_pio_str_write(CPUState *cpu, + hv_x64_io_port_intercept_message *info, + size_t repeat, uint16_t port, + bool direction_flag) +{ + int ret; + uint64_t src; + uint8_t data[4] =3D { 0 }; + size_t len =3D info->access_info.access_size; + + src =3D linear_addr(cpu, info->rsi, R_DS); + + for (size_t i =3D 0; i < repeat; i++) { + ret =3D read_memory(cpu, 0, 0, src, data, len); + if (ret < 0) { + error_report("Failed to read memory"); + return -1; + } + ret =3D pio_write(port, data, len, false); + if (ret < 0) { + error_report("Failed to write to io port"); + return -1; + } + src +=3D direction_flag ? -len : len; + info->rsi +=3D direction_flag ? -len : len; + } + + return 0; +} + +static int handle_pio_str_read(CPUState *cpu, + hv_x64_io_port_intercept_message *info, + size_t repeat, uint16_t port, + bool direction_flag) +{ + int ret; + uint64_t dst; + size_t len =3D info->access_info.access_size; + uint8_t data[4] =3D { 0 }; + + dst =3D linear_addr(cpu, info->rdi, R_ES); + + for (size_t i =3D 0; i < repeat; i++) { + pio_read(port, data, len, false); + + ret =3D write_memory(cpu, 0, 0, dst, data, len); + if (ret < 0) { + error_report("Failed to write memory"); + return -1; + } + dst +=3D direction_flag ? -len : len; + info->rdi +=3D direction_flag ? -len : len; + } + + return 0; +} + +static int handle_pio_str(CPUState *cpu, hv_x64_io_port_intercept_message = *info) +{ + uint8_t access_type =3D info->header.intercept_access_type; + uint16_t port =3D info->port_number; + bool repop =3D info->access_info.rep_prefix =3D=3D 1; + size_t repeat =3D repop ? info->rcx : 1; + size_t insn_len =3D info->header.instruction_length; + bool direction_flag; + uint32_t reg_names[3]; + uint64_t reg_values[3]; + int ret; + X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; + + ret =3D fetch_guest_state(cpu); + if (ret < 0) { + error_report("Failed to fetch guest state"); + return -1; + } + + direction_flag =3D (env->eflags & DESC_E_MASK) !=3D 0; + + if (access_type =3D=3D HV_X64_INTERCEPT_ACCESS_TYPE_WRITE) { + ret =3D handle_pio_str_write(cpu, info, repeat, port, direction_fl= ag); + if (ret < 0) { + error_report("Failed to handle pio str write"); + return -1; + } + reg_names[0] =3D HV_X64_REGISTER_RSI; + reg_values[0] =3D info->rsi; + } else { + ret =3D handle_pio_str_read(cpu, info, repeat, port, direction_fla= g); + reg_names[0] =3D HV_X64_REGISTER_RDI; + reg_values[0] =3D info->rdi; + } + + reg_names[1] =3D HV_X64_REGISTER_RIP; + reg_values[1] =3D info->header.rip + insn_len; + reg_names[2] =3D HV_X64_REGISTER_RAX; + reg_values[2] =3D info->rax; + + ret =3D set_x64_registers(cpu, reg_names, reg_values); + if (ret < 0) { + error_report("Failed to set x64 registers"); + return -1; + } + + cpu->accel->dirty =3D false; + + return 0; +} + +static int handle_pio(CPUState *cpu, const struct hyperv_message *msg) +{ + struct hv_x64_io_port_intercept_message info =3D { 0 }; + int ret; + + ret =3D set_ioport_info(msg, &info); + if (ret < 0) { + error_report("Failed to convert message to ioport info"); + return -1; + } + + if (info.access_info.string_op) { + return handle_pio_str(cpu, &info); + } + + return handle_pio_non_str(cpu, &info); +} + int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *e= xit) { - error_report("unimplemented"); - abort(); + int ret; + enum MshvVmExit exit_reason; + int cpu_fd =3D mshv_vcpufd(cpu); + + ret =3D ioctl(cpu_fd, MSHV_RUN_VP, msg); + if (ret < 0) { + return MshvVmExitShutdown; + } + + switch (msg->header.message_type) { + case HVMSG_UNRECOVERABLE_EXCEPTION: + return MshvVmExitShutdown; + case HVMSG_UNMAPPED_GPA: + case HVMSG_GPA_INTERCEPT: + ret =3D handle_mmio(cpu, msg, &exit_reason); + if (ret < 0) { + error_report("failed to handle mmio"); + return -1; + } + return exit_reason; + case HVMSG_X64_IO_PORT_INTERCEPT: + ret =3D handle_pio(cpu, msg); + if (ret < 0) { + return MshvVmExitSpecial; + } + return MshvVmExitIgnore; + default: + break; + } + + *exit =3D MshvVmExitIgnore; + return 0; } =20 void mshv_remove_vcpu(int vm_fd, int cpu_fd) --=20 2.51.0