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Thu, 09 Oct 2025 00:51:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHh5BzeOpzk9YPY5rNBi9iy/9ASzYHyFCbO4IG9chXAV+bzn0eFFWirCrk2ibM+n0Uczpk3uA== X-Received: by 2002:a05:600d:8110:b0:45f:2922:2aef with SMTP id 5b1f17b1804b1-46fa9b09233mr34363585e9.28.1759996276453; Thu, 09 Oct 2025 00:51:16 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Magnus Kulke Subject: [PULL 22/35] target/i386/mshv: Implement mshv_arch_put_registers() Date: Thu, 9 Oct 2025 09:50:12 +0200 Message-ID: <20251009075026.505715-23-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251009075026.505715-1-pbonzini@redhat.com> References: <20251009075026.505715-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.442, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1759996374292154100 Content-Type: text/plain; charset="utf-8" From: Magnus Kulke Write CPU register state to MSHV vCPUs. Various mapping functions to prepare the payload for the HV call have been implemented. Signed-off-by: Magnus Kulke Link: https://lore.kernel.org/r/20250916164847.77883-17-magnuskulke@linux.m= icrosoft.com [mshv.h/mshv_int.h split. - Paolo] Signed-off-by: Paolo Bonzini --- include/system/mshv_int.h | 15 +++ target/i386/mshv/mshv-cpu.c | 237 ++++++++++++++++++++++++++++++++++++ 2 files changed, 252 insertions(+) diff --git a/include/system/mshv_int.h b/include/system/mshv_int.h index c6e6e8af307..0ea8d504fa5 100644 --- a/include/system/mshv_int.h +++ b/include/system/mshv_int.h @@ -49,6 +49,20 @@ typedef struct MshvMsiControl { #define mshv_vcpufd(cpu) (cpu->accel->cpufd) =20 /* cpu */ +typedef struct MshvFPU { + uint8_t fpr[8][16]; + uint16_t fcw; + uint16_t fsw; + uint8_t ftwx; + uint8_t pad1; + uint16_t last_opcode; + uint64_t last_ip; + uint64_t last_dp; + uint8_t xmm[16][16]; + uint32_t mxcsr; + uint32_t pad2; +} MshvFPU; + typedef enum MshvVmExit { MshvVmExitIgnore =3D 0, MshvVmExitShutdown =3D 1, @@ -58,6 +72,7 @@ typedef enum MshvVmExit { void mshv_init_mmio_emu(void); int mshv_create_vcpu(int vm_fd, uint8_t vp_index, int *cpu_fd); void mshv_remove_vcpu(int vm_fd, int cpu_fd); +int mshv_configure_vcpu(const CPUState *cpu, const MshvFPU *fpu, uint64_t = xcr0); int mshv_get_standard_regs(CPUState *cpu); int mshv_get_special_regs(CPUState *cpu); int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *e= xit); diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index bc75686f828..8b10c79e547 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -73,6 +73,35 @@ static enum hv_register_name SPECIAL_REGISTER_NAMES[17] = =3D { HV_X64_REGISTER_APIC_BASE, }; =20 +static enum hv_register_name FPU_REGISTER_NAMES[26] =3D { + HV_X64_REGISTER_XMM0, + HV_X64_REGISTER_XMM1, + HV_X64_REGISTER_XMM2, + HV_X64_REGISTER_XMM3, + HV_X64_REGISTER_XMM4, + HV_X64_REGISTER_XMM5, + HV_X64_REGISTER_XMM6, + HV_X64_REGISTER_XMM7, + HV_X64_REGISTER_XMM8, + HV_X64_REGISTER_XMM9, + HV_X64_REGISTER_XMM10, + HV_X64_REGISTER_XMM11, + HV_X64_REGISTER_XMM12, + HV_X64_REGISTER_XMM13, + HV_X64_REGISTER_XMM14, + HV_X64_REGISTER_XMM15, + HV_X64_REGISTER_FP_MMX0, + HV_X64_REGISTER_FP_MMX1, + HV_X64_REGISTER_FP_MMX2, + HV_X64_REGISTER_FP_MMX3, + HV_X64_REGISTER_FP_MMX4, + HV_X64_REGISTER_FP_MMX5, + HV_X64_REGISTER_FP_MMX6, + HV_X64_REGISTER_FP_MMX7, + HV_X64_REGISTER_FP_CONTROL_STATUS, + HV_X64_REGISTER_XMM_CONTROL_STATUS, +}; + int mshv_set_generic_regs(const CPUState *cpu, const hv_register_assoc *as= socs, size_t n_regs) { @@ -372,8 +401,216 @@ int mshv_load_regs(CPUState *cpu) return 0; } =20 +static inline void populate_hv_segment_reg(SegmentCache *seg, + hv_x64_segment_register *hv_reg) +{ + uint32_t flags =3D seg->flags; + + hv_reg->base =3D seg->base; + hv_reg->limit =3D seg->limit; + hv_reg->selector =3D seg->selector; + hv_reg->segment_type =3D (flags >> DESC_TYPE_SHIFT) & 0xF; + hv_reg->non_system_segment =3D (flags & DESC_S_MASK) !=3D 0; + hv_reg->descriptor_privilege_level =3D (flags >> DESC_DPL_SHIFT) & 0x3; + hv_reg->present =3D (flags & DESC_P_MASK) !=3D 0; + hv_reg->reserved =3D 0; + hv_reg->available =3D (flags & DESC_AVL_MASK) !=3D 0; + hv_reg->_long =3D (flags >> DESC_L_SHIFT) & 0x1; + hv_reg->_default =3D (flags >> DESC_B_SHIFT) & 0x1; + hv_reg->granularity =3D (flags & DESC_G_MASK) !=3D 0; +} + +static inline void populate_hv_table_reg(const struct SegmentCache *seg, + hv_x64_table_register *hv_reg) +{ + memset(hv_reg, 0, sizeof(*hv_reg)); + + hv_reg->base =3D seg->base; + hv_reg->limit =3D seg->limit; +} + +static int set_special_regs(const CPUState *cpu) +{ + X86CPU *x86cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86cpu->env; + struct hv_register_assoc assocs[ARRAY_SIZE(SPECIAL_REGISTER_NAMES)]; + size_t n_regs =3D ARRAY_SIZE(SPECIAL_REGISTER_NAMES); + int ret; + + /* set names */ + for (size_t i =3D 0; i < n_regs; i++) { + assocs[i].name =3D SPECIAL_REGISTER_NAMES[i]; + } + populate_hv_segment_reg(&env->segs[R_CS], &assocs[0].value.segment); + populate_hv_segment_reg(&env->segs[R_DS], &assocs[1].value.segment); + populate_hv_segment_reg(&env->segs[R_ES], &assocs[2].value.segment); + populate_hv_segment_reg(&env->segs[R_FS], &assocs[3].value.segment); + populate_hv_segment_reg(&env->segs[R_GS], &assocs[4].value.segment); + populate_hv_segment_reg(&env->segs[R_SS], &assocs[5].value.segment); + populate_hv_segment_reg(&env->tr, &assocs[6].value.segment); + populate_hv_segment_reg(&env->ldt, &assocs[7].value.segment); + + populate_hv_table_reg(&env->gdt, &assocs[8].value.table); + populate_hv_table_reg(&env->idt, &assocs[9].value.table); + + assocs[10].value.reg64 =3D env->cr[0]; + assocs[11].value.reg64 =3D env->cr[2]; + assocs[12].value.reg64 =3D env->cr[3]; + assocs[13].value.reg64 =3D env->cr[4]; + assocs[14].value.reg64 =3D cpu_get_apic_tpr(x86cpu->apic_state); + assocs[15].value.reg64 =3D env->efer; + assocs[16].value.reg64 =3D cpu_get_apic_base(x86cpu->apic_state); + + ret =3D mshv_set_generic_regs(cpu, assocs, n_regs); + if (ret < 0) { + error_report("failed to set special registers"); + return -1; + } + + return 0; +} + +static int set_fpu(const CPUState *cpu, const struct MshvFPU *regs) +{ + struct hv_register_assoc assocs[ARRAY_SIZE(FPU_REGISTER_NAMES)]; + union hv_register_value *value; + size_t fp_i; + union hv_x64_fp_control_status_register *ctrl_status; + union hv_x64_xmm_control_status_register *xmm_ctrl_status; + int ret; + size_t n_regs =3D ARRAY_SIZE(FPU_REGISTER_NAMES); + + /* first 16 registers are xmm0-xmm15 */ + for (size_t i =3D 0; i < 16; i++) { + assocs[i].name =3D FPU_REGISTER_NAMES[i]; + value =3D &assocs[i].value; + memcpy(&value->reg128, ®s->xmm[i], 16); + } + + /* next 8 registers are fp_mmx0-fp_mmx7 */ + for (size_t i =3D 16; i < 24; i++) { + assocs[i].name =3D FPU_REGISTER_NAMES[i]; + fp_i =3D (i - 16); + value =3D &assocs[i].value; + memcpy(&value->reg128, ®s->fpr[fp_i], 16); + } + + /* last two registers are fp_control_status and xmm_control_status */ + assocs[24].name =3D FPU_REGISTER_NAMES[24]; + value =3D &assocs[24].value; + ctrl_status =3D &value->fp_control_status; + ctrl_status->fp_control =3D regs->fcw; + ctrl_status->fp_status =3D regs->fsw; + ctrl_status->fp_tag =3D regs->ftwx; + ctrl_status->reserved =3D 0; + ctrl_status->last_fp_op =3D regs->last_opcode; + ctrl_status->last_fp_rip =3D regs->last_ip; + + assocs[25].name =3D FPU_REGISTER_NAMES[25]; + value =3D &assocs[25].value; + xmm_ctrl_status =3D &value->xmm_control_status; + xmm_ctrl_status->xmm_status_control =3D regs->mxcsr; + xmm_ctrl_status->xmm_status_control_mask =3D 0; + xmm_ctrl_status->last_fp_rdp =3D regs->last_dp; + + ret =3D mshv_set_generic_regs(cpu, assocs, n_regs); + if (ret < 0) { + error_report("failed to set fpu registers"); + return -1; + } + + return 0; +} + +static int set_xc_reg(const CPUState *cpu, uint64_t xcr0) +{ + int ret; + struct hv_register_assoc assoc =3D { + .name =3D HV_X64_REGISTER_XFEM, + .value.reg64 =3D xcr0, + }; + + ret =3D mshv_set_generic_regs(cpu, &assoc, 1); + if (ret < 0) { + error_report("failed to set xcr0"); + return -errno; + } + return 0; +} + +static int set_cpu_state(const CPUState *cpu, const MshvFPU *fpu_regs, + uint64_t xcr0) +{ + int ret; + + ret =3D set_standard_regs(cpu); + if (ret < 0) { + return ret; + } + ret =3D set_special_regs(cpu); + if (ret < 0) { + return ret; + } + ret =3D set_fpu(cpu, fpu_regs); + if (ret < 0) { + return ret; + } + ret =3D set_xc_reg(cpu, xcr0); + if (ret < 0) { + return ret; + } + return 0; +} + +/* + * TODO: populate topology info: + * + * X86CPU *x86cpu =3D X86_CPU(cpu); + * CPUX86State *env =3D &x86cpu->env; + * X86CPUTopoInfo *topo_info =3D &env->topo_info; + */ +int mshv_configure_vcpu(const CPUState *cpu, const struct MshvFPU *fpu, + uint64_t xcr0) +{ + int ret; + + ret =3D set_cpu_state(cpu, fpu, xcr0); + if (ret < 0) { + error_report("failed to set cpu state"); + return -1; + } + + return 0; +} + +static int put_regs(const CPUState *cpu) +{ + X86CPU *x86cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86cpu->env; + MshvFPU fpu =3D {0}; + int ret; + + memset(&fpu, 0, sizeof(fpu)); + + ret =3D mshv_configure_vcpu(cpu, &fpu, env->xcr0); + if (ret < 0) { + error_report("failed to configure vcpu"); + return ret; + } + + return 0; +} + int mshv_arch_put_registers(const CPUState *cpu) { + int ret; + + ret =3D put_regs(cpu); + if (ret < 0) { + error_report("Failed to put registers"); + return -1; + } + error_report("unimplemented"); abort(); } --=20 2.51.0