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Thu, 09 Oct 2025 00:51:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFnB/z1c3Q3wgqAXdsU2+WjHB7mMZ9qP/aVL6lqbAqDwyhA/Y9egxDQCtC4gaExVjQunTrRfA== X-Received: by 2002:a05:600c:6388:b0:46e:1a07:7bd5 with SMTP id 5b1f17b1804b1-46fa9b0797cmr44423085e9.29.1759996270483; Thu, 09 Oct 2025 00:51:10 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Magnus Kulke Subject: [PULL 20/35] target/i386/mshv: Implement mshv_get_standard_regs() Date: Thu, 9 Oct 2025 09:50:10 +0200 Message-ID: <20251009075026.505715-21-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251009075026.505715-1-pbonzini@redhat.com> References: <20251009075026.505715-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.442, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1759996350331154100 Content-Type: text/plain; charset="utf-8" From: Magnus Kulke Fetch standard register state from MSHV vCPUs to support debugging, migration, and other introspection features in QEMU. Fetch standard register state from a MHSV vCPU's. A generic get_regs() function and a mapper to map the different register representations are introduced. Signed-off-by: Magnus Kulke Link: https://lore.kernel.org/r/20250916164847.77883-15-magnuskulke@linux.m= icrosoft.com [mshv.h/mshv_int.h split. - Paolo] Signed-off-by: Paolo Bonzini --- include/system/mshv_int.h | 1 + target/i386/mshv/mshv-cpu.c | 116 +++++++++++++++++++++++++++++++++++- 2 files changed, 115 insertions(+), 2 deletions(-) diff --git a/include/system/mshv_int.h b/include/system/mshv_int.h index 731841af929..b0a79296ad9 100644 --- a/include/system/mshv_int.h +++ b/include/system/mshv_int.h @@ -58,6 +58,7 @@ typedef enum MshvVmExit { void mshv_init_mmio_emu(void); int mshv_create_vcpu(int vm_fd, uint8_t vp_index, int *cpu_fd); void mshv_remove_vcpu(int vm_fd, int cpu_fd); +int mshv_get_standard_regs(CPUState *cpu); int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *e= xit); int mshv_load_regs(CPUState *cpu); int mshv_store_regs(CPUState *cpu); diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 9ead03ca2d8..4e3eee113bb 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -96,6 +96,66 @@ int mshv_set_generic_regs(const CPUState *cpu, const hv_= register_assoc *assocs, return 0; } =20 +static int get_generic_regs(CPUState *cpu, hv_register_assoc *assocs, + size_t n_regs) +{ + int cpu_fd =3D mshv_vcpufd(cpu); + int vp_index =3D cpu->cpu_index; + hv_input_get_vp_registers *in; + hv_register_value *values; + size_t in_sz, names_sz, values_sz; + int i, ret; + struct mshv_root_hvcall args =3D {0}; + + /* find out the size of the struct w/ a flexible array at the tail */ + names_sz =3D n_regs * sizeof(hv_register_name); + in_sz =3D sizeof(hv_input_get_vp_registers) + names_sz; + + /* fill the input struct */ + in =3D g_malloc0(in_sz); + in->vp_index =3D vp_index; + for (i =3D 0; i < n_regs; i++) { + in->names[i] =3D assocs[i].name; + } + + /* allocate value output buffer */ + values_sz =3D n_regs * sizeof(union hv_register_value); + values =3D g_malloc0(values_sz); + + /* create the hvcall envelope */ + args.code =3D HVCALL_GET_VP_REGISTERS; + args.in_sz =3D in_sz; + args.in_ptr =3D (uint64_t) in; + args.out_sz =3D values_sz; + args.out_ptr =3D (uint64_t) values; + args.reps =3D (uint16_t) n_regs; + + /* perform the call */ + ret =3D mshv_hvcall(cpu_fd, &args); + g_free(in); + if (ret < 0) { + g_free(values); + error_report("Failed to retrieve registers"); + return -1; + } + + /* assert we got all registers */ + if (args.reps !=3D n_regs) { + g_free(values); + error_report("Failed to retrieve registers: expected %zu elements" + ", got %u", n_regs, args.reps); + return -1; + } + + /* copy values into assoc */ + for (i =3D 0; i < n_regs; i++) { + assocs[i].value =3D values[i]; + } + g_free(values); + + return 0; +} + static int set_standard_regs(const CPUState *cpu) { X86CPU *x86cpu =3D X86_CPU(cpu); @@ -149,11 +209,63 @@ int mshv_store_regs(CPUState *cpu) return 0; } =20 +static void populate_standard_regs(const hv_register_assoc *assocs, + CPUX86State *env) +{ + env->regs[R_EAX] =3D assocs[0].value.reg64; + env->regs[R_EBX] =3D assocs[1].value.reg64; + env->regs[R_ECX] =3D assocs[2].value.reg64; + env->regs[R_EDX] =3D assocs[3].value.reg64; + env->regs[R_ESI] =3D assocs[4].value.reg64; + env->regs[R_EDI] =3D assocs[5].value.reg64; + env->regs[R_ESP] =3D assocs[6].value.reg64; + env->regs[R_EBP] =3D assocs[7].value.reg64; + env->regs[R_R8] =3D assocs[8].value.reg64; + env->regs[R_R9] =3D assocs[9].value.reg64; + env->regs[R_R10] =3D assocs[10].value.reg64; + env->regs[R_R11] =3D assocs[11].value.reg64; + env->regs[R_R12] =3D assocs[12].value.reg64; + env->regs[R_R13] =3D assocs[13].value.reg64; + env->regs[R_R14] =3D assocs[14].value.reg64; + env->regs[R_R15] =3D assocs[15].value.reg64; + + env->eip =3D assocs[16].value.reg64; + env->eflags =3D assocs[17].value.reg64; + rflags_to_lflags(env); +} + +int mshv_get_standard_regs(CPUState *cpu) +{ + struct hv_register_assoc assocs[ARRAY_SIZE(STANDARD_REGISTER_NAMES)]; + int ret; + X86CPU *x86cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86cpu->env; + size_t n_regs =3D ARRAY_SIZE(STANDARD_REGISTER_NAMES); + + for (size_t i =3D 0; i < n_regs; i++) { + assocs[i].name =3D STANDARD_REGISTER_NAMES[i]; + } + ret =3D get_generic_regs(cpu, assocs, n_regs); + if (ret < 0) { + error_report("failed to get standard registers"); + return -1; + } + + populate_standard_regs(assocs, env); + return 0; +} =20 int mshv_load_regs(CPUState *cpu) { - error_report("unimplemented"); - abort(); + int ret; + + ret =3D mshv_get_standard_regs(cpu); + if (ret < 0) { + error_report("Failed to load standard registers"); + return -1; + } + + return 0; } =20 int mshv_arch_put_registers(const CPUState *cpu) --=20 2.51.0