From nobody Fri Nov 14 23:30:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1759977288; cv=none; d=zohomail.com; s=zohoarc; b=EozpPkbx10zKUMD8Xfqjq54kWlhGcRoXsepidpWFcWhCXs4kNV6rWBUOulSAqlunLhe6SR4QAbBn/uWJHMxMSph0xNE/b2NicMW2Ms8/B9lh/2b3A1e1iWUsQa+4MUNt084b59kEhmut+DC/rdOa6Ji+DbAv6FUB5AoV9J4EzD4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1759977288; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=ijQqw023mueq1GoiEigrLEclw2en2CRMnvi1zBCZW0Q=; b=Jl5UEEDsKtQkiGmUfT40N4zBKROQxH3V3NhQwzswUDcsgKGHqXXyv2E1wng4Bkf9UC0OA3PV4F2zlGhkUt0YE/xIeD7g6LO0CgRST5qti2vkDVwLMJpu0mi80bSdIe4SvJGNoaf202/4N8N2WF0qMd2Vn/sWodfrg/iFOZGuKNo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759977288012790.3483449806856; Wed, 8 Oct 2025 19:34:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v6gT5-0006ZL-C0; Wed, 08 Oct 2025 22:33:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v6gT4-0006Z9-CS; Wed, 08 Oct 2025 22:33:22 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v6gT1-0007cH-MO; Wed, 08 Oct 2025 22:33:22 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 9 Oct 2025 10:33:02 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 9 Oct 2025 10:33:02 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v2 01/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_uart_first() API Date: Thu, 9 Oct 2025 10:32:40 +0800 Message-ID: <20251009023301.4085829-2-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251009023301.4085829-1-jamin_lin@aspeedtech.com> References: <20251009023301.4085829-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759977296932116600 Content-Type: text/plain; charset="utf-8" Refactor the aspeed_uart_first() helper to remove its dependency on AspeedSoCState and make the UART helper APIs more generic. The function now takes uarts_base as an integer parameter instead of requiring a full SoC class instance. Corresponding call sites in aspeed.c and aspeed_soc_common.c are updated accordingly. No functional change. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 6 +++--- hw/arm/aspeed.c | 2 +- hw/arm/aspeed_soc_common.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index ed32efb543..5786fbbcbb 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -326,14 +326,14 @@ static inline int aspeed_uart_index(int uart_dev) return uart_dev - ASPEED_DEV_UART0; } =20 -static inline int aspeed_uart_first(AspeedSoCClass *sc) +static inline int aspeed_uart_first(int uarts_base) { - return aspeed_uart_index(sc->uarts_base); + return aspeed_uart_index(uarts_base); } =20 static inline int aspeed_uart_last(AspeedSoCClass *sc) { - return aspeed_uart_first(sc) + sc->uarts_num - 1; + return aspeed_uart_first(sc->uarts_base) + sc->uarts_num - 1; } =20 #endif /* ASPEED_SOC_H */ diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 6046ec0bb2..471ad7fb84 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1310,7 +1310,7 @@ static void aspeed_set_bmc_console(Object *obj, const= char *value, Error **errp) AspeedMachineClass *amc =3D ASPEED_MACHINE_GET_CLASS(bmc); AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(object_class_by_name(amc->soc_= name)); int val; - int uart_first =3D aspeed_uart_first(sc); + int uart_first =3D aspeed_uart_first(sc->uarts_base); int uart_last =3D aspeed_uart_last(sc); =20 if (sscanf(value, "uart%u", &val) !=3D 1) { diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index bc70e864fb..a4e74acdce 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -62,7 +62,7 @@ bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **e= rrp) void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr) { AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); - int uart_first =3D aspeed_uart_first(sc); + int uart_first =3D aspeed_uart_first(sc->uarts_base); int uart_index =3D aspeed_uart_index(dev); int i =3D uart_index - uart_first; =20 --=20 2.43.0