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With PIE, the PTE layout changes, forcing HPD. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 3 ++- target/arm/helper.c | 19 ++++++++++++++++++- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1d958dbf68..face1019f5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1491,7 +1491,7 @@ static inline int arm_granule_bits(ARMGranuleSize gra= n) =20 /* * Parameters of a given virtual address, as extracted from the - * translation control register (TCR) for a given regime. + * translation controls for a given regime. */ typedef struct ARMVAParameters { unsigned tsz : 8; @@ -1506,6 +1506,7 @@ typedef struct ARMVAParameters { bool ha : 1; bool hd : 1; ARMGranuleSize gran : 2; + bool pie : 1; } ARMVAParameters; =20 /** diff --git a/target/arm/helper.c b/target/arm/helper.c index b7bc27436f..37865bf70e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9386,11 +9386,12 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, bool el1_is_aa32) { uint64_t tcr =3D regime_tcr(env, mmu_idx); - bool epd, hpd, tsz_oob, ds, ha, hd; + bool epd, hpd, tsz_oob, ds, ha, hd, pie =3D false; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; ARMGranuleSize gran; ARMCPU *cpu =3D env_archcpu(env); bool stage2 =3D regime_is_stage2(mmu_idx); + int r_el =3D regime_el(env, mmu_idx); =20 if (!regime_has_2_ranges(mmu_idx)) { select =3D 0; @@ -9402,8 +9403,17 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env,= uint64_t va, * Thus disabling them makes things easier during ptw. */ hpd =3D true; + pie =3D extract64(tcr, 36, 1) && cpu_isar_feature(aa64_s2pie, = cpu); } else { hpd =3D extract32(tcr, 24, 1); + if (r_el =3D=3D 3) { + pie =3D (extract64(tcr, 35, 1) + && cpu_isar_feature(aa64_s1pie, cpu)); + } else { + pie =3D ((env->cp15.tcr2_el[2] & TCR2_PIE) + && (!arm_feature(env, ARM_FEATURE_EL3) + || (env->cp15.scr_el3 & SCR_TCR2EN))); + } } epd =3D false; sh =3D extract32(tcr, 12, 2); @@ -9443,7 +9453,13 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env,= uint64_t va, regime_is_user(env, mmu_idx)) { epd =3D true; } + + pie =3D ((env->cp15.tcr2_el[r_el] & TCR2_PIE) + && (!arm_feature(env, ARM_FEATURE_EL3) + || (env->cp15.scr_el3 & SCR_TCR2EN)) + && (r_el =3D=3D 2 || (arm_hcrx_el2_eff(env) & HCRX_TCR2EN))= ); } + hpd |=3D pie; =20 gran =3D sanitize_gran_size(cpu, gran, stage2); =20 @@ -9522,6 +9538,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, = uint64_t va, .ha =3D ha, .hd =3D ha && hd, .gran =3D gran, + .pie =3D pie, }; } =20 --=20 2.43.0