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Wed, 08 Oct 2025 14:59:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v7 52/73] target/arm: Implement GCSPOPCX Date: Wed, 8 Oct 2025 14:55:52 -0700 Message-ID: <20251008215613.300150-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251008215613.300150-1-richard.henderson@linaro.org> References: <20251008215613.300150-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1759961339907116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 1 + target/arm/cpregs-gcs.c | 17 +++++++++++ target/arm/tcg/translate-a64.c | 56 ++++++++++++++++++++++++++++++++++ 3 files changed, 74 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index ccf45fd136..6d9145109f 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -52,6 +52,7 @@ enum { ARM_CP_GCSPOPM =3D 0x0009, ARM_CP_GCSPUSHX =3D 0x000a, ARM_CP_GCSPOPX =3D 0x000b, + ARM_CP_GCSPOPCX =3D 0x000c, =20 /* Flag: reads produce resetvalue; writes ignored. */ ARM_CP_CONST =3D 1 << 4, diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c index 5b5b895a09..3795bf7f36 100644 --- a/target/arm/cpregs-gcs.c +++ b/target/arm/cpregs-gcs.c @@ -66,6 +66,19 @@ static CPAccessResult access_gcspushx(CPUARMState *env, = const ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +static CPAccessResult access_gcspopcx(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + /* Trap if lock not taken, and enabled. */ + if (env->pstate & PSTATE_EXLOCK) { + int el =3D arm_current_el(env); + if (env->cp15.gcscr_el[el] & GCSCR_EXLOCKEN) { + return CP_ACCESS_EXLOCK; + } + } + return CP_ACCESS_OK; +} + static const ARMCPRegInfo gcs_reginfo[] =3D { { .name =3D "GCSCRE0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 5, .opc2 =3D 2, @@ -120,6 +133,10 @@ static const ARMCPRegInfo gcs_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 7, .opc2 =3D 4, .access =3D PL1_W, .accessfn =3D access_gcspushx, .fgt =3D FGT_NGCSE= PP, .type =3D ARM_CP_GCSPUSHX }, + { .name =3D "GCSPOPCX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 7, .opc2 =3D 5, + .access =3D PL1_W, .accessfn =3D access_gcspopcx, .fgt =3D FGT_NGCSE= PP, + .type =3D ARM_CP_GCSPOPCX }, { .name =3D "GCSPOPX", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 7, .opc2 =3D 6, .access =3D PL1_W, .type =3D ARM_CP_GCSPOPX }, diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 72b912a605..bb8ffba586 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2568,6 +2568,54 @@ static void gen_gcspushx(DisasContext *s) clear_pstate_bits(PSTATE_EXLOCK); } =20 +static void gen_gcspopcx(DisasContext *s) +{ + TCGv_i64 gcspr =3D cpu_gcspr[s->current_el]; + int spsr_idx =3D aarch64_banked_spsr_index(s->current_el); + int spsr_off =3D offsetof(CPUARMState, banked_spsr[spsr_idx]); + int elr_off =3D offsetof(CPUARMState, elr_el[s->current_el]); + int gcscr_off =3D offsetof(CPUARMState, cp15.gcscr_el[s->current_el]); + int pstate_off =3D offsetof(CPUARMState, pstate); + int mmuidx =3D core_gcs_mem_index(s->mmu_idx); + MemOp mop =3D finalize_memop(s, MO_64 | MO_ALIGN); + TCGv_i64 addr =3D tcg_temp_new_i64(); + TCGv_i64 tmp1 =3D tcg_temp_new_i64(); + TCGv_i64 tmp2 =3D tcg_temp_new_i64(); + TCGLabel *fail_label =3D + delay_exception(s, EXCP_UDEF, syn_gcs_data_check(GCS_IT_GCSPOPCX, = 31)); + + /* The value at top-of-stack must be an exception token. */ + tcg_gen_qemu_ld_i64(tmp1, gcspr, mmuidx, mop); + tcg_gen_brcondi_i64(TCG_COND_NE, tmp1, 0b1001, fail_label); + + /* Validate in turn, ELR ... */ + tcg_gen_addi_i64(addr, gcspr, 8); + tcg_gen_qemu_ld_i64(tmp1, addr, mmuidx, mop); + tcg_gen_ld_i64(tmp2, tcg_env, elr_off); + tcg_gen_brcond_i64(TCG_COND_NE, tmp1, tmp2, fail_label); + + /* ... SPSR ... */ + tcg_gen_addi_i64(addr, addr, 8); + tcg_gen_qemu_ld_i64(tmp1, addr, mmuidx, mop); + tcg_gen_ld_i64(tmp2, tcg_env, spsr_off); + tcg_gen_brcond_i64(TCG_COND_NE, tmp1, tmp2, fail_label); + + /* ... and LR. */ + tcg_gen_addi_i64(addr, addr, 8); + tcg_gen_qemu_ld_i64(tmp1, addr, mmuidx, mop); + tcg_gen_brcond_i64(TCG_COND_NE, tmp1, cpu_reg(s, 30), fail_label); + + /* Writeback stack pointer after pop. */ + tcg_gen_addi_i64(gcspr, addr, 8); + + /* PSTATE.EXLOCK =3D GetCurrentEXLOCKEN(). */ + tcg_gen_ld_i64(tmp1, tcg_env, gcscr_off); + tcg_gen_ld_i64(tmp2, tcg_env, pstate_off); + tcg_gen_shri_i64(tmp1, tmp1, ctz64(GCSCR_EXLOCKEN)); + tcg_gen_deposit_i64(tmp2, tmp2, tmp1, ctz64(PSTATE_EXLOCK), 1); + tcg_gen_st_i64(tmp2, tcg_env, pstate_off); +} + static void gen_gcspopx(DisasContext *s) { TCGv_i64 gcspr =3D cpu_gcspr[s->current_el]; @@ -2920,6 +2968,14 @@ static void handle_sys(DisasContext *s, bool isread, gen_gcspushx(s); } return; + case ARM_CP_GCSPOPCX: + /* Choose the CONSTRAINED UNPREDICTABLE for UNDEF. */ + if (rt !=3D 31) { + unallocated_encoding(s); + } else if (s->gcs_en) { + gen_gcspopcx(s); + } + return; case ARM_CP_GCSPOPX: /* Choose the CONSTRAINED UNPREDICTABLE for UNDEF. */ if (rt !=3D 31) { --=20 2.43.0