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charset="utf-8" The AMD IOMMU is set up at boot time and uses PCI bus numbers + devfn for indexing into DTE. The problem is that before the guest started, all PCI bus numbers are 0 as no PCI discovery happened yet (BIOS or/and kernel will do that later) so relying on the bus number is wrong. The immediate effect is emulated devices cannot do DMA when places on a bus other that 0. Replace static array of address_space with hash table which uses devfn and PCIBus* for key as it is not going to change after the guest is booted. Co-developed-by: Alexey Kardashevskiy Signed-off-by: Alexey Kardashevskiy Signed-off-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 127 ++++++++++++++++++++++++++------------------ hw/i386/amd_iommu.h | 2 +- 2 files changed, 77 insertions(+), 52 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 378e0cb55eab..0a4b4d46d885 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -59,7 +59,7 @@ const char *amdvi_mmio_high[] =3D { }; =20 struct AMDVIAddressSpace { - uint8_t bus_num; /* bus number */ + PCIBus *bus; /* PCIBus (for bus number) */ uint8_t devfn; /* device function */ AMDVIState *iommu_state; /* AMDVI - one per machine */ MemoryRegion root; /* AMDVI Root memory map region */ @@ -101,6 +101,11 @@ typedef enum AMDVIFaultReason { AMDVI_FR_PT_ENTRY_INV, /* Failure to read PTE from guest memory */ } AMDVIFaultReason; =20 +typedef struct amdvi_as_key { + PCIBus *bus; + int devfn; +} amdvi_as_key; + uint64_t amdvi_extended_feature_register(AMDVIState *s) { uint64_t feature =3D AMDVI_DEFAULT_EXT_FEATURES; @@ -382,6 +387,42 @@ static guint amdvi_uint64_hash(gconstpointer v) return (guint)*(const uint64_t *)v; } =20 +static gboolean amdvi_as_equal(gconstpointer v1, gconstpointer v2) +{ + const struct amdvi_as_key *key1 =3D v1; + const struct amdvi_as_key *key2 =3D v2; + + return key1->bus =3D=3D key2->bus && key1->devfn =3D=3D key2->devfn; +} + +static guint amdvi_as_hash(gconstpointer v) +{ + const struct amdvi_as_key *key =3D v; + return (guint)((uint64_t)key->bus | (key->devfn << 24)); +} + +static AMDVIAddressSpace *amdvi_as_lookup(AMDVIState *s, PCIBus *bus, + int devfn) +{ + amdvi_as_key key =3D { .bus =3D bus, .devfn =3D devfn }; + return g_hash_table_lookup(s->address_spaces, &key); +} + +static int amdvi_find_as_by_devid(gpointer key, gpointer value, + gpointer user_data) +{ + amdvi_as_key *as =3D (struct amdvi_as_key *)key; + uint16_t devid =3D *((uint16_t *)user_data); + + return devid =3D=3D PCI_BUILD_BDF(pci_bus_num(as->bus), as->devfn); +} + +static AMDVIAddressSpace *amdvi_get_as_by_devid(AMDVIState *s, uint16_t de= vid) +{ + return g_hash_table_find(s->address_spaces, + amdvi_find_as_by_devid, &devid); +} + static AMDVIIOTLBEntry *amdvi_iotlb_lookup(AMDVIState *s, hwaddr addr, uint64_t devid) { @@ -551,7 +592,7 @@ static inline uint64_t amdvi_get_pte_entry(AMDVIState *= s, uint64_t pte_addr, =20 static int amdvi_as_to_dte(AMDVIAddressSpace *as, uint64_t *dte) { - uint16_t devid =3D PCI_BUILD_BDF(as->bus_num, as->devfn); + uint16_t devid =3D PCI_BUILD_BDF(pci_bus_num(as->bus), as->devfn); AMDVIState *s =3D as->iommu_state; =20 if (!amdvi_get_dte(s, devid, dte)) { @@ -1011,25 +1052,14 @@ static void amdvi_switch_address_space(AMDVIAddress= Space *amdvi_as) */ static void amdvi_reset_address_translation_all(AMDVIState *s) { - AMDVIAddressSpace **iommu_as; - - for (int bus_num =3D 0; bus_num < PCI_BUS_MAX; bus_num++) { - - /* Nothing to do if there are no devices on the current bus */ - if (!s->address_spaces[bus_num]) { - continue; - } - iommu_as =3D s->address_spaces[bus_num]; + AMDVIAddressSpace *iommu_as; + GHashTableIter as_it; =20 - for (int devfn =3D 0; devfn < PCI_DEVFN_MAX; devfn++) { + g_hash_table_iter_init(&as_it, s->address_spaces); =20 - if (!iommu_as[devfn]) { - continue; - } - /* Use passthrough as default mode after reset */ - iommu_as[devfn]->addr_translation =3D false; - amdvi_switch_address_space(iommu_as[devfn]); - } + while (g_hash_table_iter_next(&as_it, NULL, (void **)&iommu_as)) { + iommu_as->addr_translation =3D false; + amdvi_switch_address_space(iommu_as); } } =20 @@ -1089,27 +1119,21 @@ static void enable_nodma_mode(AMDVIAddressSpace *as) */ static void amdvi_update_addr_translation_mode(AMDVIState *s, uint16_t dev= id) { - uint8_t bus_num, devfn, dte_mode; + uint8_t dte_mode; AMDVIAddressSpace *as; uint64_t dte[4] =3D { 0 }; int ret; =20 - /* - * Convert the devid encoded in the command to a bus and devfn in - * order to retrieve the corresponding address space. - */ - bus_num =3D PCI_BUS_NUM(devid); - devfn =3D devid & 0xff; - /* * The main buffer of size (AMDVIAddressSpace *) * (PCI_BUS_MAX) has a= lready * been allocated within AMDVIState, but must be careful to not access * unallocated devfn. */ - if (!s->address_spaces[bus_num] || !s->address_spaces[bus_num][devfn])= { + + as =3D amdvi_get_as_by_devid(s, devid); + if (!as) { return; } - as =3D s->address_spaces[bus_num][devfn]; =20 ret =3D amdvi_as_to_dte(as, dte); =20 @@ -1783,7 +1807,7 @@ static void amdvi_do_translate(AMDVIAddressSpace *as,= hwaddr addr, bool is_write, IOMMUTLBEntry *ret) { AMDVIState *s =3D as->iommu_state; - uint16_t devid =3D PCI_BUILD_BDF(as->bus_num, as->devfn); + uint16_t devid =3D PCI_BUILD_BDF(pci_bus_num(as->bus), as->devfn); AMDVIIOTLBEntry *iotlb_entry =3D amdvi_iotlb_lookup(s, addr, devid); uint64_t entry[4]; int dte_ret; @@ -1858,7 +1882,7 @@ static IOMMUTLBEntry amdvi_translate(IOMMUMemoryRegio= n *iommu, hwaddr addr, } =20 amdvi_do_translate(as, addr, flag & IOMMU_WO, &ret); - trace_amdvi_translation_result(as->bus_num, PCI_SLOT(as->devfn), + trace_amdvi_translation_result(pci_bus_num(as->bus), PCI_SLOT(as->devf= n), PCI_FUNC(as->devfn), addr, ret.translated_addr); return ret; } @@ -2222,30 +2246,28 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *b= us, void *opaque, int devfn) { char name[128]; AMDVIState *s =3D opaque; - AMDVIAddressSpace **iommu_as, *amdvi_dev_as; - int bus_num =3D pci_bus_num(bus); + AMDVIAddressSpace *amdvi_dev_as; + amdvi_as_key *key; =20 - iommu_as =3D s->address_spaces[bus_num]; + amdvi_dev_as =3D amdvi_as_lookup(s, bus, devfn); =20 /* allocate memory during the first run */ - if (!iommu_as) { - iommu_as =3D g_new0(AMDVIAddressSpace *, PCI_DEVFN_MAX); - s->address_spaces[bus_num] =3D iommu_as; - } - - /* set up AMD-Vi region */ - if (!iommu_as[devfn]) { + if (!amdvi_dev_as) { snprintf(name, sizeof(name), "amd_iommu_devfn_%d", devfn); =20 - iommu_as[devfn] =3D g_new0(AMDVIAddressSpace, 1); - iommu_as[devfn]->bus_num =3D (uint8_t)bus_num; - iommu_as[devfn]->devfn =3D (uint8_t)devfn; - iommu_as[devfn]->iommu_state =3D s; - iommu_as[devfn]->notifier_flags =3D IOMMU_NOTIFIER_NONE; - iommu_as[devfn]->iova_tree =3D iova_tree_new(); - iommu_as[devfn]->addr_translation =3D false; + amdvi_dev_as =3D g_new0(AMDVIAddressSpace, 1); + key =3D g_new0(amdvi_as_key, 1); =20 - amdvi_dev_as =3D iommu_as[devfn]; + amdvi_dev_as->bus =3D bus; + amdvi_dev_as->devfn =3D (uint8_t)devfn; + amdvi_dev_as->iommu_state =3D s; + amdvi_dev_as->notifier_flags =3D IOMMU_NONE; + amdvi_dev_as->iova_tree =3D iova_tree_new(); + amdvi_dev_as->addr_translation =3D false; + key->bus =3D bus; + key->devfn =3D devfn; + + g_hash_table_insert(s->address_spaces, key, amdvi_dev_as); =20 /* * Memory region relationships looks like (Address range shows @@ -2288,7 +2310,7 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus= , void *opaque, int devfn) =20 amdvi_switch_address_space(amdvi_dev_as); } - return &iommu_as[devfn]->as; + return &amdvi_dev_as->as; } =20 static const PCIIOMMUOps amdvi_iommu_ops =3D { @@ -2329,7 +2351,7 @@ static int amdvi_iommu_notify_flag_changed(IOMMUMemor= yRegion *iommu, if (!s->dma_remap && (new & IOMMU_NOTIFIER_MAP)) { error_setg_errno(errp, ENOTSUP, "device %02x.%02x.%x requires dma-remap=3D1", - as->bus_num, PCI_SLOT(as->devfn), PCI_FUNC(as->devfn)); + pci_bus_num(as->bus), PCI_SLOT(as->devfn), PCI_FUNC(as->devfn)= ); return -ENOTSUP; } =20 @@ -2510,6 +2532,9 @@ static void amdvi_sysbus_realize(DeviceState *dev, Er= ror **errp) s->iotlb =3D g_hash_table_new_full(amdvi_uint64_hash, amdvi_uint64_equal, g_free, g_free); =20 + s->address_spaces =3D g_hash_table_new_full(amdvi_as_hash, + amdvi_as_equal, g_free, g_free); + /* set up MMIO */ memory_region_init_io(&s->mr_mmio, OBJECT(s), &mmio_mem_ops, s, "amdvi-mmio", AMDVI_MMIO_SIZE); diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index daf82fc85f96..38471b95d153 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -408,7 +408,7 @@ struct AMDVIState { bool mmio_enabled; =20 /* for each served device */ - AMDVIAddressSpace **address_spaces[PCI_BUS_MAX]; + GHashTable *address_spaces; =20 /* list of address spaces with registered notifiers */ QLIST_HEAD(, AMDVIAddressSpace) amdvi_as_with_notifiers; --=20 2.34.1 From nobody Fri Nov 14 22:21:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Physical AMD IOMMU supports upto 64 bits of DMA address. When device tries to read or write from the given DMA address, IOMMU translates the address using page table assigned to that device. Since IOMMU uses per device page tables, the emulated IOMMU should use the cache tag of 68 bits (64 bit address - 12 bit page alignment + 16 device ID). Current emulated AMD IOMMU uses GLib hash table to create software iotlb and uses 64 bit key to store the IOVA and deviceID, which limits the IOVA to 60 bits. This cause failure while setting up the device when guest is booted with "iommu.forcedac=3D1". To solve this problem, define `struct amdvi_iotlb_key` which uses 64 bit IOVA and 16 bit devid as key to store and lookup IOTLB entry. Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU") Signed-off-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 51 ++++++++++++++++++++++++++++----------------- hw/i386/amd_iommu.h | 5 +++-- 2 files changed, 35 insertions(+), 21 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 0a4b4d46d885..5106d9cc4036 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -106,6 +106,11 @@ typedef struct amdvi_as_key { int devfn; } amdvi_as_key; =20 +typedef struct amdvi_iotlb_key { + uint64_t gfn; + uint16_t devid; +} amdvi_iotlb_key; + uint64_t amdvi_extended_feature_register(AMDVIState *s) { uint64_t feature =3D AMDVI_DEFAULT_EXT_FEATURES; @@ -377,16 +382,6 @@ static void amdvi_log_pagetab_error(AMDVIState *s, uin= t16_t devid, PCI_STATUS_SIG_TARGET_ABORT); } =20 -static gboolean amdvi_uint64_equal(gconstpointer v1, gconstpointer v2) -{ - return *((const uint64_t *)v1) =3D=3D *((const uint64_t *)v2); -} - -static guint amdvi_uint64_hash(gconstpointer v) -{ - return (guint)*(const uint64_t *)v; -} - static gboolean amdvi_as_equal(gconstpointer v1, gconstpointer v2) { const struct amdvi_as_key *key1 =3D v1; @@ -423,11 +418,27 @@ static AMDVIAddressSpace *amdvi_get_as_by_devid(AMDVI= State *s, uint16_t devid) amdvi_find_as_by_devid, &devid); } =20 +static gboolean amdvi_iotlb_equal(gconstpointer v1, gconstpointer v2) +{ + const amdvi_iotlb_key *key1 =3D v1; + const amdvi_iotlb_key *key2 =3D v2; + + return key1->devid =3D=3D key2->devid && key1->gfn =3D=3D key2->gfn; +} + +static guint amdvi_iotlb_hash(gconstpointer v) +{ + const amdvi_iotlb_key *key =3D v; + /* Use GPA and DEVID to find the bucket */ + return (guint)(key->gfn << AMDVI_PAGE_SHIFT_4K | + (key->devid & ~AMDVI_PAGE_MASK_4K)); +} + + static AMDVIIOTLBEntry *amdvi_iotlb_lookup(AMDVIState *s, hwaddr addr, uint64_t devid) { - uint64_t key =3D (addr >> AMDVI_PAGE_SHIFT_4K) | - ((uint64_t)(devid) << AMDVI_DEVID_SHIFT); + amdvi_iotlb_key key =3D {devid, AMDVI_GET_IOTLB_GFN(addr)}; return g_hash_table_lookup(s->iotlb, &key); } =20 @@ -449,8 +460,7 @@ static gboolean amdvi_iotlb_remove_by_devid(gpointer ke= y, gpointer value, static void amdvi_iotlb_remove_page(AMDVIState *s, hwaddr addr, uint64_t devid) { - uint64_t key =3D (addr >> AMDVI_PAGE_SHIFT_4K) | - ((uint64_t)(devid) << AMDVI_DEVID_SHIFT); + amdvi_iotlb_key key =3D {devid, AMDVI_GET_IOTLB_GFN(addr)}; g_hash_table_remove(s->iotlb, &key); } =20 @@ -461,8 +471,10 @@ static void amdvi_update_iotlb(AMDVIState *s, uint16_t= devid, /* don't cache erroneous translations */ if (to_cache.perm !=3D IOMMU_NONE) { AMDVIIOTLBEntry *entry =3D g_new(AMDVIIOTLBEntry, 1); - uint64_t *key =3D g_new(uint64_t, 1); - uint64_t gfn =3D gpa >> AMDVI_PAGE_SHIFT_4K; + amdvi_iotlb_key *key =3D g_new(amdvi_iotlb_key, 1); + + key->gfn =3D AMDVI_GET_IOTLB_GFN(gpa); + key->devid =3D devid; =20 trace_amdvi_cache_update(domid, PCI_BUS_NUM(devid), PCI_SLOT(devid= ), PCI_FUNC(devid), gpa, to_cache.translated_addr); @@ -475,7 +487,8 @@ static void amdvi_update_iotlb(AMDVIState *s, uint16_t = devid, entry->perms =3D to_cache.perm; entry->translated_addr =3D to_cache.translated_addr; entry->page_mask =3D to_cache.addr_mask; - *key =3D gfn | ((uint64_t)(devid) << AMDVI_DEVID_SHIFT); + entry->devid =3D devid; + g_hash_table_replace(s->iotlb, key, entry); } } @@ -2529,8 +2542,8 @@ static void amdvi_sysbus_realize(DeviceState *dev, Er= ror **errp) } } =20 - s->iotlb =3D g_hash_table_new_full(amdvi_uint64_hash, - amdvi_uint64_equal, g_free, g_free); + s->iotlb =3D g_hash_table_new_full(amdvi_iotlb_hash, + amdvi_iotlb_equal, g_free, g_free); =20 s->address_spaces =3D g_hash_table_new_full(amdvi_as_hash, amdvi_as_equal, g_free, g_free); diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 38471b95d153..8089f9472ac4 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -220,8 +220,9 @@ #define PAGE_SIZE_PTE_COUNT(pgsz) (1ULL << ((ctz64(pgsz) - 12) % 9)) =20 /* IOTLB */ -#define AMDVI_IOTLB_MAX_SIZE 1024 -#define AMDVI_DEVID_SHIFT 36 +#define AMDVI_IOTLB_MAX_SIZE 1024 +#define AMDVI_IOTLB_DEVID_SHIFT 48 +#define AMDVI_GET_IOTLB_GFN(addr) (addr >> AMDVI_PAGE_SHIFT_4K) =20 /* default extended feature */ #define AMDVI_DEFAULT_EXT_FEATURES \ --=20 2.34.1