From nobody Fri Nov 14 23:29:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1759893885; cv=none; d=zohomail.com; s=zohoarc; b=OSzvIKxf9EjB3LYPVGLD/TYa/AScnlzpA4sEo9Eutmr+1QdL1kDicG3Ux0G6x9O9xuaUrFAPZQNFzYtY5RUgtcW890mNcORaFaxJzxSMQWRldvG8W++12arkDcBS58QfMS4d8BPu+JJVp/o1ha0hchY2mQzXQ+pMH6e4WxkNF+E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1759893885; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=trcEVJG7T4qfStOHOh2SPg2cDW0Kd9ZPjtGUgWCmZNM=; b=LZ3qNoplHZDgiUFZjt3HzXRUuzTWzViuKqLeCQkmKner3tCQZ07yt2AgdAK7LecyQwNWbh4wOJB9AUfstbKKLB73aaTNQfnCfWlh6KCjNVkzENWMZJusJ3fpecY0QX4KVVtRyx6XOJoCDdVNIXZ8G9qaiIWv3nqqtWlaluUUgiA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759893885197866.5574183402011; Tue, 7 Oct 2025 20:24:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v6KlJ-0001rn-8X; Tue, 07 Oct 2025 23:22:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v6KlH-0001rX-M0; Tue, 07 Oct 2025 23:22:43 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v6KlF-0000T8-DC; Tue, 07 Oct 2025 23:22:43 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 8 Oct 2025 11:22:10 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 8 Oct 2025 11:22:10 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 08/16] hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_soc_uart_realize() API Date: Wed, 8 Oct 2025 11:21:53 +0800 Message-ID: <20251008032207.593353-9-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251008032207.593353-1-jamin_lin@aspeedtech.com> References: <20251008032207.593353-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759893887173116600 Content-Type: text/plain; charset="utf-8" Refactor aspeed_soc_uart_realize() to take MemoryRegion *, SerialMM *, and MMIO base addr instead of AspeedSoCState *, decoupling the helper from SoC state and making it reusable per-UART. The helper now realizes a single UART instance and maps its MMIO. IRQ wiring and iteration over all UARTs are moved to callers. Update call sites in AST1030, AST2400, AST2600, AST27x0 SSP/TSP, and AST2700 to loop over UARTs, call the new helper, and connect IRQ via aspeed_soc_get_irq(sc->get_irq, s, uart). This simplifies the UART realize path and reduces cross-module coupling. No functional change. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 3 ++- hw/arm/aspeed_ast10x0.c | 10 ++++++++-- hw/arm/aspeed_ast2400.c | 10 ++++++++-- hw/arm/aspeed_ast2600.c | 10 ++++++++-- hw/arm/aspeed_ast27x0-ssp.c | 10 ++++++++-- hw/arm/aspeed_ast27x0-tsp.c | 10 ++++++++-- hw/arm/aspeed_ast27x0.c | 10 ++++++++-- hw/arm/aspeed_soc_common.c | 29 ++++++++++------------------- 8 files changed, 60 insertions(+), 32 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 427708c087..3cd9ad189f 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -305,7 +305,8 @@ enum { const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); qemu_irq aspeed_soc_get_irq(qemu_irq (*fn)(void *ctx, int dev), void *ctx, int dev); -bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); +bool aspeed_soc_uart_realize(MemoryRegion *memory, SerialMM *smm, + const hwaddr addr, Error **errp); void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base, int uarts_num, Chardev *chr); bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 3ce866c66a..80e0da526c 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -193,6 +193,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); DeviceState *armv7m; Error *err =3D NULL; + int uart; int i; g_autofree char *sram_name =3D NULL; =20 @@ -317,8 +318,13 @@ static void aspeed_soc_ast1030_realize(DeviceState *de= v_soc, Error **errp) sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); =20 /* UART */ - if (!aspeed_soc_uart_realize(s, errp)) { - return; + for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { + if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], + sc->memmap[uart], errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + aspeed_soc_get_irq(sc->get_irq, s, uart)); } =20 /* Timer */ diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index 2910c40807..33736a8988 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -252,6 +252,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) AspeedSoCState *s =3D ASPEED_SOC(dev); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); g_autofree char *sram_name =3D NULL; + int uart; =20 /* Default boot region (SPI memory or ROMs) */ memory_region_init(&s->spi_boot_container, OBJECT(s), @@ -339,8 +340,13 @@ static void aspeed_ast2400_soc_realize(DeviceState *de= v, Error **errp) aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_ADC)); =20 /* UART */ - if (!aspeed_soc_uart_realize(s, errp)) { - return; + for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { + if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], + sc->memmap[uart], errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + aspeed_soc_get_irq(sc->get_irq, s, uart)); } =20 /* I2C */ diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index cd14dc95bb..80570698fb 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -363,6 +363,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); qemu_irq irq; g_autofree char *sram_name =3D NULL; + int uart; =20 /* Default boot region (SPI memory or ROMs) */ memory_region_init(&s->spi_boot_container, OBJECT(s), @@ -489,8 +490,13 @@ static void aspeed_soc_ast2600_realize(DeviceState *de= v, Error **errp) aspeed_soc_get_irq(sc->get_irq, s, ASPEED_DEV_ADC)); =20 /* UART */ - if (!aspeed_soc_uart_realize(s, errp)) { - return; + for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { + if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], + sc->memmap[uart], errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + aspeed_soc_get_irq(sc->get_irq, s, uart)); } =20 /* I2C */ diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index e63a4b3ad3..57dd588af4 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -165,6 +165,7 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *= dev_soc, Error **errp) AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); DeviceState *armv7m; g_autofree char *sram_name =3D NULL; + int uart; int i; =20 if (!clock_has_source(s->sysclk)) { @@ -238,8 +239,13 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState = *dev_soc, Error **errp) qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i= )); } /* UART */ - if (!aspeed_soc_uart_realize(s, errp)) { - return; + for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { + if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], + sc->memmap[uart], errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + aspeed_soc_get_irq(sc->get_irq, s, uart)); } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl), diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 9537ce121c..28376b3338 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -165,6 +165,7 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *= dev_soc, Error **errp) AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); DeviceState *armv7m; g_autofree char *sram_name =3D NULL; + int uart; int i; =20 if (!clock_has_source(s->sysclk)) { @@ -238,8 +239,13 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState = *dev_soc, Error **errp) qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i= )); } /* UART */ - if (!aspeed_soc_uart_realize(s, errp)) { - return; + for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { + if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], + sc->memmap[uart], errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + aspeed_soc_get_irq(sc->get_irq, s, uart)); } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl), diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 9a53f51ec5..de2b4277ce 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -688,6 +688,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) AspeedINTCClass *icio =3D ASPEED_INTC_GET_CLASS(&a->intc[1]); g_autofree char *name =3D NULL; qemu_irq irq; + int uart; =20 /* Default boot region (SPI memory or ROMs) */ memory_region_init(&s->spi_boot_container, OBJECT(s), @@ -789,8 +790,13 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) sc->memmap[ASPEED_DEV_SCUIO]); =20 /* UART */ - if (!aspeed_soc_uart_realize(s, errp)) { - return; + for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { + if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], + sc->memmap[uart], errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + aspeed_soc_get_irq(sc->get_irq, s, uart)); } =20 /* FMC, The number of CS is set at the board level */ diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index 2bd872d9a6..6bb8ed730f 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -36,28 +36,19 @@ qemu_irq aspeed_soc_get_irq(qemu_irq (*fn)(void *ctx, i= nt dev), return fn(ctx, dev); } =20 -bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp) +bool aspeed_soc_uart_realize(MemoryRegion *memory, SerialMM *smm, + const hwaddr addr, Error **errp) { - AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); - SerialMM *smm; - - for (int i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uar= t++) { - smm =3D &s->uart[i]; - - /* Chardev property is set by the machine. */ - qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); - qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400); - qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2); - qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIA= N); - if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) { - return false; - } - - sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, - aspeed_soc_get_irq(sc->get_irq, s, uart)); - aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart= ]); + /* Chardev property is set by the machine. */ + qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); + qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400); + qdev_set_legacy_instance_id(DEVICE(smm), addr, 2); + qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); + if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) { + return false; } =20 + aspeed_mmio_map(memory, SYS_BUS_DEVICE(smm), 0, addr); return true; } =20 --=20 2.43.0