From nobody Fri Nov 14 23:29:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1759893844; cv=none; d=zohomail.com; s=zohoarc; b=VT1CCtplq5n083nGZHTHoRzWzFRPBUOKz8tWnSKg1jX80Rnr5I2umKhmqhj2Cvw7pP+GYXB9o30h1yS/KGWyIuXXJ+0VSMfATqY4GHo8v2LYE7TBCF4mSFRuVO/qrT3+CJdQrn8Z5HRzovDywtFAoWkddFaPsm+nqZJ33tWkbiw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1759893844; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Tn+QKS76OL6nMGNvwvZNmQSx4y9dNhYFBjBI9PMn1TE=; b=VZAeI/Rp4uGcPMDMGquY3NEBmJdM9GIRW7aWgEzksGBiVHMEeTXTQlx18z4WxqIepQUb0qMeDeRr2sN0wxboGGgbpciRsdJeKVfBM8kdqX6+x487R6c7oJ6kb1PCAon+ouUBSeCNGkzNbGDQgDzmrx+39wfDD0rwO7rX+IIQVc0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1759893844296835.3242562038586; Tue, 7 Oct 2025 20:24:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v6Klw-0002Ri-0J; Tue, 07 Oct 2025 23:23:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v6Klo-0002KO-83; Tue, 07 Oct 2025 23:23:16 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v6Kll-0000bG-7G; Tue, 07 Oct 2025 23:23:15 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 8 Oct 2025 11:22:13 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 8 Oct 2025 11:22:13 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 15/16] hw/arm/aspeed_ast27x0-tsp: Rename type to TYPE_ASPEED27X0TSP_COPROCESSOR Date: Wed, 8 Oct 2025 11:22:00 +0800 Message-ID: <20251008032207.593353-16-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251008032207.593353-1-jamin_lin@aspeedtech.com> References: <20251008032207.593353-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1759893847963116600 Content-Type: text/plain; charset="utf-8" Rename the AST27x0 TSP type from TYPE_ASPEED27X0TSP_SOC to TYPE_ASPEED27X0TSP_COPROCESSOR to align with the naming convention used for the SSP coprocessor (TYPE_ASPEED27X0SSP_COPROCESSOR). This change clarifies that TSP is implemented as a coprocessor rather than a full SoC. This ensures consistent terminology between SSP and TSP components and improves clarity within the coprocessor subsystem code. No functional change. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_coprocessor.h | 4 ++-- hw/arm/aspeed_ast27x0-fc.c | 3 ++- hw/arm/aspeed_ast27x0-tsp.c | 10 +++++----- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h index 77159c230b..d274e8e20e 100644 --- a/include/hw/arm/aspeed_coprocessor.h +++ b/include/hw/arm/aspeed_coprocessor.h @@ -55,8 +55,8 @@ struct Aspeed27x0CoprocessorState { OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0CoprocessorState, ASPEED27X0SSP_COPROCESSOR) =20 -#define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc" +#define TYPE_ASPEED27X0TSP_COPROCESSOR "aspeed27x0tsp-coprocessor" DECLARE_OBJ_CHECKERS(Aspeed27x0CoprocessorState, AspeedCoprocessorClass, - ASPEED27X0TSP_SOC, TYPE_ASPEED27X0TSP_SOC) + ASPEED27X0TSP_COPROCESSOR, TYPE_ASPEED27X0TSP_COPROCE= SSOR) =20 #endif /* ASPEED_COPROCESSOR_H */ diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index 67982d2fa0..a61ecff390 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -149,7 +149,8 @@ static bool ast2700fc_tsp_init(MachineState *machine, E= rror **errp) s->tsp_sysclk =3D clock_new(OBJECT(s), "TSP_SYSCLK"); clock_set_hz(s->tsp_sysclk, 200000000ULL); =20 - object_initialize_child(OBJECT(s), "tsp", &s->tsp, TYPE_ASPEED27X0TSP_= SOC); + object_initialize_child(OBJECT(s), "tsp", &s->tsp, + TYPE_ASPEED27X0TSP_COPROCESSOR); memory_region_init(&s->tsp_memory, OBJECT(&s->tsp), "tsp-memory", UINT64_MAX); =20 diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index c00f7d056c..8d3d457919 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -1,5 +1,5 @@ /* - * ASPEED Ast27x0 TSP SoC + * ASPEED Ast27x0 TSP Coprocessor * * Copyright (C) 2025 ASPEED Technology Inc. * @@ -108,7 +108,7 @@ static struct nvic_intc_irq_info ast2700_tsp_intcmap[] = =3D { static qemu_irq aspeed_soc_ast27x0tsp_get_irq(void *ctx, int dev) { AspeedCoprocessorState *s =3D (AspeedCoprocessorState *)ctx; - Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_SOC(s); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_COPROCESSOR(s); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); =20 int or_idx; @@ -130,7 +130,7 @@ static qemu_irq aspeed_soc_ast27x0tsp_get_irq(void *ctx= , int dev) =20 static void aspeed_soc_ast27x0tsp_init(Object *obj) { - Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_SOC(obj); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_COPROCESSOR(obj); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(obj); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); int i; @@ -161,7 +161,7 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj) =20 static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **er= rp) { - Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_SOC(dev_soc); + Aspeed27x0CoprocessorState *a =3D ASPEED27X0TSP_COPROCESSOR(dev_soc); AspeedCoprocessorState *s =3D ASPEED_COPROCESSOR(dev_soc); AspeedCoprocessorClass *sc =3D ASPEED_COPROCESSOR_GET_CLASS(s); DeviceState *armv7m; @@ -287,7 +287,7 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClas= s *klass, const void *dat =20 static const TypeInfo aspeed_soc_ast27x0tsp_types[] =3D { { - .name =3D TYPE_ASPEED27X0TSP_SOC, + .name =3D TYPE_ASPEED27X0TSP_COPROCESSOR, .parent =3D TYPE_ASPEED_COPROCESSOR, .instance_size =3D sizeof(Aspeed27x0CoprocessorState), .instance_init =3D aspeed_soc_ast27x0tsp_init, --=20 2.43.0